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System On Chip

Team leader: Marie-Minerve Louërat Bldg 24-25, room  308

 

The department is a major academic contributor in the field of System on Chip. It brings together a hundred people, including thirty academic staff from « Université Pierre et Marie Curie » (UPMC) and « Centre National de la Recherche Scientifique » CNRS. Our research activities are organised into four main area:

  • many core architectures contain hundreds or thousands of heterogeneous cores. They are studied following software aspects (data-flow modelling and co design of software and hardware), execution environments (operating systems tailored to many core architectures) and hardware architectures.

  • structure of dynamic systems changes over time. The department is studying in particular the design of low power wireless sensor networks and receivers for Software Radio. Reconfigurable architectures are also addressed by integrating them into chips and for specific applications such as cryptography.

  • heterogeneous systems bring together, in a multi-physic context, software and digital functions, analog, MEMS and RF. The study of their modelling and simulation using SystemC-AMS and their prototyping is a transverse axis of the department.

  • safety and reliability of SoC are studied: hardware verification methods based on Model-checking, the study of power supply noise and clock synchronisation are addressed.

These four axis find applications in transport and health.

Teams

  • ALSOC - Integrated on chip multiprocessor systems, real time systems, formal verification systems and generating optimized code for a target architecture.
  • CIAN - architectures, methods and tools for the modelling, the simulation, the design and the verification of mixed and heterogeneous circuits.
  • QI - Quantum Information.
  • SYEL -  modeling performance of heterogeneous systems,  signal integrity, low power wireless sensor network, software radio and e-health applications.
LIP6 LIP6-SoC LIP6 CNRS UPMC