Publications

Mathieu Rosière, Jean-Lou Desbarbieux, Nathalie Drach and Franck Wajsburt

An Out-of-Order Superscalar Processor on FPGA: The ReOrder Buffer Design

IEEE, 2012.

Antoine Lévêque, François Pêcheux, Marie-Minerve Louërat, Hassan Aboushady, Fabio Cenni, Serge Scotti, Abdelbasset Massouri and Laurent Clavier

Holistic Modeling of Heterogeneous Embedded Systems with High Multi-Discipline Feedback: Application to a Precollision Mitigation Braking System

in Design, Automation and Test in Europe (DATE), Dresden, 2012.

Ahmed Ashry and Hassan Aboushady

A 3.6GS/s, 15mW, 50dB SNDR, 28MHz bandwidth RF ΣΔ ADC with a FoM of 1pJ/bit in 130nm CMOS

in Custom Integrated Circuits Conference (CICC'11), pages 1-4, 2011.

Ahmed Ashry and Hassan Aboushady

A 4th Order Subsampled RF ΣΔ ADC Centered at 2.4GHz with a Sine-Shaped Feedback DAC

in European Solid-State Circuits Conference (ESSCIRC'11), pages 263-266, 2011.

Jean-Michel Akré, Eldar Zianbetov, Mohammad Javidan, François Anceau, Mehdi Terosiet, Sylvain Feruglio, Dimitri Galayko, Olivier Romain, Éric Colinet and Jérôme Juillard

A Design Approah for Networks of self-Sampled All-Digital Phase-Locked Loops

in 20th European Conference on Circuit theory and Design (ECCTD'11),, pages 795-798, 2011.

Stéphanie Youssef, Farakh Javid, Damien Dupuis, Ramy Iskander and Marie-Minerve Louërat

A Python-Based Layout-Aware Analog Design Methodology For Nanometric Technologies

in The 6th IEEE International Design and Test Workshop, (IDT), Beirut, Lebanon, 2011.

Stéphanie Youssef, Farakh Javid, Damien Dupuis, Ramy Iskander and Marie-Minerve Louërat

A Seamless Representation for Coupling Transistor Sizing with Nanometric CMOS Layout Generation

in 20th European Conference on Circuit Theory and Design (ECCTD), Linkoping, Sweden, pages 341-344, 2011.

Mehdi Terosiet, Sylvain Feruglio, Farouk Vallette, Patrick Garda, Olivier Romain and Julien Le Kernec

A Self-Sufficient Digitally Controlled Ring Oscillator Compensated for Supply Voltage Variation

in The IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Beirut, Liban, 2011.

Stéphanie Youssef, Damien Dupuis, Ramy Iskander and Marie-Minerve Louërat

A Stack-Based Routing Methodology For Nanometric Analogue CMOS Devices

in The IEEE Virtual Worldwide Forum For PhD Researchers in Electronic Design Automation, (VW FEDA), 2011.

Stéphanie Youssef, Damien Dupuis, Ramy Iskander and Marie-Minerve Louërat

A Stack-Based Routing Methodology For Nanometric CMOS Devices

in IEEE MOS-AK/GSA Workshop, Paris, 2011.

Mohammad Javidan, Eldar Zianbetov, François Anceau, Dimitri Galayko, Éric Colinet and Jérôme Juillard

A novel technique to reduce the metastability of Bang-Bang Phase Frequency Detectors

in Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, pages 2577-2580, 2011.

Mohammad Javidan, Eldar Zianbetov, François Anceau, Dimitri Galayko, Anton Korniienko, Éric Colinet, Gérard Scorletti, Jean-Michel Akré and Jérôme Juillard

All-digital PLL array provides reliable distributed clock for SOCs

in Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, pages 2589-2592, 2011.

Mehdi Terosiet, Sylvain Feruglio, Dimitri Galayko and Patrick Garda

An Analytical Model Of The Oscillation Period For Tri-State Inverter Based DCO

in The IEEE International Conference on Microelectronics (ICM), Hammamet, Tunisie, 2011.

Farakh Javid, Ramy Iskander, Marie-Minerve Louërat and Damien Dupuis

Analog Circuits Sizing Using Bipartite Graphs

in IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Seoul, South Korea, pages 1-4, 2011.

Umer Farooq, Husain Parvez, Zied Marrakchi and Habib Mehrez

Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA

ARC 2011, 2011.

Dimitri Galayko, Raphaël Guillemet, Andrii Dudka and Philippe Basset

Comprehensive dynamic and stability analysis of electrostatic Vibration Energy Harvester (E-VEH)

in Solid-State Sensors, Actuators and Microsystems Conference (TRANSDUCERS), 2011 16th International, pages 2382-2385, 2011.

Anton Korniienko, Gérard Scorletti, Éric Colinet, Eric Blanco, Jérôme Juillard and Dimitri Galayko

Control Law Synthesis for Distributed Multi-Agent Systems: Application to Active Clock Distribution Networks

in American Control Conference, 2011.

Serge Scotti, Martin Barnasconi, Marie-Minerve Louërat and Emmanuel Vaumorin

Design Refinement of Embedded Analogue and Mixed Signal System

in CATRENE DTC conference and EdaForum, Dresden, 2011.

Emna Amouri, Zied Marrakchi and Habib Mehrez

Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA

ReCoSoC 2011, 2011.

Hélder R. Florentino, Raimundo C. S. Freire, Alan V. S. Sá, Caio Florentino and Dimitri Galayko

Electrostatic vibration energy harvester with piezoelectric start-up generator

in Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, pages 1343-1346, 2011.

Umer Farooq, Husain Parvez, Emna Amouri, Habib Mehrez and Zied Marrakchi

Exploring the Effect of LUT and Arity Size on a Tree-based Application Specific Inflexible FPGA

in International conference on Design & Technology of Integrated Systems (DTIS), Athens, pages 1-6, 2011.

Chuan Shan, Eldar Zianbetov, Mohammad Javidan, François Anceau, Mehdi Terosiet, Sylvain Feruglio, Dimitri Galayko, Olivier Romain, Éric Colinet and Jérôme Juillard

FPGA Implementation of Reconfigurable ADPLL Network for Distributed Clock Generation

in accepted in 2011 International Conference on Field Programmable Technology, 2011.

Ramy Iskander and Marie-Minerve Louërat

Hierarchical Sizing and Biasing of Analog Firm Intellectual Properties

in IEEE MOS-AK/GSA Workshop, Paris, 2011.

Bruno Robisson, Michel Agoyan, Sébastien Le Henaff, Patrick Soquet, Guillaume Phan, Franck Wajsburt and Pirouz Bazargan Sabet

Implementation of complex strategies of security in secure embedded systems

in NTMS IFIP International Conference on New Technologies, Mobility and Security, Paris, France, 2011.

Zhen Zhang, Dimitri Refauvelet, Alain Greiner, Mounir Benabdenbi and François Pêcheux

Localization of Damaged Resources in NoC Based Shared-Memory MP2SOC, using a Distributed Cooperative Configuration Infrastructure

in VTS IEEE VLSI Test Symposium, 2011.

Hussain Adel, Marie-Minerve Louërat, Hugo Gicquel and Marc Sabut

Low Voltage Techniques for Pipelined A/D Converters

in Colloque GDR SOC SIP, Lyon, 2011.

Minh Huu Nguyen, Bruno Robisson, Michel Agoyan and Nathalie Drach

Low-cost recovery for the code integrity protection in secure embedded processors

in HOST IEEE International Symposium IEEE International Symposium on Hardware-Oriented Security and Trust, San Diego, Etats-Unis, 2011.

Mathieu Rosière, Jean-Lou Desbarbieux, Nathalie Drach and Franck Wajsburt

MORPHEO: a high-performance processor generator for a FPGA implementation

IEEE, 2011.

Bruno Robisson, Michel Agoyan, Sylvain Bouquet, Minh Huu Nguyen, Sébastien Le Henaff, Patrick Soquet, Guillaume Phan, Franck Wajsburt, Pirouz Bazargan Sabet and Nathalie Drach

Management of the security in smart secure devices

in SSI Smart Systems Integration Conference, Zurich, Suisse, 2011.

Daniela Genius and Nicolas Pouillon

Monitoring Software Communication Channels on a Shared Memory Multi-Processor System on Chip

in ReCoSoC Reconfigurable Communication-centric SoCs, Montpellier, France, 2011.

Joël Porquet, Alain Greiner and Christian Schwarz

NoC-MPU: A Secure Architecture for Flexible Co-Hosting on Shared Memory MPSoCs

in DATE Design Automation and Test in Europe Conference Grenoble, France, March 2011, Grenoble, France, pages 591-594, 2011.

Mahmoud Abdoallah, Mohamed Dessouky, Marie-Minerve Louërat, Hugo Gicquel and Abdel Halim Shousha

Pipelined ADC Design Exploration Methodology Employing Circuit-System Refinement

in IEEE Electronics, Communications and Photonics Conference (SIECPC), Riyadh, pages 1-4, 2011.

Olivier Romain, Johan Mazeyrat, Patrick Garda, Hakeim Talleb, David Lautru, Man-Faï Wong, Joe Wiart, Victor Fouad Hanna, Pierre-Yves Lagrée, Michel Bonneau, Chantal Kang, Miguel Fernandez, Jean-Frédéric Gerbeau, Valérie Deplano, Bernard Berthier, Cécile Legallais and Pascal Leprince

RFID implantable pressure sensor for the follow-up of abdominal aortic aneurysm stented

in International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2011, pages 1-6, 2011.

Stéphanie Youssef, Damien Dupuis, Ramy Iskander and Marie-Minerve Louërat

Routing Methodology For Nanometric Analog CMOS Devices

in , Lyon, 2011.

Ahmed Ashry and Hassan Aboushady

Sine-Shaping Mixer for Continuous-Time ΣΔ ADCs

in IEEE International Symposium on Circuits and Systems (ISCAS'11), pages 1113-1116, 2011.

Sophie Belloeil-Dupuis, Roselyne Chotin-Avot and Habib Mehrez

Stratus: Free design of highly parametrized VLSI modules interoperable with commercial tools

in ISQED International Symposium on Quality Electronic Design, Santa Clara, California, USA, pages 502-507, 2011.

Farakh Javid, Ramy Iskander, Marie-Minerve Louërat and Damien Dupuis

Using Compact MOS Models for Hierarchical Sizing and Biasing of Analog IPs

in IEEE MOS-AK/GSA Workshop, 2011.

Oussama Gamoudi, Nathalie Drach and Karine Heydemann

Using runtime activity to dynamically filter out inefficient data prefetches

in Euro-Par European Conference on Parallel computing, Bordeaux, France, pages 338-350, 2011.

Jad Ayoub, Bertrand Granado, Olivier Romain and Yasser Mhanna

3-D object recognition based on SVM and stereo-vision: Application in endoscopic imaging

in International Conference of Soft Computing and Pattern Recognition (SoCPaR), 2010, pages 198-201, 2010.

Farakh Javid, Ramy Iskander, Marie-Minerve Louërat and Damien Dupuis

A Design Environment for Analog IPs Design Knowledge Capture and Migration

in Colloque GDR SOC-SIP : System-On-Chip, System-In-Package, Paris, France, 2010.

Ahmed Ashry and Hassan Aboushady

A Generalized Approach to Design CT ΣΔ Ms based on FIR DAC

in ISCAS IEEE International Symposium on Circuits and Systems, pages 21-24, 2010.

Mohamed Benazouz, Olivier Marchetti, Alix Munier-Kordon and P. Urard

A New Approach for Minimizing Buffer Capacities with Throughput Constraint for Embedded System Design

in AICCSA IEEE/ACS International Conference on Computer Systems and Applications, Hammamet, Tunisie, pages 1-6, 2010.

Umer Farooq, Zied Marrakchi and Habib Mehrez

A New Datapath-Oriented Tree-based FPGA Architecture

in IEEE International Conference on Microelectronics (ICM), Cairo, Egypt, pages 403-406, 2010.

Mohamed Benazouz, Olivier Marchetti, Alix Munier-Kordon and T. Michel

A New Method for Minimizing Buffer Sizes for Cyclo-Static Dataflow Graphs

in ESTIMedia IEEE International Workshop on Embedded Systems for Real-Time Multimedia, Scottsdale, Arizona, USA, pages 1-6, 2010.

Stéphanie Youssef, Damien Dupuis, Ramy Iskander and Marie-Minerve Louërat

A Python-Based Analog Layout Generation Tool For Nanometer CMOS Technologies

in Colloque GDR SOC-SIP : System-On-Chip, System-In-Package, Paris, France, 2010.

Anton Korniienko, Éric Colinet, Gérard Scorletti, Eric Blanco, Dimitri Galayko and Jérôme Juillard

A clock network of distributed ADPLLs using an asymmetric comparison strategy

in ISCAS IEEE International Symposium on Circuits and Systems, Paris, France, pages 3212-3215, 2010.

Sami Taktak, Emmanuelle Encrenaz and Jean-Lou Desbarbieux

A polynomial algorithm to prove deadlock-freeness of wormhole networks

in PDP EUROMICRO Conference on Parallel, Distributed and Network-based Computing IEEE Computer Society, Pisa, Italy, pages 121-128, 2010.

Husain Parvez, Zied Marrakchi and Habib Mehrez

Application Specific FPGA Using Heterogeneous Logic Blocks

in ARC International Symposium on Applied Reconfigurable Computing, Bangkok, Thailand, pages 92-109, 2010.

D. Belfort and Hassan Aboushady

Automatic Design of RF Linear Transconductor

in LASCAS IEEE Circuits and Systems Society Latin American Symposium on Circuits and Systems, Foz do Iguaçu, Brésil, 2010.

Stéphanie Youssef, Damien Dupuis, Ramy Iskander and Marie-Minerve Louërat

Automatic Stress Effects Computation Based On A Layout Generation Tool For Analog IC

in IEEE International Behavioral Modeling and Simulation Conference (BMAS), San Jose, California, Etats Unis, pages 7-12, 2010.

Abdelbasset Massouri, Antoine Lévêque, Laurent Clavier, Michel Vasilevski, Andreas Kaiser and Marie-Minerve Louërat

Baseband Fading Channel Simulator for Inter-vehicle Communication using SystemC-AMS

in IEEE International Behavioral Modeling and Simulation Conference (BMAS), San Jose, Californie, USA, 2010.

Raphaël Guillemet, Philippe Basset, Dimitri Galayko and Tarik Bourouina

Combined optimization of electrical and mechanical parameters of an out-of-plane gap-closing electrostatic Vibration Energy Harvester (VEH)

in DTIP' Symposium on Design, Test, Integration & Packaging of MEMS/MOEMS 2009, Sevilla, Spain, pages 73-78, 2010.

Raphaël Guillemet, Philippe Basset, Dimitri Galayko and Tarik Bourouina

Combined optimization of electrical and mechanical parameters of in-plane and out-of-plane gap-closing electrostatic Vibration Energy Harvesters (VEHs)

in EUROSENSORS European Conference on sensors, actuators and microsystems, Linz, Austria, 2010.

Mootaz Allam, Hassan Aboushady and Marie-Minerve Louërat

Continuous-Time Sigma-Delta Modulators With VCO-Based Voltage-to-Phase and Volage-to-Frequency Quantizers

in Midwest Symposium on Circuits and Systems (MWSCAS), Seattle, Etats-Unis, pages 676-679, 2010.

Zied Guitouni, Roselyne Chotin-Avot, Mohsen Machhout, Habib Mehrez and Rached Tourki

Design and FPGA Implementation of Modular Multiplication Methods Using Cellular Automata

in DTIS IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Hammamet, Tunisie, pages 1-5, 2010.

Raouf Khalil, Mootaz Allam, Ramy Iskander and Marie-Minerve Louërat

Design and Modeling of 8-Bit Successive Approximation Analog to Digital Converter

in Colloque GDR SOC-SIP : System-On-Chip, System-In-Package, Paris, France, 2010.

Raouf Khalil, Andrii Dudka, Dimitri Galayko, Ramy Iskander and Philippe Basset

Design and Modeling of a Successive Approximation ADC for the Electrostatic Harvester of Vibration Energy

in BMAS IEEE International Behavioral Modeling and Simulation Conference, California, états unis, pages 57-62, 2010.

Eldar Zianbetov, Mohammad Javidan, François Anceau, Dimitri Galayko, Éric Colinet and Jérôme Juillard

Design and VHDL Modeling of All-Digital PLLs

in NEWCAS IEEE International Conference on NEWCAS, Montréal, Canada, 2010.

Hussain Adel, Mohamed Dessouky, Marie-Minerve Louërat, Hugo Gicquel and Hisham Haddara

Foreground Digital Calibration of Non-Linear Errors in Pipelined A/D Converters

in IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France, pages 569-572, 2010.

Abdelrezzak Bara, Pirouz Bazargan Sabet, Rémy Chevallier, Emmanuelle Encrenaz, Dominique Le Dû and Patricia Renault

Formal Verification of Timed VHDL Programs

in FDL Forum on Specification & Design Languages, Southampton, UK, pages 80-85, 2010.

Husain Parvez, Zied Marrakchi and Habib Mehrez

Heterogeneous-ASIF: An Application Specific Inflexible FPGA using Heterogeneous logic blocks

in FPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, California, USA, pages 290-290, 2010.

Raouf Khalil, Andrii Dudka, Dimitri Galayko and Philippe Basset

High-voltage low power analogue-to-digital conversion for adaptive architectures of capacitive vibration energy harvesters

in PowerMEMS Workshop on Micro and Nanotechnology for Power Generation and Energy Conversion Applications, Leuven, Belgique, 2010.

Ahmed Ashry and Hassan Aboushady

Jitter Analysis of Bandpass Continuous-Time ΣΔ Ms for Different Feedback DAC Shapes

in ISCAS IEEE International Symposium on Circuits and Systems, pages 3997-4000, 2010.

Delaram Haghighitalab, Michel Vasilevski and Hassan Aboushady

LNA Automatic Synthesis and Characterization for Accurate RF System-Level Simulation

in MWSCAS Midwest Symposium on Circuits and Systems, Seattle, Etats-Unis, 2010.

Minh Huu Nguyen, Bruno Robisson, Michel Agoyan and Nathalie Drach

Low-cost fault tolerance on the ALU in simple pipelined processors

in DDECS IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Vienne, Autriche, 2010.

Ahmed Ashry and Hassan Aboushady

Main Defects of LC-Based ΣΔ Modulators

in IEEE International Midwest Symposium on Circuits and Systems (MWSCAS'10), pages 897-900, 2010.

Ahmed Ashry and Hassan Aboushady

Modeling Jitter in Continuous-Time ΣΔ Modulators

in IEEE International Behavioral Modeling and Simulation Conference (BMAS'10), pages 55-58, 2010.

Souheib Baarir, Cécile Braunstein, Emmanuelle Encrenaz, Jean-Michel Ilié, Tun Li, Isabelle Mounier, Denis Poitrenaud and Sana Younes

Quantifying Robustness by Symbolic Model checking

in 1st Hardware Verification Workshop (CAV workshop), pages 1-12, 2010.

Jad Ayoub, Bertrand Granado, Yasser Mhanna and Olivier Romain

SVM based colon polyps classifier in a wireless active stereo endoscope

in Engineering in Medicine and Biology Society (EMBC), 2010 Annual International Conference of the IEEE, pages 5585-5588, 2010.

Jean-Michel Akré, Jérôme Juillard, Dimitri Galayko and Éric Colinet

Synchronized State in Networks of Digital Phase-Locked Loops

in IEEE International Conference on NEWCAS, Montréal, Canada, 2010.

Antoine Lévêque, François Pêcheux, Marie-Minerve Louërat, Hassan Aboushady and Michel Vasilevski

SystemC AMS models for low-power heterogeneous designs : Application to a WSN for the detection of seismic perturbations

in Workshop on Ultra-Low Power Sensor Networks (WUPS), Hannover, 2010.

W. Gaber, Mootaz Allam, Hassan Aboushady, Marie-Minerve Louërat and E. Eid

Systematic Design of Continuous-Time Sigma-Delta Modulators with VCO-Based Quantizers

in IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France, pages 29-32, 2010.

Amr Habib, François Pêcheux and Marie-Minerve Louërat

Systemc-ams modeling of a pcr-ce lab-on-chip for multithreaded dna analysis

in 22nd Intl Conference on Microelectronics (ICM), Cairo, 2010.

Abraham Suissa, Olivier Romain, Julien Denoulet, Khalil Hachicha and Patrick Garda

Temperature and Supply Voltage Aware Power Modeling of Analog Functions at System Level

in DTIS: IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Hammamet, Tunisia, pages 1-6, 2010.

Maher Kayal, Ramy Iskander and Rafael Castro-Lopez

Tutorial Session: Future Trends in Analog EDA

in NEWCAS IEEE International Conference on NEWCAS, Montréal, Québec, Canada, 2010.

Nicolas Beilleau, Hassan Aboushady, Franck Montaudon and Andreia Cathelin

A 1.3V 26mW 3.2GS/s Undersampled LC Bandpass Sigma-Delta ADC for a SDR ISM-band Receiver in 130nm CMOS

in RFIC IEEE Radio Frequency Integrated Circuits Symposium, Boston, MA, USA, pages 383-386, 2009.

Daniela Genius, Alix Munier-Kordon and Khouloud Zine el Abidine

A Buffer Space Optimal Solution for Re-establishing the Packet Order in a MPSoC Network Processor

in Euro-Par European Conference on Parallel computing, Delft, Pays-Bas, pages 216-227, 2009.

Alain Greiner, Etienne Faure, Nicolas Pouillon and Daniela Genius

A Generic Hardware / Software Communication Middleware for Streaming Applications on Shared Memory Multi Processor Systems-on-Chip

in FDL Forum on Specification & Design Languages, Nice, France, 2009.

Umer Farooq, Husain Parvez, Zied Marrakchi and Habib Mehrez

A New Tree-based coarse-grained FPGA Architecture

in IEEE International Conference on PhD. Research in MicroElectronics, PRIME'09, Cork, Ireland, pages 48-51, 2009.

D. Belfort, Nicolas Beilleau, Hassan Aboushady, Marie-Minerve Louërat and Sebastian Y. C. Catunda

A Q-enhanced LC bandpass filter using CAIRO+

in IEEE International Conference on Electronic Circuits and Systems, (ICECS), Tunisia, pages 860-863, 2009.

Mohamed Benazouz, Olivier Marchetti, Alix Munier-Kordon and P. Urard

A polynomial algorithm for the computation of buffer capacities with throughput constraint for embedded system design.

in CIE IEEE International Conference on Computers & Industrial Engineering, Troyes, FRANCE, pages 690-695, 2009.

Husain Parvez, Zied Marrakchi and Habib Mehrez

ASIF: Application Specific Inflexible FPGA

in ICFPT International Conference on Field-Programmable Technology, Sydney, Australia, pages 112-119, 2009.

Michel Vasilevski, Hassan Aboushady and Marie-Minerve Louërat

Automatic Model Refinement of GmC Integrators for High-Level Simulation of Continuous-Time Sigma-Delta Modulators

in IEEE International Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan, pages 2769-2772, 2009.

Mehdi Terosiet, Dimitri Galayko and Sylvain Feruglio

Bruit dans les oscillateurs contrôlés, application à un réseau de PLLs couplée

in Colloque du GDR SOC-SIP, 2009.

Julien Le Kernec, Philippe Dreuiller, Gérard Bobillot, Julien Denoulet, Olivier Romain and Patrick Garda

Case study analysis of linear Chirp and Multitones (OFDM) radar signals through simulations and measurement with HYCAM-Research test bench

in International Conference on Radar, RADAR 2009, Bordeaux, France, 2009.

Zied Marrakchi, Umer Farooq, Hayder Mrabet and Habib Mehrez

Comparison of Tree-Based and Mesh-Based Coarse-Grained FPGA Architectures

in ICM International Conference on Microelectronics, Marrakech, Morocco, 2009.

Souheib Baarir, Cécile Braunstein, Ranaud Clavel, Emmanuelle Encrenaz, Jean-Michel Ilié, Régis Leveugle, Isabelle Mounier, Laurence Pierre and Denis Poitrenaud

Complementary Formal Approaches for Dependability Analysis

IEEE Computer Society, 2009.

Haluk Ozaktas and Karine Heydemann

Compression de code pour processeurs haute-performance

in SympA Symposium en Architecture de Machines, Toulouse, France, 2009.

Anthony Kolar, Olivier Romain and Bertrand Granado

Cyclope:  Une  méthode  de  discrimination  spectrale  innovante  dans  le  cadre  d’un  capteur  de  vision  3D  intégré  temps  réel  sans  fils

in 22ème  Colloque  GRETSI, Dijon, France, 2009.

Ramy Iskander, Marie-Minerve Louërat and Andreas Kaiser

Design and Analysis of Analog Firm IPs using Hierarchical Sizing and Biasing Methodology

in ESSDERC European Solid-State Device Research Conference, Athens, Greece, 2009.

Minh Huu Nguyen, Bruno Robisson and Nathalie Drach

Evaluation of the Time Redundant Fault Tolerance on the ALU for Simple Pipelined Processors

in ACISC Annual Austin Conference on Integrated Systems & Circuits, Austin, Texas, USA, 2009.

Ramy Iskander, Marie-Minerve Louërat and Andreas Kaiser

Hierarchical Sizing and Biasing of Analog Firm Intellectual Properties

in Design Automation and Test in Europe Conference University Booth at DATE, Desden, Germany, 2009.

Haluk Ozaktas, Karine Heydemann, Christine Rochange and Cassé Hugues

Impact of Code Compression on Estimated Worst-Case Execution Times

in RTNS International Conference on Real-Time and Network Systems, Paris, France, 2009.

Emna Amouri, Hayder Mrabet, Zied Marrakchi and Habib Mehrez

Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing

in ReConFig International Conference on Reconfigurable Computing and FPGAs 2009, Cancun, Mexico, 2009.

André Suelflow, Görschwin Fey, Cécile Braunstein, Ulrich Kuehne and Rolf Drechsler

Increasing the Accuracy of SAT-Based Debugging

in DATE Design Automation and Test in Europe Conference, Nice, France, pages 1326-1331, 2009.

Joël Porquet, Christian Schwarz and Alain Greiner

Multi-compartment: A new architecture for secure co-hosting on SoC

in SoC International Symposium on System-on-Chip, Tampere, Finland, pages 124-127, 2009.

Assia Djabelkhir, Nathalie Drach, Karine Heydemann and Frédéric Arzel

Parallélisation supervisée pour les multicoeurs embarqués

in SympA Symposium en Architecture de Machines, Toulouse, France, 2009.

Emna Amouri, Hayder Mrabet, Zied Marrakchi and Habib Mehrez

Placement and Routing Techniques to Improve Delay Balance of WDDL Netlist in MFPGA

in ICECS IEEE International Conference on Electronics, Circuits, and Systems 2009, Hammamet, Tunisie, 2009.

Farakh Javid, Ramy Iskander and Marie-Minerve Louërat

Simulation-Based Hierarchical Sizing and Biasing of Analog Firm IPs

in IEEE International Behavioral Modeling and Simulation Conference (BMAS), San Jose, California, United States, pages 43-48, 2009.

Andrii Dudka, Dimitri Galayko and Philippe Basset

Smart Adaptive Power Management in Electrostatic Harvester of Vibration Energy

in PowerMEMS Workshop on Micro and Nanotechnology for Power Generation and Energy Conversion Applications 2009, district of Columbia, USA, pages 257-260, 2009.

Farakh Javid, Hassan Aboushady, Nicolas Beilleau and D. Morche

The Design of RF Bandpass Sigma-Delta Modulators with Bulk Acoustic Wave Resonators

in ISCAS IEEE International Symposium on Circuits and Systems, Taipei, Taiwan, 2009.

Andrii Dudka, Dimitri Galayko and Philippe Basset

VHDL-AMS modeling of adaptive electrostatic harvester of vibration energy with dual-output DC-DC converter

in BMAS IEEE International Behavioral Modeling and Simulation Conference, San Jose, CA, USA, pages 13-18, 2009.

Oussama Gamoudi, Nathalie Drach and Karine Heydemann

Vers une méthode adaptative de préchargement de données

in SympA Symposium en Architecture de Machines, Toulouse, France, 2009.

Husain Parvez, Zied Marrakchi, Umer Farooq and Habib Mehrez

A New Coarse-grained FPGA Architecture Exploration Environment

in ICFPT International Conference on Field-Programmable Technology, Taipei, Taiwan, pages 285-288, 2008.

Patricia Renault and Pirouz Bazargan Sabet

A Novel Method to Determine the RC Interconnect Circuit Outputs

in DCIS International Conference on Design of Circuits and Integrated Systems, Grenoble, France, 2008.

Olivier Certner, Zheng Li, Pierre Palatin, Olivier Temam, Frédéric Arzel and Nathalie Drach

A Practical Approach for Reconciling High and Predictable Performance in Non-Regular Parallel Programs

in MULTIPROG International Workshop on Programmability Issues for Multi-Core Computers, Göteberg, Sweden, 2008.

Olivier Certner, Pierre Palatin, Zheng Li, Olivier Temam, Frédéric Arzel and Nathalie Drach

A Practical Approach for Reconciling High and Predictable Performance in Non-Regular Parallel Programs

in DATE Design Automation and Test in Europe Conference, Munich, Germany, pages 740-745, 2008.

Zhen Zhang, Alain Greiner and Sami Taktak

A Reconfigurable Routing Algorithm for a Fault-Tolerant 2D-Mesh Network-on-Chip

in DAC ACM/EDAC/IEEE Design Automation Conference, Anaheim, California, USA, pages 441-446, 2008.

Jad Ayoub, Olivier Romain, Bertrand Granado and Yasser Mhanna

Accuracy amélioration of an integrated real‐time 3D image sensor

in Conference on Design & Architectures for Signal and Image Processing, DASIP, Brussels, Belgium, 2008.

Étienne André, Thomas Chatain, Emmanuelle Encrenaz and Laurent Fribourg

An Inverse Method for Parametric Timed Automata

in Electr. Notes Theor. Comput. Sci, 223, pages 29-46, 2008.

Sophie Belloeil, Roselyne Chotin-Avot and Habib Mehrez

Arithmetic Data path Optimization using Borrow-Save Representation

in ISVLSI IEEE Computer Society Annual Symposium on Emerging VLSI, Montpellier, FRANCE, pages 4-9, 2008.

Sophie Belloeil, Roselyne Chotin-Avot, Habib Mehrez and Alix Munier-Kordon

Automatic Allocation of Redundant Operators in Arithmetic Data path Optimization

in DASIP IEEE International Conference on Design and Architectures for Signal and Image Processing, Bruxelles, Belgique, pages 176-183, 2008.

Hayder Mrabet, Husain Parvez, Zied Marrakchi and Habib Mehrez

Automatic Layout Generator of Domain Specific FPGA:

in ICM International Conference on Microelectronics, Sharjah, UAE, 2008.

Ayyaz Mahmood Paracha, Philippe Basset, Dimitri Galayko, Frédéric Marty, Andrii Dudka and Tarik Bourouina

Characterization of a DC/DC converter using an in-plane bulk-silicon capacitive transducer for vibration-to-electricity power conversion

in PowerMEMS Workshop on Micro and Nanotechnology for Power Generation and Energy Conversion Applications, Sendai, Japon, pages 297-300, 2008.

Daniela Genius, Nicolas Pouillon and Alain Greiner

Design Space Explorer : Un Outil de Co-Conception pour Plate-formes Multi-processeurs sur Puce

in CNFM Coordination Nationale pour la Formation en Micro-nanoélectronique, St Malo, France, pages 33-38, 2008.

Zied Marrakchi, Hayder Mrabet, Emna Amouri and Habib Mehrez

Efficient Tree Topology for FPGA Interconnect Network

in GLSVLSI ACM Great Lakes Symposium on VLSI, Orlando, Florida, USA, pages 321-326, 2008.

Michel Vasilevski, Nicolas Beilleau, Hassan Aboushady and François Pêcheux

Efficient and Refined Modeling of Wireless Sensor Network Nodes Using SystemC-AMS

in PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, Istanbul, Turkey, 2008.

Husain Parvez, Zied Marrakchi and Habib Mehrez

Enhanced Methodology and Tools for Exploring Domain-Specific Coarse-grained FPGAs

in ReConFig International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, 2008.

Husain Parvez, Hayder Mrabet and Habib Mehrez

Generic Techniques and CAD tools for automated generation of FPGA Layout

in PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, Istanbul, Turkey, pages 141-144, 2008.

Sylvain Feruglio, François Andrieu, Faynot Olivier and Gérard Ghibaudo

Low-Temperature Electrical Characterization of eXtra-strained FD-SOI n-MOSFETs with TiN/HfO2 Gate Stack for the 32 nm Technology Node

in The 8th International Workshop On Low Temperature Electronics (WOLTE'08), Ilmenau, Germany, 2008.

Dimitri Galayko and Philippe Basset

Mechanical/electrical power-aware impedance matching for design of capacitive vibration energy harvesters

in PowerMEMS Workshop on Micro and Nanotechnology for Power Generation and Energy Conversion Applications, Sendai, Japon, pages 293-296, 2008.

Michel Vasilevski, François Pêcheux, Nicolas Beilleau, Hassan Aboushady and Karsten Einwich

Modeling and Refining Heterogeneous Systems With SystemC-AMS: Application to WSN

in DATE Design Automation and Test in Europe Conference, Munich, Germany, 2008.

Dimitri Galayko, Ken Caluwaerts and Philippe Basset

Modelling techniques for capacitive harvesters of vibration energy

in PowerMEMS Workshop on Micro and Nanotechnology for Power Generation and Energy Conversion Applications, Sendai, Japon, pages 445-448, 2008.

Dimitri Galayko, Philippe Basset and Ayyaz Mahmood Paracha

Optimization and AMS Modeling for design of an electrostatic vibration energy harvester's conditioning circuit with an auto-adaptive process for external vibration changes

in DTIP' Symposium on Design, Test, Integration & Packaging of MEMS/MOEMS, Nice, France, 2008.

Ivan Miro Panades, Fabien Clermidy, Pascal Vivet and Alain Greiner

Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture

in NoC ACM/IEEE International Symposium on Networks-on-Chip, Newcastle, Royaume Unis, pages 139-148, 2008.

Ken Caluwaerts, Dimitri Galayko and Philippe Basset

SystemC-AMS Heterogeneous Modeling of a Capacitive Harvester of Vibration Energy

in BMAS IEEE International Behavioral Modeling and Simulation Conference, San José, CA, USA, 2008.

Ken Caluwaerts, Dimitri Galayko, Philippe Basset and Ayyaz Mahmood Paracha

SystemC-AMS modeling of an electromechanical harvester of vibration energy

in FDL Forum on Specification & Design Languages, Stuttgart, Allemagne, 2008.

Etienne Faure and Daniela Genius

Telecommunication Application Modelling with Multi Writer Multi Reader Channels: a Case Study

in FDL Forum on Specification & Design Languages, Stuttgart, Allemagne, 2008.

Umer Farooq, Zied Marrakchi, Hayder Mrabet and Habib Mehrez

The Effect of LUT and Cluster Size on a Tree based FPGA Architecture

in ReConFig International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexique, 2008.

Thomas Finateu, Ivan Miro Panades, Fabrice Boissières, Jean-Baptiste Bègueret, Yann Deval, Didier Belot and Franck Badets

A 500-Mhz Sigma-Delta Phase Interpolation Direct Digital Synthesizer

in A-SSCC IEEE Asian Solid-State Circuits Conference, Jeju, Corée, pages 452-455, 2007.

Ludovic Noury, Habib Mehrez, François Durbin and André Tissot

A Cascadable ASIC Prototype for Real Time Time-Frequency Analysis

in MWSCAS Midwest Symposium on Circuits and Systems, Montreal, Canada, 2007.

Will R. M. Almeida, Georgina M. Freitas, Lígia S. Palma, Sebastian Y. C. Catunda, Raimundo C. S. Freire, Hassan Aboushady, Francisco F. Santos and Amauri Oliveira

A Constant Temperature Thermoresistive Sigma-Delta Anemometer

in IMTC IEEE Instrumentation and Measurement Technology Conference, Warsaw, Poland, 2007.

Richard Buchmann and Alain Greiner

A Fully Static Scheduling Approach for Fast Cycle Accurate SystemC Simulation of MPSoCs

in ICM International Conference on Microelectronics, Cairo, Egypt, pages 105-108, 2007.

Ludovic Noury, François Durbin, Habib Mehrez and André Tissot

A Generic ASIC Architecture for Real Time Time-Frequency Analysis of Non-stationary Large Bandwidth Signals

in IMTC IEEE Instrumentation and Measurement Technology Conference, Warsaw, Poland, 2007.

Zied Marrakchi, Hayder Mrabet, Grégory Souffleteau, Christian Masson and Habib Mehrez

A Routability Driven Partitioning and Detailed Placement Approach for Multilevel Hierarchical FPGA

in FPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, Californie, USA, pages 225-225, 2007.

Anthony Kolar, Tarik Graba, Andrea Pinna, Olivier Romain, Bertrand Granado and Thomas Ea

A digital processing architecture for 3D reconstruction

in IEEE International Conf. on Application-Specific Systems, Architectures and Processors (ASAP), Montreal, Canada, 2007.

Anthony Kolar, Bertrand Granado, Olivier Romain, Tarik Graba and Andrea Pinna

A  multishutter  time  sensor  for  multispectral  imaging  in  a  3D  Reconstruction  embedded  sensor

in IEEE DCIS, XXII Conference on Design of  Circuits and Integrated Systems, Sevilla, Spain, 2007.

Dimitri Galayko, Rodrigo Pizarro, Philippe Basset, Ayyaz Mahmood Paracha and Gilles Amendola

AMS modeling of controlled switch for design optimization of capacitive vibration energy harvester

in BMAS IEEE International Behavioral Modeling and Simulation Conference, San Jose, CA, USA, pages 115-120, 2007.

Alix Munier-Kordon and D. Rebaine

An approximation algorithm for the UET two-machine open shop problem with time delays

in MISTA Multidisciplinary International Scheduling Conference: Theory and Applications, Paris, France, 2007.

Matthieu Tuna, Mounir Benabdenbi and Alain Greiner

At-Speed Testing of Core-Based System-On-Chip Using an Embedded Micro-Tester

in VTS IEEE VLSI Test Symposium, Berkeley, California, USA, 2007.

Emmanuelle Encrenaz and Alain Finkel

Automatic Verification of Counter Systems with Ranking Functions

in INFINITY International Symposium on Infinite-Space Systems, Porto, Portugal, 2007.

Ivan Miro Panades and Alain Greiner

Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-chip in GALS Architecture

in NoC ACM/IEEE International Symposium on Networks-on-Chip, Princeton, New Jersey, USA, pages 83-92, 2007.

Sylvain Feruglio, François Andrieu, Faynot Olivier and Gérard Ghibaudo

Characterization of sub 45nm strained FD-SOI c-MOSFETs with TiN/HfO2 gate stack

in The 8th International Conference on Ultimate Integration on Silicon (ULIS’07), Leuven, Belgium, 2007.

Ramy Iskander, Marie-Minerve Louërat and Andreas Kaiser

Computing Systematic Offsets in Amplifiers Using Hierarchical Graph-Based Sizing and Biasing

in ICM International Conference on Microelectronics, Le Caire, Egypte, 2007.

Ramy Iskander, Dimitri Galayko and Marie-Minerve Louërat

Connaissance et Opimisation pour la Synthèse Analogique

in Colloque Groupement de Recherche : System-On-Chip, System-In-Package, GDR SoC SiP, Paris, France, 2007.

Sophie Belloeil, Roselyne Chotin-Avot and Habib Mehrez

Data Path Optimization using Redundant Arithmetic and Pattern Matching

in Workshop on Design and Architectures for Signal and Image Processing (DASIP'2007), Grenoble, France, 2007.

Daniela Genius, Etienne Faure and Nicolas Pouillon

Deploying a Telecommunication on Multiprocessor Systems-on-Chip

DASIP, 2007.

David Faura, Olivier Romain, Khalil Hachicha and Patrick Garda

Design  and  Implementation  of  a  Motion  Coprocesseur  for  the  Merite  Beacon

in IEEE  Workshop  International  on  Wireless  Sensor  Network,  NOTERE 2007, Marrakech,  Morocco, 2007.

Ramy Iskander, Marie-Minerve Louërat and Andreas Kaiser

Détection et évaluation des tensions de décalage d'un circuit analogique

in TAISA Colloque sur le Traitement Analogique de l'Information du Signal et ses Applications, Lyon, France, pages 13-16, 2007.

Johan Mazeyrat, Olivier Romain, Patrick Garda, Pierre-Yves Lagrée, Michel Destrade, Mourad Karouia and Pascal Leprince

ENDOCOM : Abdominal Aortic Aneurysm test bench for in vitro simulation

in Engineering in Medicine and Biology Society, 2007. EMBS 2007. 29th Annual International Conference of the IEEE, pages 2323-2326, 2007.

Zied Marrakchi, Hayder Mrabet, Christian Masson and Habib Mehrez

Efficient Mesh of Tree Interconnect for FPGA Architecture

in ICFPT International Conference on Field-Programmable Technology, Kitakyushu, JAPAN, pages 269-272, 2007.

Johan Mazeyrat, Olivier Romain, Patrick Garda, Mourad Karouia, Pascal Leprince, Pierre-Yves Lagrée and Michel Destrade

Endocom:  conception  d'un  banc  in  vitro  de  simulation  des  anévrismes  de  l'aorte  abdominal

in C2I, Colloque  Interdisciplinaire  en  Instrumentation, Nancy, France, 2007.

Abbas Sheibanyrad and Alain Greiner

Hybrid-Timing FIFOs to use on Networks-on-Chip in GALS Architectures

in ESA International Conference on Embedded Systems and Applications, Las Vegas, Nevada, USA, 2007.

François Andrieu, Faynot Olivier, Florent Rochette, Jean-Charles Barbé, Christel Buj, Yann Bogumilowicz, Fabienne Allain, Vincent Delaye, Dominique Lafond, François Aussenac, Sylvain Feruglio, Joël Eymery, Takeshi Akatsu, Patrick Maury, Laurent Brévard, Lucie Tosti, H. Dansas, Eric Rouchouze, Jean-Michel Hartmann and Laurent Vandroux

Impact of Mobility Boosters (XsSOI, CESL, TiN gate) on the Performance of 100 or 110 oriented FDSOI cMOSFETs for the 32nm Node

in The 2007 Symposium on VLSI, Kyoto, Japan, 2007.

Ramy Iskander, Dimitri Galayko, Marie-Minerve Louërat and Andreas Kaiser

Knowledge-Aware Synthesis Using Hierarchical Graph-Based Sizing and Biasing

in 50th Midwest Symposium on Circuits and Systems (MWSCAS), Montréal, Québec, Canada, pages 984-987, 2007.

Zied Marrakchi, Hayder Mrabet, Christian Masson and Habib Mehrez

Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances

in NoC ACM/IEEE International Symposium on Networks-on-Chip, Princeton, Etats Unis, pages 243-252, 2007.

Mohammad Alassir, Julien Denoulet, Olivier Romain and Patrick Garda

Modeling I2C Communication Between SoCs with SystemC-AMS

in Industrial Electronics, 2007. ISIE 2007. IEEE International Symposium on, Vigo, Spain, pages 1412-1417, 2007.

Michel Vasilevski, Hassan Aboushady, François Pêcheux and Laurent de Lamarre

Modeling Wireless Sensor Network Nodes Using SystemC-AMS

in ICM International Conference on Microelectronics, Cairo, Egypt, 2007.

Michel Vasilevski, François Pêcheux, Hassan Aboushady and Laurent de Lamarre

Modeling and Refining Heterogeneous Systems With SystemC-AMS: Application to WSN

in BMAS IEEE International Behavioral Modeling and Simulation Conference, San Jose, CA, USA, 2007.

Mohammad Alassir, Julien Denoulet, Olivier Romain, Gabriel Vasilescu, Romain Arnaud and Patrick Garda

Modeling field bus communications for automotive applications

in Forum on specification and Design Languages (FDL '07), Barcelona, Spain, pages 56-61, 2007.

Dimitri Galayko, Rodrigo Pizarro, Philippe Basset, Ayyaz Mahmood Paracha and Gilles Amendola

Optimization and AMS modeling of capacitive vibration harvester

in PowerMEMS Workshop on Micro and Nanotechnology for Power Generation and Energy Conversion Applications, Freiburg, Allemagne, pages 109-112, 2007.

Olivier Romain and Bruce Denby

Prototype  of  a  Software  Defined  Broadcast  Media  Indexing  Engine

IEEE, 2007.

Tarik Graba, David Faura, Sylvain Viateur, Olivier Romain, Bertrand Granado and Patrick Garda

Seuillage  Dynamique  temps  réel  dans  un  système  embarqué

in Colloque  GRETSI:  Traitement  du  signal  et  des  images,  2007, Troyes, France, 2007.

Kolin Paul and Joël Porquet

Silicon Compaction/Defragmentation for Partial Runtime Reconfiguration

in DSD EUROMICRO Conference on Digital System Design, Lübeck, Allemagne, 2007.

Anthony Kolar, Tarik Graba, Andrea Pinna, Olivier Romain, Bertrand Granado and Eric Belhaire

Smart Bi-Spectral Image Sensor for 3D Vision

IEEE, 2007.

Matthieu Tuna, Olivier Garcia and Mounir Benabdenbi

Software-Based Self-Test Strategies for Memory Caches of RISC Processor Cores

in LATW IEEE Latin-American Test Workshop, Cuzco, Peru, pages 124-130, 2007.

Sophie Belloeil, Damien Dupuis, Christian Masson, Jean-Paul Chaput and Habib Mehrez

Stratus: A procedural circuit description language based upon Python

in ICM International Conference on Microelectronics, Cairo, Egypte, pages 275-278, 2007.

Abbas Sheibanyrad, Ivan Miro Panades and Alain Greiner

Systematic Comparison between the Asynchronous and the Multi-Synchronous Implementations of a Network on Chip Architecture

in DATE Design Automation and Test in Europe Conference 2007, Nice, France, pages 1090-1095, 2007.

Ramy Iskander, Andreas Kaiser and Marie-Minerve Louërat

Systematic Offset Detection and Evaluation Using Hierarchical Graph-Based Sizing and Biasing

in 14th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Marrackech, Morocco, pages 170-173, 2007.

Will R. M. Almeida, Georgina M. Freitas, Lígia S. Palma, Sebastian Y. C. Catunda, Raimundo C. S. Freire, Francisco F. Santos, Amauri Oliveira and Hassan Aboushady

Thermal Sigma-Delta Modulator: Anemometer Performance Analysis

in IMTC IEEE Instrumentation and Measurement Technology Conference, Warsaw, Poland, 2007.

Farouk Vallette, Gabriel Vasilescu, Sylvain Feruglio and Patrick Garda

Tolerance Analysis in MOSFET Analog Integrated Circuits

in WSEAS the 7th International Conference on Systems Theory and Scientific Computation (ISTASC'07), 2007.

Cécile Braunstein and Emmanuelle Encrenaz

Using CTL formulae as component abstraction in a design and verification flow

in ACSD IEEE International Conference on Application of Concurrency to System Design, Bratislava, Slovak Republic, pages 80-89, 2007.

Anthony Kolar, Tarik Graba, Andrea Pinna, Olivier Romain, Bertrand Granado and Thomas Ea

A Digital Processing Architecture For 3D Reconstruction

IEEE, 2006.

Cécile Braunstein and Emmanuelle Encrenaz

A Further Step in the Incremental Design Process: Incorporation of an Increment Specification

in LPAR IEEE International Conference on Logic for Programming Artificial Intelligence and Reasoning, Phnom Penh, Cambodge, 2006.

Ivan Miro Panades, Alain Greiner and Abbas Sheibanyrad

A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach

in NanoNet International Conference on Nano-Networks, Lausanne, Switzerland, pages 1-5, 2006.

Mohammad Alassir, Julien Denoulet, Olivier Romain and Patrick Garda

A SystemC AMS model of an 12C bus controller

IEEE, 2006.

Sami Taktak, Emmanuelle Encrenaz and Jean-Lou Desbarbieux

A Tool for Automatic Detection of Deadlock in Wormhole Networks on Chip

in HLDVT IEEE International High Level Design Validation and Test Workshop, Monterey, California, USA, pages 203-210, 2006.

Etienne Faure, Alain Greiner and Daniela Genius

A generic hardware/software communication mechanism for Multi-Processor System on Chip, Targeting Telecommunication Applications

in ReCoSoC Reconfigurable Communication-centric SoCs, Montpellier, France, pages 237-242, 2006.

Hayder Mrabet, Zied Marrakchi, Pierre Souillot and Habib Mehrez

A multilevel hierarchical interconnection structure for FPGA

in FPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, California, USA, 2006.

Zied Marrakchi, Hayder Mrabet and Habib Mehrez

A new Multilevel Hierarchical MFPGA and its suitable configuration tools

in ISVLSI IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, Karlsruhe, Germany, pages 263-268, 2006.

Olivier Marchetti and Alix Munier-Kordon

A polynomial algorithm for a bi-criteria cyclic scheduling problem.

in PlanSIG UK PLANNING AND SCHEDULING Special Interest Group, Nottingham, UK, pages 88-96, 2006.

Emmanuel Viaud and François Pêcheux

An Efficient TLM/T Modeling and Simulation Environment Based on Conservative Parallel Discrete Event Principles

in PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, Otranto, Italy, pages 217-220, 2006.

Emmanuel Viaud, François Pêcheux and Alain Greiner

An Efficient TLM/T Modeling and Simulation Environment Based on Conservative Parallel Discrete Event Principles

in DATE Design Automation and Test in Europe Conference, München, Germany, pages 94-99, 2006.

Mohammad Alassir, Julien Denoulet, Olivier Romain and Patrick Garda

An I2C Bus Controller Model and Simulation in SystemC-AMS

in Design of Circuits and Integrated Systems, International Conference (DCIS 06), Barcelona, Spain, 2006.

Ramy Iskander, Pierre Nguyen-Tuong, Laurent de Lamarre, Vincent Bourguet, Marie-Minerve Louërat and Alain Greiner

Automated Hierarchical Knowledge-Based Synthesis for Analog Cells using CAIRO+

in DATE Design Automation and Test in Europe Conference, Munich, Allemagne, 2006.

Richard Buchmann and Alain Greiner

Automatic Translation of SystemC Simulation Model From VHDL RTL Model : a Semantic Approach

in DATE Design Automation and Test in Europe Conference, München, Germany, 2006.

Olivier Marchetti and Alix Munier-Kordon

Complexity results for bi-criteria cyclic scheduling problems

in RenPar Rencontres Francophones du Parallélisme, Perpignan, France, pages 17-24, 2006.

Zied Marrakchi, Hayder Mrabet and Habib Mehrez

Configuration tools for a new multilevel hierarchical FPGA

in FPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, California, USA, 2006.

Ramy Iskander, Marie-Minerve Louërat and Andreas Kaiser

Dimensionnement automatique d'un circuit analogique à l'aide des transistors de référence

in TAISA Colloque sur le Traitement Analogique de l'Information du Signal et ses Applications, Strasbourg, France, pages 89-92, 2006.

Mathieu Carrier and Alain Greiner

Détection d'obstacles en contexte routier par stéréo vision sur un système intégré sur puce

in JNRDM Journées Nationales du Réseau Doctoral en Microélectronique, Rennes, France, pages 243-245, 2006.

Zied Marrakchi, Hayder Mrabet and Habib Mehrez

Evaluation of Hierarchical FPGA partitioning methodologies based on architecture Rent Parameter

in PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, Otranto, Italy, pages 85-88, 2006.

Cécile Braunstein and Emmanuelle Encrenaz

Formalizing the incremental design and verification process of a pipelined protocol converter

in RSP International Workshop on Rapid System Prototyping, Chania, Crete, Greece, pages 103-109, 2006.

Ramy Iskander, Marie-Minerve Rosset-Louërat and Andreas Kaiser

Hierarchical Graph-Based Sizing for Analog Cells Through Reference Transistors

in PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics Winner of the Bronze Leaf Certificate, Otranto, Italy, pages 321-324, 2006.

Hayder Mrabet, Zied Marrakchi, Habib Mehrez and André Tissot

Implementation of Scalable Embedded FPGA for SOC

in DTIS IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Tunis, Tunisia, pages 74-77, 2006.

Maxime Palus and François Anceau

JMQ, un processeur Java de hautes performances

in SympA Symposium en Architecture de Machines, Perpignan, France, pages 154-165, 2006.

José Bonan, Christoph Hagleitner and Hassan Aboushady

Low-Power Cell-Level ADC for a MEMS-Based Parallel Scanning-Probe Storage Device

in ESSCIRC European Solid-State Circuits Conference, Montreux, Switzerland, pages 239-242, 2006.

Alain Greiner, Frédéric Pétrot, Mathieu Carrier, Mounir Benabdenbi, Roselyne Chotin-Avot and Raphaël Labayrade

Mapping an obstacles detection, stereo vision-based, software application on a multi-processor system-on-chip

in IV IEEE Intelligent Vehicles Symposium, Tokyo, Japan, pages 370-376, 2006.

Ivan Miro Panades, Alain Greiner and Abbas Sheibanyrad

Micro-réseau sur puce compatible avec l'approche GALS

in JNRDM Journées Nationales du Réseau Doctoral en Microélectronique, Rennes, France, 2006.

Nizar Abdallah and Pirouz Bazargan Sabet

Modeling the Effects of Input Slew Rate and Temporal Proximity of Input Transitions in Event-Driven Simulation

in SSST IEEE Southeastern Symposium on System Theory, Cookeville, Tenessess, USA, pages 185-189, 2006.

Mohammad Alassir, Julien Denoulet, Olivier Romain and Patrick Garda

Modelling and Simulation of an I2C Bus Controller in SystemC-AM

in Forum on specification and Design Languages, FDL 2006, Darmstadt, Germany, pages 121-128, 2006.

Frédéric Pétrot, Alain Greiner and Pascal Gomez

On cache coherency and memory consistency issues in NoC based shared memory multiprocessor SoC architectures

in DSD EUROMICRO Conference on Digital System Design, Dubrovnik, Croatia, pages 53-60, 2006.

Laurent de Lamarre, Marie-Minerve Louërat and Andreas Kaiser

Optimisation des éléments passifs d'un convertisseur sigma-delta temps continu

in TAISA Colloque sur le Traitement Analogique de l'Information du Signal et ses Applications, Strasbourg, France, pages 101-104, 2006.

Laurent de Lamarre, Marie-Minerve Louërat and Andreas Kaiser

Optimizing Resistances and Capacitances of a Continuous-Time Sigma-Delta Modulator

in ICECS IEEE International Conference on Electronics Circuits and Systems, Nice, France, pages 419-422, 2006.

Hayder Mrabet, Zied Marrakchi, Pierre Souillot and Habib Mehrez

Performances Improvement of FPGA using Novel Multilevel Hierarchical Interconnection Structure

in ICCAD IEEE/ACM International Conference on Computer-Aided Design, San Jose, California, USA, pages 675-679, 2006.

Hayder Mrabet, Zied Marrakchi, Pierre Souillot and Habib Mehrez

Performances Improvement of FPGA using Novel Multilevel Hierarchical Interconnection Structure II

in ReCoSoC Reconfigurable Communication-centric SoCs, Montpellier, France, pages 117-123, 2006.

Zied Marrakchi, Hayder Mrabet and Habib Mehrez

Performances comparison between Multilevel hierarchical and Mesh FPGA

in DTIS IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Tunis, Tunisia, pages 166-171, 2006.

Dimitri Galayko, Ramy Iskander, Marie-Minerve Louërat and Alain Greiner

Réutilisation et migration d'amplificateurs avec CAIRO+

in JP CNFM Journées pédagogiques du CNFM, Saint Malo, France, pages 35-39, 2006.

Matthieu Tuna, Mounir Benabdenbi and Alain Greiner

STESOC: A Software-Based Test-Access-Mechanism Controller

in ETS IEEE European Test Symposium, Southampton, England, pages 91-96, 2006.

Alexandre Coveliers, Karine Heydemann and Nathalie Drach

Sensibilité aux jeux de données de la compilation itérative

in SympA Symposium en Architecture de Machines, Perpignan, France, pages 35-46, 2006.

Matthieu Tuna and Mounir Benabdenbi

Software-Based Self-Test of Register Files in RISC Processor Cores using March Algorithms

in LATW IEEE Latin-American Test Workshop digest of papers, Buenos Aires, Argentina, pages 67-72, 2006.

Sophie Belloeil, Jean-Paul Chaput, Roselyne Chotin-Avot, Christian Masson and Habib Mehrez

Stratus : Un environnement de développement de circuits

in JP CNFM Journées pédagogiques du CNFM, Saint Malo, France, pages 57-61, 2006.

Nicolas Beilleau, Abla Kammoun and Hassan Aboushady

Systematic Design Method for LC Bandpass Sigma-Delta Modulators with Feedback FIRDACs

in ISCAS IEEE International Symposium on Circuits and Systems, Kos, Greece, pages 1896-1899, 2006.

Matthieu Tuna, Mounir Benabdenbi and Alain Greiner

T-Proc: An Embedded IEEE1500-Wrapped Cores Tester

in PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, Otranto, Italie, pages 493-496, 2006.

Emmanuelle Encrenaz and Laurent Fribourg

Time separation of events, an inverse method

in LIX Colloquium on emerging Trends in Concurrency Theory, Palaiseau, France, 2006.

Abbas Sheibanyrad and Alain Greiner

Two Efficient Synchronous <-> Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures

in PATMOS Power and Timing Modeling Optimization and Simulation, Montpellier, France, pages 192-202, 2006.

Abla Kammoun, Nicolas Beilleau and Hassan Aboushady

Undersampled LC bandpass Sigma-Delta modulators with Feedback FIRDACs

in ISCAS IEEE International Symposium on Circuits and Systems, Kos, Greece, pages 4427-4430, 2006.

Christophe Alexandre, Marek Sroka, Hugo Clément and Christian Masson

Zephyr: a Static Timing Analyzer integrated in a trans-hierarchical refinement design flow

in PATMOS Power and Timing Modeling Optimization and Simulation, Montpellier, France, pages 319-328, 2006.

Ana Belen Abril Garcia, Habib Mehrez, Frédéric Pétrot, Jean Gobert and Carolina Miro

A High Level SoC Energy Analysis Method with good Accuracy using Cycle Accurate Simulation

in COOLChips IEEE Symposium on Low-Power and High-Speed Chips, Yokohama, Japan, 2005.

Laurent de Lamarre, Marie-Minerve Rosset-Louërat and Andreas Kaiser

A simple 3.8mW, 300 MHz, 4-bit flash analog-to-digital converter

in Microtechnologies for the New Millennium 2005 VLSI Circuits and Systems II, Sevilla, Spain, pages 825-832, 2005.

Ana Belen Abril Garcia, Habib Mehrez, Frédéric Pétrot, Jean Gobert and Carolina Miro

Architectural Energy Estimation of Embedded Systems using Cycle Accurate Simulation

in Microtechnologies for the New Millennium 2005 VLSI Circuits and Systems II, Sevilla, Spain, 2005.

Ramy Iskander, Marie-Minerve Rosset-Louërat and Andreas Kaiser

Automatic Biasing Point Extraction and Design Plan Generation for Analog IPs

in MWSCAS Midwest Symposium on Circuits and Systems, Cincinnati, Ohio, USA, pages 901-910, 2005.

Patricia Renault and Pirouz Bazargan Sabet

Capturing RC-Interconnect Effect in Crosstalk Analysis

in MIXDES Mixed Design of Integrated Circuits and Systems, Krakow, Poland, pages 309-314, 2005.

A. Latiri, Hassan Aboushady and Nicolas Beilleau

Design of Continuous-Time Sigma-Delta Modulators with Sine-Shaped Feedback DACs

in ISCAS IEEE International Symposium on Circuits and Systems, Kobe, Japan, pages 3672-3675, 2005.

Ana Belen Abril Garcia, Habib Mehrez, Frédéric Pétrot, Jean Gobert and Carolina Miro

Energy Estimation and Optimisation of Embedded Systems using Cycle Accurate Simulation

in FTFC Journées d'études Faible Tension Faible Consommation, Paris, France, pages 29-32, 2005.

Damien Dupuis

Etude comparative de deux algorithmes de placement de systèmes intégrés sur puce

in JNRDM Journées Nationales du Réseau Doctoral en Microélectronique, Paris, France, pages 55-57, 2005.

Diaaeldin Khalil, Mohamed Dessouky, Vincent Bourguet, Marie-Minerve Rosset-Louërat, Andreia Cathelin and Hani Ragai

Evaluation of Capacitor Ratios in Automated Accurate Common-Centroid Capacitor Arrays

in ISQED International Symposium on Quality Electronic Design, San Jose, California, USA, pages 143-147, 2005.

Richard Buchmann and Alain Greiner

Fast Functional SystemC Simulator using Static Scheduling

in DATE Design Automation and Test in Europe Conference, München, Germany, 2005.

Zied Marrakchi, Hayder Mrabet and Habib Mehrez

Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation

in ReConFig International Conference on Reconfigurable Computing and FPGAs, Puebla city, Mexico, 2005.

Zied Marrakchi, Hayder Mrabet and Habib Mehrez

Hierarchical FPGA clustering to improve routability

in PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, Lausanne, Switzerland, pages 139-142, 2005.

Hayder Mrabet, Zied Marrakchi, Habib Mehrez and André Tissot

Implementation of Scalable Embedded FPGA for SOC

in ReCoSoC Reconfigurable Communication-centric SoCs, Montpellier, France, 2005.

Daniel Zaoui, Frédéric Pétrot and Raphaël Labayrade

Intégration système d'une application de détection d'obstacles par stéréovision

in SympA Symposium en Architecture de Machines, Le Croisic, France, pages 183-194, 2005.

François Pêcheux, Bruno Allard, Christophe Lallement, Alain Vachoux and Hervé Morel

Modeling and simulation of multi-discipline systems using bond graphs and VHDL-AMS

in ICBGM International Conference on Bond Graph Modeling and Simulation, New-Orleans, Louisiane, USA, pages 1-6, 2005.

Sophie Belloeil and Habib Mehrez

Optimisation de chemins de données par l'utilisation de l'arithmétique redondante

in JNRDM Journées Nationales du Réseau Doctoral en Microélectronique, Paris, France, pages 268-270, 2005.

Matthieu Tuna, Mounir Benabdenbi and Alain Greiner

STESI: Testing wrapped IP cores using a dedicated Test Processor

in I-IP IEEE International Workshop on Infrastructure IP, PalmSprings, California, USA, pages 60-66, 2005.

Matthieu Tuna, Mounir Benabdenbi and Alain Greiner

STESI: a new software-based strategy for testing socs containing wrapped IP cores

in MIXDES Mixed Design of Integrated Circuits and Systems, Krakow, Poland, pages 459-464, 2005.

Karine Heydemann, François Bodin and Henri-Pierre Charles

Software-Only Compression System for Trading-off Code Size and Performance

in SCOPES International Workshop on Software and Compilers for Embedded Systems, Dallas, Texas, USA, pages 27-36, 2005.

Ramy Iskander, Laurent de Lamarre, Pierre Nguyen-Tuong, Marie-Minerve Louërat and Andreas Kaiser

Synthèse d'un IP amplificateur analogique CMOS avec CAIRO+

in TAISA Colloque sur le Traitement Analogique de l'Information du Signal et ses Applications, Marseille, France, pages 69-72, 2005.

Christophe Alexandre, Hugo Clément, Jean-Paul Chaput, Marek Sroka, Christian Masson and Rémy Escassut

TSUNAMI: An Integrated Timing-Driven Place And Route Research Platform

in DATE Design Automation and Test in Europe Conference, München, Germany, pages 920-921, 2005.

Laurent de Lamarre, Marie-Minerve Louërat and Andreas Kaiser

Un convertisseur flash 4 bits à base de transistors MOS consommant 3,8mW à 300MHz

in TAISA Colloque sur le Traitement Analogique de l'Information du Signal et ses Applications, Marseille, France, pages 57-60, 2005.

Nicolas Beilleau, Hassan Aboushady and Marie-Minerve Rosset-Louërat

Using Finite Impulse Response Feedback DACs to design Sigma-Delta modulators based on LC filters

in MWSCAS Midwest Symposium on Circuits and Systems, Cincinnati, Ohio, USA, pages 696-699, 2005.

Marek Sroka

Zephyr : Un outil d'analyse de timing pour placement-routage timing-driven de systèmes intégrés sur puce

in JNRDM Journées Nationales du Réseau Doctoral en Microélectronique, Paris, France, 2005.

Pierre Nguyen-Tuong, Vincent Bourguet, Laurent de Lamarre, Marie-Minerve Rosset-Louërat and Alain Greiner

A Language to Design Generators of Analog Functions

in FDL Forum on Specification & Design Languages, Lille, France, pages 30-31, 2004.

Vincent Bourguet, Laurent de Lamarre and Marie-Minerve Rosset-Louërat

A Layout-Educated Analog Design Flow

in MWSCAS Midwest Symposium on Circuits and Systems, Hiroshima, Japan, pages 432-488, 2004.

Hassan Aboushady, Laurent de Lamarre, Nicolas Beilleau and Marie-Minerve Rosset-Louërat

A Mixed Equation-based and Simulation-based Design Methodology for Continuous-Time Sigma-Delta Modulators

in MWSCAS Midwest Symposium on Circuits and Systems, Hiroshima, Japon, pages 109-112, 2004.

Vincent Bourguet, Laurent de Lamarre and Marie-Minerve Rosset-Louërat

Analog IC Design with a Library of Parameterized Device Generators

in DCIS International Conference on Design of Circuits and Integrated Systems, Bordeaux, France, pages 739-744, 2004.

Marie-Martine Paget, Marie-Claire Nogier and Hélène Giroire

Autoevaluation in 8086 assembly language programming

in CALIE Computer Aided Learning In Engineering Education, University Joseph Fourier, Grenoble, France, pages 209-214, 2004.

Hayder Mrabet, Zied Marrakchi, Habib Mehrez and André Tissot

Automatic Layout of Scalable Embedded Field Programmable Gate Array

in ICEEC International Conference on Electrical Electronic and Computer Engineering, Cairo, Egypt, pages 469-472, 2004.

Hassan Aboushady, Laurent de Lamarre, Nicolas Beilleau and Marie-Minerve Rosset-Louërat

Automatic Synthesis and Simulation of Continuous-Time Sigma Delta Modulators

in DATE Design Automation and Test in Europe Conference, Paris, France, pages 674-675, 2004.

Cécile Braunstein and Emmanuelle Encrenaz

CTL-Property Transformations along an Incremental Design Process

in AVOCS International Workshop on Automated Verification of Critical Systems, London, England, pages 263-278, 2004.

Diaaeldin Khalil, Mohamed Dessouky, Vincent Bourguet, Marie-Minerve Rosset-Louërat, Andreia Cathelin and Hani Ragai

Compensated Layout for Automated Accurate Common-Centroid Capacitor Arrays

in ICEEC International Conference on Electrical Electronic and Computer Engineering, Cairo, Egypt, pages 481-484, 2004.

Ramy Iskander, Laurent de Lamarre, Andreas Kaiser and Marie-Minerve Rosset-Louërat

Design Space Exploration for Analog IPs using CAIRO+

in ICEEC International Conference on Electrical Electronic and Computer Engineering, Cairo, Egypt, pages 473-476, 2004.

Patricia Renault and Pirouz Bazargan Sabet

Determining The Analytic Waveform of an RC-Circuit Output

in MIXDES Mixed Design of Integrated Circuits and Systems, Szczecin, Poland, pages 363-368, 2004.

Ivan Augé, Frédéric Pétrot, Richard Buchmann, François Donnet, Pascal Gomez and Etienne Faure

Disydent : un environnement pour la conception de systèmes numériques synchrones

in SCS congrès international de Signaux Circuits et Systèmes, Monastir, Tunisie, pages 72-77, 2004.

Richard Buchmann, Alain Greiner and Frédéric Pétrot

Fast Cycle Accurate Simulation To Simulate Event-Driven Behavior

in ICEEC International Conference on Electrical Electronic and Computer Engineering, Cairo, Egypt, pages 37-40, 2004.

Nicolas Beilleau, Hassan Aboushady and Marie-Minerve Rosset-Louërat

Filtering Adjacent Channel Blockers using Signal-Transfer-Function of Continuous-Time Sigma-Delta Modulators

in MWSCAS Midwest Symposium on Circuits and Systems, Hiroshima, Japon, pages 329-332, 2004.

Pierre Nguyen-Tuong, Marie-Minerve Rosset-Louërat and Alain Greiner

Guidelines for Designing Smart and Reusable Analog IP Cores

in SAME Sophia Antipolis MicroElectronics Forum, Sophia Antipolis, France, 2004.

Ludovic Noury and Habib Mehrez

Générateur de netlist de filtres numériques RIF optimisés

in JNRDM Journées Nationales du Réseau Doctoral en Microélectronique, Marseille, France, pages 451-453, 2004.

Mouhamadou Diaby, Matthieu Tuna, Jean-Lou Desbarbieux and Franck Wajsburt

High level synthesis methodology from C to FPGA used for a network protocol communication.

in RSP International Workshop on Rapid System Prototyping, Geneva, Switzerland, pages 103-108, 2004.

Hassan Aboushady and Marie-Minerve Rosset-Louërat

Loop Delay Compensation in Bandpass Continuous-Time Modulators without Additional Feedback Coefficients

in ISCAS IEEE International Symposium on Circuits and Systems, Vancouver, Canada, pages 1124-1127, 2004.

Pierre Nguyen-Tuong, Marie-Minerve Rosset-Louërat and Alain Greiner

Managing the Shape Function of Analog Devices in a Slicing Tree Floorplan

in Mixed Design of Integrated Circuits and Systems (MIXDES), Szczecin, Poland, pages 226-229, 2004.

Etienne Faure, Daniela Genius, Frédéric Pétrot and Saifeddine Berrayana

Modular on chip multi processor for routing applications

in Euro-Par European Conference on Parallel computing, Pise, Italie, pages 847-855, 2004.

Mounir Benabdenbi, Alain Greiner, François Pêcheux, Emmanuel Viaud and Matthieu Tuna

STEPS: experimenting a new software-based strategy for testing SoCs containing P1500-compliant IP cores

in DATE Design Automation and Test in Europe Conference, Paris, France, pages 712-713, 2004.

Matthieu Tuna and Emmanuel Viaud

STEPS: une approche logicielle pour le test des circuits intégrés sur puce (SoC)

in JNRDM Journées Nationales du Réseau Doctoral en Microélectronique, Marseille, France, pages 263-265, 2004.

Patricia Renault and Pirouz Bazargan Sabet

Splitting of RC-Network for Accurate Model Reduction

in ICM International Conference on Microelectronics, Tunis, Tunisia, pages 734-737, 2004.

Ludovic Noury, Habib Mehrez, François Durbin and André Tissot

Use of multiple numeration systems for architecture and design of a high performance FIR filter netlist generator

in ICM International Conference on Microelectronics, Tunis, Tunisia, pages 547-550, 2004.

Hervé Charlery, Alain Greiner, Emmanuelle Encrenaz, Laurent Mortiez and Adrijean Andriahantenaina

Using VCI in a on-chip system around SPIN network

in MIXDES Mixed Design of Integrated Circuits and Systems, Szczecin, Poland, pages 571-576, 2004.

Vincent Beaudenon and Emmanuelle Encrenaz

Utilisation de Diagrammes de Décision de Données pour la Vérification Fonctionnelle de Systèmes Matériels

in MAJECTSTIC MAnifestation des JEunes Chercheurs STIC, Calais, France, 2004.

Michaël Dupré, Nathalie Drach and Olivier Temam

VHC: Quickly Building an Optimizer for Complex Embedded Architectures

in CGO IEEE/ACM International Symposium on Code Generation and Optimization, San Jose, California, USA, pages 53-64, 2004.

Livres

Articles

Proceedings