7 | | The TSAR architecture implements two atomic read-then-write operations to support various synchronization mechanisms : |
8 | | * The '''LL/SC''' (Linked Load / Store Conditional) operations are implemented as TWO specific Command/Response VCI transactions. As the LL/SC instructions are implemented in the MIPS32 instruction set, these instructions van be used by both the kernel code and by the application code to read a data at address X, test this data, and write the (possibly modified) data at the same address X, with the guaranty that no other access to this data was done between the read and write access. |
9 | | * The '''CAS''' (Compare and Swap) operation is implemented as ONE specific Command/Response VCI transaction. As there is no CAS instruction in the MIPS32 instruction set, this operation is cannot be used by the software. It is only used by some hardware components such as the MMU contained in the L1 cache controller (to update the DIRTY bit in the page tables), or by some DMA peripheral such as the vci_mwmr_dma component to atomically access the lock protecting a shared communication channel. |
| 7 | The TSAR architecture implements two read-then-write atomic operations to support various synchronization mechanisms : |
| 8 | * The '''LL/SC''' (Linked Load / Store Conditional) operation is implemented as two specific VCI transactions. As the LL/SC instructions are implemented in the MIPS32 instruction set, these instructions can be used by both the kernel code and by the application code to read a data at address X, test this data, and write the (possibly modified) data at the same address X, with the guaranty that no other access to this address was done between the read and write access. |
| 9 | |
| 10 | * The '''CAS''' (Compare and Swap) operation is implemented as a specific VCI transaction. As there is no CAS instruction in the MIPS32 instruction set, this operation cannot be used by the software. It is only used by some hardware components such as the L1 cache controller (to allow the MMU to update the DIRTY bit in the page tables), or by some DMA peripheral such as the vci_mwmr_dma component (to atomically access the lock protecting a shared communication channel). |
22 | | * When a processor P executes the SC(X,D) instruction to an address X, this conditional write is sent to the L2 cache by the L1 cache, and the command contains also the reservation key K and the data to be written D. The L2 cache makes an associative search in the ''reservation table''. If both the address X and the key K matches, the atomic operation is a success : The reservation is canceled in the ''reservation table'', the D value is written at address X, and a ''success'' value is returned in the response to the L1 cache. If there is no match in the ''associative table'', the atomic operation is a failure: the D value is not written at address X, the ''reservation table is not modified, and a ''failure'' value is returned to the L1 cache. |
| 23 | * When a processor P executes the SC(X,D) instruction to an address X, this conditional write is sent to the L2 cache by the L1 cache, and the command contains both the reservation key K and the data to be written D. The L2 cache makes an associative search in the ''reservation table''. If both the address X and the key K match, the atomic operation is a success : The reservation is canceled in the ''reservation table'', the D value is written at address X, and a ''success'' value is returned to the L1 cache. If there is no match in the ''associative table'', the atomic operation is a failure: the D value is not written at address X, the ''reservation table is not modified, and a ''failure'' value is returned to the L1 cache. |
51 | | We summarize |
| 55 | Each entry in the ''reservation table'' contains 3 fields to store one reservation: |
| 56 | * physical address : 40 bits |
| 57 | * reservation key : 32 bits |
| 58 | * valid reservation : 1 bit |
| 59 | |
| 60 | We summarize below the actions done by the L2 cache controller receiving a LL(X), SC(X,D,K) or SW(X,DT) VCI command from a L1 cache controller: |
| 61 | * '''LL(X)''' : The L2 cache makes an associative search on the X address in the ''reservation table''. In case of hit (X = Xr), the L2 cache returns both the D value stored at address X, and the K value stored in the ''reservation table'' to the L1 cache. In case of miss, the L2 cache allocates a new K value from the key allocator, |
| 62 | registers a new entry in the ''reservation table''(this can require a victim eviction), and returns the D and K values to the L1 cache. |
| 63 | * '''SC(X,D,K)''' : The L2 cache makes an associative search on both the the X address and the K key in the ''reservation table''. In case of hit, the reservation is invalided in the ''reservation table'', the D value is written at address X, and a ''success'' value is returned to the L1 cache. In case of miss, the D value is not written at address X, the ''reservation table'' is not modified, and a ''failure'' value is returned to the L1 cache. |
| 64 | * '''SW(X,D)''' : The L2 cache makes an associative search on the X address in the ''reservation table''. As the write command can be a burst, with a Xmin and Xmax addresses, the HIT condition for each entry containing an address Xr is actually Xmin <= Xr <= Xmax. In case of hit, the reservation Xr is invalidated. In case of miss, the entry containing Xr is not invalided. In both cases the D value is written at address X. |