Changes between Version 10 and Version 11 of VirtualMemory
- Timestamp:
- Jun 28, 2009, 1:17:05 PM (15 years ago)
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VirtualMemory
v10 v11 5 5 The TSAR MMU (Memory Management Unit) is an hardware component implemented in the L1 cache controller. This cache controller is a generic component that can be used with any single instruction issue, 32 bits processor. As any MMU, the generic TSAR MMU is in charge of the virtual to physical address translation, and perfoms 6 6 access right verifications. It implements a paginated virtual memory, supporting two page sizes : 4 Kbytes pages, and 2 Mbytes pages. 7 8 [[Image(generic_mmu.png, nolink)]] 7 9 8 10 As the processor core can issue two simultaneous instruction and data requests, there is actually two separated data and instructions caches, … … 33 35 It is implemented as a single 32 bits word : 34 36 35 * PTE1 :37 * PTE1 : 36 38 ||V||T||L||R||C||W||X||U||G||D|| reserved (3 bits) || PPN1 (19 bits) || 37 39 … … 100 102 == 2. Generic MMU == 101 103 102 For each TSAR programmable processor, the generic MMU is implemented as an hardware component in the L1 cache controller.104 The generic MMU is implemented as an hardware component in the L1 cache controller. 103 105 As the processor core can issue two simultaneous instruction and data requests, there is actually two separated data and instructions caches, 104 sharing the same physical access to the VCI/OCP interconnect. These L1 caches use physical addresses. 106 sharing the same physical access to the VCI/OCP interconnect. These cache are set associative, and have a total capacity of 16 Kbytes : 107 * cache line width = 64 bytes 108 * number of associative sets = 64 sets 109 * number of associative ways = 4 ways 110 105 111 Similarly, the L1 cache controller contains two separated hardware MMUs for instruction and data. Each MMU contains a 64 entries TLB (Translation Look-aside Buffer). 106 112 These TLBs are implemented as set-associative caches (8 sets of 8 ways). Each entry in these TLBs can contain either a 4 Kbytes page descriptor, or a 2 Mbytes page descriptor.
