Changes between Version 15 and Version 16 of VirtualMemory

Timestamp:

Jun 30, 2009, 2:19:06 PM (15 years ago)

Author:

alain

Comment:

--

VirtualMemory

@@ -111 +111 @@
 
 The data cache L1 implement a writhe-through policy, in order to simplify the cache-coherence protocol.
-It contains a write-buffer and that is in charge to build write burst, withe the following constraints :
+It contains a write-buffer that is in charge to build write burst, withe the following constraints :
  * the burst length is variable
  * the maximal burst length is 8 32 bits words
@@ -143 +143 @@
 || Exeption type                              || code  || cause                                                         || severity ||
 ||                                                       ||            ||                                                                    ||                      ||
-||MMU_PT1_UNMAPPED                ||            || Page fault on Table1 (invalid PTE)   || non fatal error ||
-||MMU_PT2_UNMAPPED                ||            || Page fault on Table 2 (invalid PTE)  || non fatal error ||
-||MMU_PRIVILEGE_VIOLATION         ||            ||Protected access in user mode         || user  error ||
-||MMU_WRITE_VIOLATION             ||            || Write access to a non write page             || user error ||
-||MMU_EXEC_VIOLATION              ||            || Exec access to a non exec page               || user error ||
-||MMU_UNDEFINED_XTN               ||            || Undefined external access address     || user error ||
-||MMU_PT1_ILLEGAL_ACCESS          ||            || Bus Error accès Table1                               || kernel error ||
-||MMU_PT2_ILLEGAL_ACCESS          ||            || Bus Error accès Table2                               || kernel error ||
-||MMU_CACHE_ILLEGAL_ACCESS ||            || Bus Error during the cache access      ||kernel error ||
+||MMU_PT1_UNMAPPED                ||    1      || Page fault on Table1 (invalid PTE)    || non fatal error ||
+||MMU_PT2_UNMAPPED                ||     2       || Page fault on Table 2 (invalid PTE)         || non fatal error ||
+||MMU_PRIVILEGE_VIOLATION         ||       4     ||Protected access in user mode                || user  error ||
+||MMU_WRITE_VIOLATION             ||         8   || Write access to a non write page            || user error ||
+||MMU_EXEC_VIOLATION              || 0x10 || Exec access to a non exec page             || user error ||
+||MMU_UNDEFINED_XTN               || 0x20           || Undefined external access address     || user error ||
+||MMU_PT1_ILLEGAL_ACCESS          || 0x40           || Bus Error accès Table1                           || kernel error ||
+||MMU_PT2_ILLEGAL_ACCESS          || 0x080           || Bus Error accès Table2                          || kernel error ||
+||MMU_CACHE_ILLEGAL_ACCESS || 0x100           || Bus Error during the cache access      ||kernel error ||
 
 
@@ -165 +165 @@
 || register name               || index  || description                                                    || mode ||
 ||                                         ||             ||                                                                         ||            ||
-|| MMU_PTPR                    ||             || Page Table Pointer Register                       || R/W   ||
-|| MMU_MODE                 ||             || Data & Inst TLBs Mode Register                || R/W   ||
-|| MMU_ICACHE_FLUSH   ||                    || Instruction Cache flush                          || W       ||
-|| MMU_DCACHE_FLUSH ||              || Data Cache flush                                         || W       ||
-|| MMU_ITLB_INVAL         ||             || Instruction TLB line invalidation                || W       ||
-|| MMU_DTLB_INVAL           ||             || Data TLB line Invalidation                                || W       ||
-|| MMU_ICACHE_INVAL   ||             || Instruction Cache line invalidation            || W       ||
-|| MMU_DCACHE_INVAL  ||             || Data Cache line invalidation                       || W       ||
-|| MMU_IETR                         ||             || Instruction Exception Type Register          || R/W  ||
-|| MMU_IBVAR                   ||             || Instruction Bad Virtual Address Register  || R/W  ||
-|| MMU_DETR                    ||             || Data Exception Type Register                    || R/W   ||
-|| MMU_DBVAR                 ||             || Data Bad Virtual Address Register             || R/W  || 
+|| MMU_PTPR                    ||    0       || Page Table Pointer Register                       || R/W   ||
+|| MMU_MODE                 ||    1       || Data & Inst TLBs Mode Register                || R/W   ||
+|| MMU_ICACHE_FLUSH   ||           2       || Instruction Cache flush                           || W       ||
+|| MMU_DCACHE_FLUSH ||     3       || Data Cache flush                                          || W       ||
+|| MMU_ITLB_INVAL         ||    4       || Instruction TLB line invalidation                || W     ||
+|| MMU_DTLB_INVAL           ||   5        || Data TLB line Invalidation                         || W      ||
+|| MMU_ICACHE_INVAL   ||    6       || Instruction Cache line invalidation            || W     ||
+|| MMU_DCACHE_INVAL  ||    7      || Data Cache line invalidation                       || W     ||
+|| MMU_IETR                         ||    8      || Instruction Exception Type Register          || R      ||
+|| MMU_IBVAR                   ||   9       || Instruction Bad Virtual Address Register  || R      ||
+|| MMU_DETR                    ||  10      || Data Exception Type Register                       || R      ||
+|| MMU_DBVAR                 ||  11      || Data Bad Virtual Address Register             || R      ||