Nathalie DRACH-TEMAM

Professeur / Professor

Université Pierre et Marie Curie - UPMC (Paris 6)

Laboratoire d'Informatique de Paris 6 (LIP6)

 


 

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·               A. Drebes, A.Pop, K. Heydemann, A. Cohen, N. Drach : Scalable Task Parallelism for NUMA: A Uniform Abstraction for Coordinated Scheduling and Memory Management. International Conference on Parallel Architectures and Compilation Techniques (PACT), 2016 (Best paper award).

·               A. Drebes, A. Pop, K. Heydemann, N. Drach, A. Cohen : NUMA-aware scheduling and memory allocation for data-flow task-parallel applications. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPOPP),  2016.

·               A. Drebes, K. Heydemann, N. Drach, A. Pop, A. Cohen : Topology-aware and dependence-aware scheduling and memory allocation for task-parallel languages. ACM Transactions on Architecture and Code Optimization (TACO), 2014.

·               A. Drebes, K. Heydemann, A. Pop, A. Cohen, N. Drach : Automatic Detection of Performance Anomalies in Task-Parallel Programs. 19th IEEE European Test, workshop Resource-awareness and Adaptivity in multi-core ComputING Symposium, 2014.

·               A. Drebes, K. Heydemann, N. Drach, P. Antoniu, A. Cohen : Aftermath: Performance analysis of task-parallel applications on many-core NUMA systems, Tenth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, 2014.

·               A. Drebes, A. Pop, K. Heydemann, A. Cohen, N. Drach : Aftermath: A graphical tool for performance analysis and debugging of fine-grained task-parallel programs and run-time systems. International Conference on High-Performance and Embedded Architectures and Compilers, workshop Programmability Issues for Heterogeneous Multicores, 2014.

·               M. Rosière, J.-L. Desbarbieux, N. Drach, F. Wajsbürt : An Out-of-Order Superscalar Processor on FPGA: The ReOrder Buffer Design, DATE Design Automation and Test in Europe Conference, Allemagne, 2012.

·               O. Gamoudi, N. Drach, K. Heydemann : Using runtime activity to dynamically filter out inecient data prefetches, 17th International European Conference on Parallel and Distributed Computing Euro-Par 2011, France, 2011.

·               M.-H. Nguyen, B. Robisson, M. Agoyan, N. Drach : Low-cost recovery for the code integrity protection in secure embedded processors, IEEE International Symposium on Hardware-Oriented Security and Trust HOST, USA, 2011.

·               M. Rosière, J.‑L. Desbarbieux, N. Drach, F. Wajsbürt : MORPHEO: a high-performance processor generator for a FPGA implementation, IEEE Conference on Design and Architectures for Signal and Image Processing DASIP, Finlande, 2011.

·               B. Robisson, M. Agoyan, S. Bouquet, M.-H. Nguyen, S. Le Henaff, P. Soquet, G. Phan, F. Wajsbürt, P. Bazargan-Sabet, N. Drach : Management of the security in smart secure devices, Smart Systems Integration Conference, Suisse, 2011.

·               M. Daumas, N. Drach (ouvrage collectif sous la direction de) : Architecture des ordinateurs, Revue Technique et Science Informatiques (TSI), vol. 29, n° 2, édition Hermès, 2010.

·               M.-H. Nguyen, B. Robisson, M. Agoyan, N. Drach : Low-cost fault tolerance on the ALU in simple pipelined processors. IEEE conference DDECS - Design and Diagnostics of Electronic Circuits and Systems, Autriche, 2010.

·               M.-H. Nguyen, B. Robisson, N. Drach : Evaluation of the Time Redundant Fault Tolerance on the ALU for Simple Pipelined Processors, 4th Annual Austin Conference on Integrated Systems & Circuits, Etats-Unis, 2009.

·               O. Gamoudi, N. Drach, K.Heydemann : Vers une méthode adaptative de préchargement de données, Symposium en Architecture de Machines, France, 2009.

·               Djabelkhir Assia, Drach Nathalie, Heydemann Karine, Arzel Frédéric : Parallélisation supervisée pour les multicoeurs embarqués, Symposium en Architecture de Machines, France, 2009.

·               Coveliers, K. Heydemann, N. Drach : Sensibilité aux jeux de données de la compilation itérative, Revue Technique et Science Informatiques (TSI), vol. 27, n°6, 2008.

·               O. Certner, L. Zheng, P. Palatin, O. Temam, F. Arzel, N. Drach : A Practical Approach for Reconciling High and Predictable Performance in Non-Regular Parallel Programs, International Workshop on Programmability Issues for Multi-Core Computers , Suède, 2008.

·               O. Certner, P. Palatin, Z. Li, O. Temam, F. Arzel, N. Drach : A Practical Approach for Reconciling High and Predictable Performance in Non-Regular Parallel Programs, DATE Design Automation and Test in Europe Conference , Allemagne, 2008.

·               Coveliers, K. Heydemann, N. Drach : Sensibilité aux jeux de données de la compilation itérative, SympA Symposium en Architecture de Machines , France, pp. 35-46, 2006.

·               Limousin, J. Sebot, A. Vartanian, N. Drach : Architecture Optimization for Multimedia Application Exploiting Data and Thread-Level Parallel, Journal of Systems Architecture, Elsevier Science. Volume 51, Issue 1, pages 15-27, 01/2005.

·               M. Dupré, N. Drach, O. Temam : VHC: Quickly Building an Optimizer for Complex Embedded Architectures, IEEE-ACM International Symposium on Code Generation and Optimization", pages 53-64, USA, 2004.

·               M. Dupré, N. Drach : Algorithme d’ordonnancement dynamique pour exécution statique, Revue Technique et Science Informatiques (TSI), p. 713-735, vol. 22, 11/2003.

·               N. Drach, J.-L. Béchennec, O. Temam: Increasing Hardware Data Prefetching Performance Using the Second-Level Cache, Journal of Systems Architecture, Elsevier Science. Volume/Issue 48/4-5, pages 137-149, 11/2002.

·               J. Sebot, N. Drach : SIMD ISA Extensions: Power Efficiency on Multimedia, IEICE Transactions on Electronics, special issue on high-performance and low-power microprocessors, éditeur Oxford University Press. Volume E85-C, numéro 2, 2002.

·               M. Dupré, N. Drach : Algorithme d’ordonnancement dynamique pour exécution statique, 8ème Symposium en Architectures Nouvelles de Machines (Sympa), 2002.

·               J. Sebot, N. Drach : Memory Bandwidth: the True Bottleneck of SIMD Multimedia Performance on a Superscalar Processor, European Conference on Parallel Computing (EuroPar), LNCS, p. 439-447, Vol. 2150, Springer-Verlag,  2001.

·               J. Sebot, N. Drach : SIMD ISA Extensions : Reducing Power Consumption on a Superscalar Processor for Multimedia applications,  International Symposium on Low-Power and High-Speed Chips (Cool Chips IV), ACM-IEEE, 2001.

·               Limousin, J. Sebot, A. Vartanian, N. Drach : Improving 3D Geometry Transformations on a Simultaneous Multithreaded SIMD, International Conference on Supercomputing (ICS), p. 236 - 245, ACM, 2001.

·               J. Sebot, N. Drach : Extensions SIMD et superscalaire dans l'ordre :  une solution pour réduire la consommation des applications multimédia, 7ème Symposium en Architectures Nouvelles de Machines (Sympa), 2001.

·               Limousin, J. Sebot, A. Vartanian, N. Drach : Amélioration des performances des transformations géométriques 3D temps réel sur un processeur SMT SIMD, 7ème Symposium en Architectures Nouvelles de Machines (Sympa), 2001.

·               N. Drach, J. Sebot : SIMD ISA Extensions : Tradeoff between Power Consumption and Performance on a Superscalar Processor. In Kool Chips Workshop, International Symposium on Microarchitecture (MICRO) ACM-IEEE, 2000.

·               Vartanian, J.-L. Béchennec, N. Drach : The Best Distribution for a Parallel OpenGL 3D Engine with Texture Caches, International Symposium on High-Performance Computer Architecture (HPCA), IEEE, 2000.

·               Limousin, N. Drach, J-.L. Béchennec : Politiques d'émission pour un processeur SMT, 6ème Symposiun en Architectures Nouvelles de Machines (Sympa), 2000.

·               J. Sébot, A. Vartanian, J.-L. Béchennec, N. Drach : A Parallel Algorithm for 3D Geometry Transformations in OpenGL, European Conference on Parallel Computing (EuroPar), LNCS, Vol. 1685, Springer-Verlag, 1999.

·               Vartanian, J.-L. Béchennec, N. Drach : Two Schemes to Improve the Performance of Sort-Last 3D Parallel Rendering Machine with Texture Caches, European Conference on Parallel Computing (EuroPar), LNCS, Vol. 1685, Springer-Verlag, 1999.

·               Vartanian, J-L. Béchennec, N. Drach : Evaluation of High Performance Multicache Parallel Texture Mapping, International Conference on Supercomputing (ICS), p. 289 - 296,  ACM, 1998.

·               V. Branger, N. Drach : Performance du préchargement de données dans les processeurs superscalaires, Revue Technique et Science Informatiques (TSI), 1997.

·               O. Temam, N. Drach : Software Assistance for Data Caches, Future Generation Computer Systems, special issue on High-Performance Computer Architecture, éditeur Elsevier Science. Volume 11, numéro 6, 1996.

·               N. Drach, E. Rohou, A. Seznec : Influence de la structure du pipeline sur les instructions de chargement, Revue Technique et Science Informatiques (TSI), 1996.

·               V. Branger, N. Drach : Impact du parallèlisme instructions sur le préchargement de données aux différents niveaux de la hiérarchie mémoire, 8ème Rencontres du Parallélisme (RenPar), 1996.

·               V. Branger, N. Drach : Etude de la localité des références sur le second niveau de cache, Symposium Architectures Nouvelles des Machines (Sympa), 1996.

·               N. Drach, A. Gefflaut, P. Joubert, A. Seznec : About Cache Associativity in Low-Cost Shared Memory Multi-Microprocessors, Parallel Processing Letters, éditeur World Scientific. Volume 5, numéro 3, 1995.

·               N. Drach : Hardware Implementation Issues of Data Prefetching, International Conference on Supercomputing (ICS), ACM,  p. 245 - 254, 1995.

·               N. Drach, A. Seznec, D.Windheiser : Direct-Mapped Versus Set-Associative Pipelined Caches, International Conference on Parallel Architectures and Compilation Techniques (PACT), ACM-IEEE, 1995.

·               O. Temam, N. Drach : Software Assistance for Data Caches, International Symposium on High-Performance Computer Architecture (HPCA), p. 154-163, IEEE, 1995.

·               N. Drach, D. Windheiser : Comparaison des caches pipelinés à correspondance directe et associatifs par ensemble, 6ème rencontres du parallélisme (RenPar), 1994.

·               N. Drach, A. Seznec : Semi-Unified Caches: Increasing Associativity of On-Chip Caches, IEEE TC on Computer Architecture Newsletter, éditeur IEEE Computer Society, 1993.

·               N. Drach, A. Seznec : MIDEE: Smoothing Branch and Intruction Cache Miss Penalties on Deep Pipelines, International Symposium on Microarchitecture (Micro), ACM-IEEE, 1993.

·               N. Drach, A. Seznec : Semi-Unified Caches, International Conference on Parallel Processing (ICPP), 1993.

·               N. Drach, A. Seznec : Les caches semi-unifiés, 5ème rencontres du parallélisme (RenPar), 1993.

 

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