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A. Korniienko, E. Colinet, G. Scorletti, E. Blanco, D. Galayko and J. Juillard, A clock network of distributed ADPLLs using an asymmetric comparison strategy, International Symphosium on Circuits and System (ISCAS), april 2010, pp. 3212-3215
J. M. Akre, J. Juillard, D. Galayko and E. Colinet, Synchronized State in Networks of Digital Phase-Locked Loops, The 8th IEEE International NEWCAS Conference (NEWCAS'10), Montreal : Canada (2010) E. Zianbetov, M. Javidan, F. Anceau, D. Galayko, E. Colinet, J. Juillard, Design and VHDL Modeling of All-Digital PLLs, 8th IEEE International NEWCAS Conference (NEWCAS’10), pp. 293-296, Montreal, Canada, June 20-23, 2010 J-M. Akré, J. Juillard, S. Olaru, D. Galayko, E. Colinet, Determination of the Behaviour of Self-Sampled Digital Phase-Locked Loops, 53rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS’10), pp. 1089-1092, Seattle, Washington (USA), August 1-4, 2010 E. Zianbetov, M. Javidan, F. Anceau, D. Galayko, E. Colinet and J. Juillard, "Design and VHDL Modeling of All-Digital PLLs", 8th IEEE International NEWCAS Conference (NEWCAS'10), Montreal, Canada, June 20-23, 2010 M. Javidan, E. Zianbetov, F. Anceau, D. Galayko, E. Colinet, A. Korniienko and J. Juillard, All-digital PLL array provides reliable distributed clock for SOCs, , IEEE International Symposium on Circuits and Systems ISCAS2011, may 2011, Rio de Janeiro, Brazil E. Zianbetov, M. Javidan, F. Anceau, D. Galayko, E. Colinet and J. Juillard, A 2 GHz CMOS DCO with optimized architecture for high speed clocking, , IEEE International Symposium on Circuits and Systems ISCAS2011, may 2011, Rio de Janeiro, Brazil M. Javidan, E. Zianbetov, F. Anceau, D. Galayko, E. Colinet and J. Juillard, Novel technique to reduce the metastability of bang-bang phase-frequency detector, , IEEE International Symposium on Circuits and Systems ISCAS2011, may 2011, Rio de Janeiro, Brazil A. Korniienko, G. Scorletti, E. Colinet, E. Blanco, J. Juillard and D. Galayko, Control Law Synthesis for Distributed Multi-Agent Systems: Applications to Active Clock Distribution Network, Automatic and Control Conference (ACC 2010), San Francisco, CA, 2010 J. M. Akré, J. Juillard, D. Galayko, E. Colinet, Synchronization Analysis of Networks of Self-Sampled All-Digital Phase-Locked Loops, IEEE Journal of Transactions on Circuits and Systems I, accepted in august 2011 J.M. Akré, J. Juillard, M. Javidan, E. Zianbetov, D. galayko, A. Korniienko, E. Colinet, A Design Approah for Networks of self-Sampled All-Digital Phase-Locked Loops, 20th European Conference on Circuit theory and Design (ECCTD'11),pp. 795-798, Linköping, Sweden, August 29-31, 2011 C. Shan, E. Zianbetov, M. Javidan, F. Anceau, M. Terosiet, S. Féruglio, D. Galayko, O. Romain, É. Colinet, J. Juillard, FPGA Implementation of Reconfigurable ADPLL Network for Distributed Clock Generation, accepted in 2011 International Conference on Field Programmable Technology, december 2011, New Dely, India |