Generate ( 'DpgenInv', modelname , param = { 'nbit' : n , 'drive' : d , 'physical' : True , 'behavioral' : True } )
n
bits inverter with an output power of d
named modelname
.
n
bits)
n
bits)
param
.
nq <= not ( i0 )
from stratus import * class inst_inv ( Model ) : def Interface ( self ) : self.i = SignalIn ( "i", 54 ) self.o = SignalOut ( "o", 54 ) self.vdd = VddIn ( "vdd" ) self.vss = VssIn ( "vss" ) def Netlist ( self ) : Generate ( 'DpgenInv', 'inv_54' , param = { 'nbit' : 54 , 'physical' : True } ) self.I = Inst ( 'inv_54', 'inst' , map = { 'i0' : self.i , 'nq' : self.o , 'vdd' : self.vdd , 'vss' : self.vss } ) def Layout ( self ) : Place ( self.I, NOSYM, Ref(0, 0) )