Generate ( 'DpgenNul', modelname , param = { 'nbit' : n , 'physical' : True } )
n
bits zero detector named modelname
.
n
bits)
param
.
q <= '1' WHEN ( i0 = X"00000000" ) ELSE '0';
from stratus import * class inst_nul ( Model ) : def Interface ( self ) : self.i = SignalIn ( "i", 4 ) self.o = SignalOut ( "o", 1 ) self.vdd = VddIn ( "vdd" ) self.vss = VssIn ( "vss" ) def Netlist ( self ) : Generate ( 'DpgenNul', 'nul_4' , param = { 'nbit' : 4 , 'physical' : True } ) self.I = Inst ( 'nul_4', 'inst' , map = { 'i0' : self.i , 'nul' : self.o , 'vdd' : self.vdd , 'vss' : self.vss } ) def Layout ( self ) : Place ( self.I, NOSYM, Ref(0, 0) )