Example :
from stratus import *
class inst_nand4 ( Model ) :
def Interface ( self ) :
self.in1 = SignalIn ( "in1", 9 )
self.in2 = SignalIn ( "in2", 9 )
self.in3 = SignalIn ( "in3", 9 )
self.in4 = SignalIn ( "in4", 9 )
self.o = SignalOut ( "o", 9 )
self.vdd = VddIn ( "vdd" )
self.vss = VssIn ( "vss" )
def Netlist ( self ) :
Generate ( 'DpgenNand4', 'nand4_9'
, param = { 'nbit' : 9
, 'physical' : True
}
)
self.I = Inst ( 'nand4_9', 'inst'
, map = { 'i0' : self.in1
, 'i1' : self.in2
, 'i2' : self.in3
, 'i3' : self.in4
, 'nq' : self.o
, 'vdd' : self.vdd
, 'vss' : self.vss
}
)
def Layout ( self ) :
Place ( self.I, NOSYM, Ref(0, 0) )