Example :
from stratus import *
class inst_and3 ( Model ) :
def Interface ( self ) :
self.in1 = SignalIn ( "in1", 16 )
self.in2 = SignalIn ( "in2", 16 )
self.in3 = SignalIn ( "in3", 16 )
self.out = SignalOut ( "o", 16 )
self.vdd = VddIn ( "vdd" )
self.vss = VssIn ( "vss" )
def Netlist ( self ) :
Generate ( 'DpgenAnd3', "and3_16"
, param = { 'nbit' : 16
, 'physical' : True
}
)
self.I = Inst ( 'and3_16', 'inst'
, map = { 'i0' : self.in1
, 'i1' : self.in2
, 'i2' : self.in3
, 'q' : self.out
, 'vdd' : self.vdd
, 'vss' : self.vss
}
)
def Layout ( self ) :
Place ( self.I, NOSYM, Ref (0, 0) )