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Lionel Lacassagne
Laboratoire d'Informatique de Paris 6 (LIP6) - Universite Pierre et Marie Curie (UPMC)
System on Chip Department (SoC)
Publications
International Journals
  1. JRTIP Journal of Real Time Image Processing: "Parallel Light Speed Labeling: an efficient connected component algorithm for labeling and analysis on multi-core processors" L. Cabaret, L. Lacassagne, D. Etiemble, 2016 (Springer Link).

  2. MVA Machine Vision and Applications: "A modular system for global and local abnormal event detection and categorization in videos" A. C. Ben Abdallah, M. Gouiffès, L. Lacassagne, 2016 (Springer Link).

  3. Eurasip Journal on Advances in Signal Processing "Covariance tracking: architecture optimizations for embedded systems" A. Roméro, L. Lacassagne, M. Gouiffès, A. Hassan Zahraee, 2014 (Eurasip Open Access ink).

  4. JRTIP Journal of Real Time Image Processing "Color tracking with contextual switching: Real-time implementation on CPU" F. Laguzet, A. Roméro, M. Gouiffès, L. Lacassagne, D. Etiemble, 2013 (Springer Link).

  5. JRTIP Journal of Real Time Image Processing "Light Speed Labeling: Efficient Connected Component Labeling on RISC Architectures" L. Lacassagne, B. Zavidovique , pp. 117-135, 2010 (Springer Link).

  6. HiPEAC: Transactions on High-Performance Embedded Architectures and Compilers 2008 "Parallelization Schemes for Memory Optimization on the Cell Processor : A Case Study on the Harris Corner Detector" T. Saidani, L. Lacassagne, J. Falcou, C. Tadonki, S. Bouaziz., vol. 3, n° 3.

  7. JRTIP Journal of Real Time Image Processing "High Performance Motion Detection: Some trends toward new embedded architectures for vision systems" L. Lacassagne, A. Manzanera, J. Denoulet, A. Mérigot, pp. 127-148, 2008.(SpringerLink)

  8. International Journal on Information and Communication Technologies "A Statistical Approach for High Speed Long Word Addition". S. Bouaziz, B. Larnaudie, E. Elouardi, L. Lacassagne, 2008,.

  9. International Journal of Computer Sciences and Application 2008 "Altivec Vector Unit Customization for embedded Systems". T. Saidani, J. Falcou, L. Lacassagne, S. Bouaziz. Vol 5, issue 3a, Special Issue : New trends in Information and Communicatoin Technologies Applications. pp.20-32. 2008.

  10. International Journal of Computer Sciences and Application 2008 " A Smart Architecture for Low-Level Image Computing" A. Elouardi, S. Bouaziz, A. Dupret, L. Lacassagne, J.O. Klein and R. Reynaud. Vol 5, issue 3a, Special Issue : New trends in Information and Communicatoin Technologies Applications. pp.1-19. 2008.

  11. EURASIP 2007 EURASIP Journal on Embedded Systems "System-Platforms-Based SystemC TLM Design of Image Processing Chains for Embedded Applications", Muhammad Omer Cheema, Lionel Lacassagne, and Omar Hammami, Volume 2007 (2007), Article ID 71043, pp. 46-52.

  12. MST 2007 IOP Measurement Science and Technology: "Time comparison in image processing: APS sensors versus an artificial retina based vision system", A Elouardi, S Bouaziz, A Dupret, L Lacassagne, J O Klein and R Reynaud ( IOP Link), pp. 2817-2826, doi doi:10.1088/0957-0233/18/9/011

  13. Journal of Applied Physics "A smart sensor based vision system: implementation and evaluation" A. Elouardi, S. Bouaziz, A. Dupret, L. Lacassagne, J.O. Klein, R. Reynaud. Vol. 39, pp1694-1705. 2006.

Electronical Journals
  1. IEEE Transcations on Instrumentation and Measurement "Image Processing Vision Systems: Standard Image Sensors Versus Retinas" A. Elouardi, S. Bouaziz, A. Dupret, L. Lacassagne, J.O. Klein, R. Reynaud IEEE Transactions on Instrumentation and Measurement, vol. 56, no 4, august 2007

  2. Multimedia Systems Design Magazine 1998 "A DSP implementation of optimal edge detectors" F. Lohier, L. Lacassagne, P. Garda.
National Journals
  1. Traitement du Signal 2010 "Parallélisation d’operateurs de TI : multi-cœurs, Cell ou GPU" A. Pédron, F. Laguzet, T. Saidani, P. Courbin, L. Lacassagne, M. Gouiffès,
  2. Technique et Science Informatiques 2005 "Des flottants 16 bits sur microprocesseurs d'usage général pour images et multimédia" D. Etiemble, L. Lacassagne, numéro spécial "Architecture des ordinateurs", 24 n°6/2005
International Conferences and Workshops
  1. DASIP 2016 "Batched Cholesky Factorization for tiny matrices", F. Lemaitre, L. Lacassagne, IEEE International Conference on Design and Architectures for Signal and Image Processing, 2016
  2. PPoPP/WPMVP 2016 "A new SIMD iterative connected component labeling algorithm", L. Lacassagne, L. Cabaret, D. Etiemble, F. Hebache, A. Petreto, ACM International Workshop on Programming Models for SIMD/Vector @ Principles and Practice of Parallel Programming Conference, 2016
  3. ICIP 2015 "Parallel Light Speed Labeling: an efficient connected component labeling algorithm for multi-core processors", L. Cabaret, L. Lacassagne, D. Etiemble, IEEE International Conference on Image Processing, 2015
  4. QCAV 2015 "Interactive ultrasonic field simulation for nondestructive testing", J. Lambert, G. Rougeron, S. Chatillon, L. Lacassagne, IEEE International Conference on Quality Control by Artificial Vision, 2015
  5. SiPS 2014 "What Is the World’s Fastest Connected Component Labeling Algorithm?", L. Cabaret, L. Lacassagne, IEEE International Workshop on Signal Processing Systems, 2014
  6. DASIP 2014 "A Review of World’s Fastest Connected Component Labeling Algorithms: Speed and Energy Estimation", L. Cabaret, L. Lacassagne, L. Oudni, IEEE International Conference on Design and Architectures for Signal and Image Processing, 2014.
  7. QNDE 2014 "Implementation of a GPU Accelerated Total Focusing Reconstruction Method within Civa Software", G. Rougeron, J. Lambert, E. Iakovleva, L. Lacassagne, N. Dominguez, Review of Progress in Quantitative Nondestructive Evaluation, 2014.
  8. PPoPP/WPMVP 2014 "High Level Transforms for SIMD and Low-Level Computer Vision Algorithms", L. Lacassagne, D. Etiemble, A. Dominguez, P. Vezolle, Workshop on programming models for SIMD/Vector processing, ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming 2014. (ACM Link)
  9. PATMOS 2013 "Optimizing High Level Synthesis with High Level Transforms for signal and image processing operators", H. Ye, L. Lacassagne , J. Falcou, D. Etiemble, L. Cabaret and O. Florent, International Workshop on Power and Timing Modeling, Optimization and Simulation, 2013
  10. DASIP 2013 "Real-time covariance tracking algorithm for embedded systems", A. Roméro, L. Lacassagne, A. Hassan Zahraee, M. Gouiffès, L. Lacassagne, IEEE International Conference on Design and Architectures for Signal and Image Processing, 2013
  11. ICIP 2013 "Total Bregman divergence for multiple object tracking", A. Roméro, M. Gouiffès, L. Lacassagne, IEEE International Conference on Image Processing, 2013
  12. Mirage 2013 "Enhanced Local Binary Covariance Matrices (ELBCM) for texture analysis and object tracking", A. Roméro, M. Gouiffès, L. Lacassagne, International Conference on Computer Vision / Computer Graphics Collaboration Techniques and Applications, ACM International Conference Proceedings Series, 2013
  13. QNDE 2013 "A fast ultrasonic simulation tool based on massively parallel implementations", J. Lambert, G. Rougeron, L. Lacassagne, Gilles Rougeron, Sylvain Chatillon, Review of Progress in Quantitative Nondestructive Evaluation,2013
  14. SNA-MC 2013 "High Performance simulation of ultrasonic fields for Non Destructive Testing", J. Lambert, L. Lacassagne, G. Rougeron, S. Le Berre, S. Chatillon, International Symposium in Nuclear Application and Monte-Carlo, 2013
  15. ACCV DTCEP 2012 "Covariance Descriptor Multiple Object Tracking and Re-Identification with Colorspace Evaluation", A. Roméro, M. Gouiffès, L. Lacassagne, IEEE ACCV - Workshop on Detection and Tracking in Challenging Environnements, 2012
  16. DASIP 2012 "Impact of High Level Transforms on High Level Synthesis for motion detection algorithm", H. Ye, L. Lacassagne, D. Etiemble, L. Cabaret, J. Falcou, A. Romero, O. Florent, IEEE International Conference on Design and Architectures for Signal and Image Processing, 2012
  17. DASIP 2012 "Analysis of multicore CPU and GPU toward parallelization of Total Focusing Method ultrasound reconstruction", J. Lambert, A. Pédron, G. Gens, F. Bimbard, L. Lacassagne, E. Iakovleva, S. Le Berre, IEEE International Conference on Design and Architectures for Signal and Image Processing, 2012
  18. ICISP 2012 "Accelerator-based implementation of the Harris algorithm", C. Tadonki, L. Lacassagne, W. Dadi, M. Daoudi, ACM International Conference on Images and Signal Processing ICISP2012
  19. ICPR 2012 "Motion histogram quantification for human action recognition", H. Tabia, M. Gouiffès, L. Lacassagne, IEEE International Conference on Pattern Recognition
  20. ISIVC 2012 "Motion modeling for abnormal event detection in crowd scenes", H. Tabia, M. Gouiffès, L. Lacassagne, IEEE International Conference on Pattern Recognition
  21. GTC 2012: "Optimization Techniques for GPU and GPP", L. Lacassagne, A. Pédron, Nvidia GPU Technology Conference 2012
  22. ICSIPA 2011 "Feature Points tracking adaptative to Saturation", A. Romero, M. Gouiffès, L. Lacassagne, IEEE International Conference on Signal and Image Processing Applications, Best Paper Award
  23. ICSIPA 2011 "Automatic color space switching for robust tracking", F. Laguzet, M. Gouiffès, L. Lacassagne, IEEE International Conference on Signal and Image Processing Applications
  24. DASIP 2011 "Parallelization of an ultrasound reconstruction algorithm for non destructive testing on multicore CPU and GPU", A. Pédron, L. Lacassagne, F. Bimbard, S. Le Berre, IEEE International Conference on Design and Architectures for Signal and Image Processing, 2011, Best Poster Award
  25. DASIP 2011 "A systemC TLM framework for distributed simulation of complex systems with unpredictable communication", J. Peeters, N. Ventroux, T. Sassolas, L. Lacassagne, IEEE International Conference on Design and Architectures for Signal and Image Processing, 2011
  26. Parco 2011 "Performance analysis of an ultrasound reconstruction algorithm for non destructuve testing", A. Pédron, L. Lacassagne, V. Barbillon, F. Bimbard, G. Rougeron, S. Le Berre, IEEE International Conference on Parallel Computing, 2011
  27. BoostCon 2011: "Cell MPI: Mastering the Cell Broadband Engine architecture through a Boost based parallel communication library", J. Falcou, L.Lacassagne, S. Schaetz, Boost Conference
  28. ICIP 2010 "Projection Histogram For Mean-Shift Tracking", M.Gouiffès, F. Laguzet, L. Lacassagne, IEEE International Conference on Image Processing, 2010
  29. ICPR 2010 "Color Connectedness Degree For Mean-Shift Tracking", M.Gouiffès, F. Laguzet, L. Lacassagne, International Conference on Pattern Recognition 2010
  30. HEART 2010 "The Harris algorithm revisited on the Cell processor", C. Tadonki, L. Lacassagne, T. Saïdani, J. Falcou, K. Hamidouche", International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies 2010
  31. ICSIPA 2009 "Video rate image segmentation by means of region splitting and merging", K. Aneja, F. Laguzet, L. Lacassagne, A. Mérigot, IEEE International Conference on Signal and Image Processing Applications
  32. ICIP 2009 "Light Speed Labeling for RISC architectures", L. Lacassagne, B. Zavidovique. IEEE International Conference on Image Processing, 2009, pp. 3245-3248.
  33. ICIP 2009 "Motion Detection: Fast and robust algorithms for embedded systems", L. Lacassagne, A. Manzanera, A. Dupret. IEEE International Conference on Image Processing, 2009, 2009, pp. 3265-3268.
  34. PACT 2009 "Algorithmic skeletons within an Embedded Domain Specific Language for the Cell processor", T. Saidani, C. Tadonki ,L. Lacassagne, J. Falcou, Daniel Etiemble. Conference on Parallel Architectures and Compilation Techniques, 2009, pp. 67-76
  35. PACT MEDEA 2007 "Parallelization Schemes for Memory Optimization on the Cell Processor: A Case Study of Image Processing Algorithm", T. Saidani, S. Piskorski ,L. Lacassagne, S. Bouaziz, Memory performance: Dealing with Applications, systems and architecture, 2007, ACM, pp. 9-16.
  36. ISPA 2007 "Parallelization Strategies for the Points of Interests Algorithm on the Cell Processor", T. Saidani, L. Lacassagne, S. Bouaziz, T. M. Khan, Fifth International Symposium on Parallel and Distributed Processing and Applications, Lecture Notes in Computer Science, (LNCS Springer Link) 2007, vol. 4742, pp. 104-112.
  37. ICIP 2007 "Adaptative multiresoluition for low power CMOS image sensor", A. Verdant, P. Villard, A. Dupret, H. Mathias, L. Lacassagne, IEEE ICIP International Conference on Image Processing, 2007, pp. 185-188.
  38. SITIS 2007"Ultra fast grey scale face detection using vector SIMD programming", O. Vermeulen, A. Manzanera, L. Lacassagne, IEEE Conference on Signal-Image Technologies and Internet-Based System, 2007, pp. 585-592.
  39. ICTIS 2007 "Efficient Altivec customization for embedded systems", T. Saidani, S. Piskorski, L. Lacassagne, S. Bouaziz, IEEE ICTIS Information and Communication Technologies International Symposium, 3-5 avril 2007, Fez, Maroc
  40. ICTIS 2007, "Active Pixel Sensors and Smart Retinas: Test and Evaluation", A. Elouardi, S. Bouaziz, A. Dupret, L. Lacassagne, J.O. Klein, R. Reynaud, IEEE ICTIS Information and Communication Technologies International Symposium, 2007
  41. CAMPS 2006 "Customizing CPU instructions for embedded vision systems", S. Piskorski , L. Lacassagne, S. Bouaziz, D. Etiemble, IEEE CAMPS Computer Architecture, Machine Perception and Sensors, 2006, pp. 59-64.
  42. CAMPS 2006 "Hardware/ software codesign of image processing applications using transaction level modeling", O. cheema, O. Hammami, L. Lacassagne, A. Mérigot, IEEE CAMPS Computer Architecture, Machine Perception and Sensors, 2006, pp. 46-52
  43. CAMPS 2006 "Low power Motion detection with mow spatial and temporal resolution for CMOS image sensor", A. Verdant, A. Dupret, H. Mathias, P. Villard, L. Lacassagne, IEEE CAMPS Computer Architecture, Machine Perception and Sensors, 2006, pp. 12-17
  44. SCAN 2006 "Efficient floating point interval processing for embedded systems and applications", S. Piskorski , L. Lacassagne, M. Kieffer, D. Etiemble, International Symposium of Scientific computing, Computer Arithmetic and Validated Numerics, 2006, pp. 23-26.
  45. TCHA 20006 "Performance evaluation of Altera C2H compiler on image processing benchmarks", D. Etiemble, S. Piskorski, L. Lacassagne, TCHA: Workshop on Tools And Compiler for Hardware Acceleration, 2006.
  46. ISIE 20006 "A smart sensor for image processing: towards a System on Chip", Introducing image processing and SIMD computations with FPGA soft-cores and customized instructions", A. Elouardi, S. Bouaziz, A. Dupret, L.Lacassagne, J.O. Klein, R. Reynaud, International Symposium on Industrial Electronics, 2006, pp 2857-2862.
  47. WRCE 2006 "Introducing image processing and SIMD computations with FPGA soft-cores and customized instructions", D. Etiemble, Lionel Lacassagne, Workshop on Reconfigurable Computing Education, 1er Mars 2006, Karlruhe, Allemagne, 6 pages
  48. Sensact 2005 "A smart sensor for automotive vision applications", A. Elouardi, S. Bouaziz, A. Dupret, L. Lacassagne, J.O. Klein, R. Reynaud, European congres, Sensors & Actuators for advanced Automotive Applications, 2005
  49. Estimedia 2005 "Customizing 16-bit floating point instruction on a NIOS II processor for FPGA image and media processing", D.Etiemble, L.Lacassagne, S. Bouaziz, IEEE 2005, 3rd Workshop on Embedded Systems for Real-Time Multimedia, pp. 61-66
  50. CAMP 2005 "Low Power Image Processing: Analog versus Digital Comparison", J.-O. Klein, L.Lacassagne, H. Mathias, S. Moutault, A. Dupret, IEEE Computer Architecture and Machine Perception, 2005, pp. 111-115.
  51. CAMP 2005 "Implementating Motion Markov Detection on General Purpose Processor and Associative Mesh", J. Denoulet, G.Mostafaoui, L.Lacassagne, A. Mérigot, IEEE Computer Architecture and Machine Perception, 2005, pp. 288-283.
  52. CAMP 2005 "16-bit Floating Point Instructions for embedded Multimedia Applications", L.Lacassagne, D.Etiemble, S. Kablia, IEEE Computer Architecture and Machine Perception, 2005, 198-209.
  53. ICTIS 2005 "A CMOS Retina Based Vision System", A. Elouardi, S. Bouaziz, A. Dupret, *L. Lacassagne,* J.O. Klein, R. Reynaud, IEEE Information and Communication Technologies International Symposium, 2005, pp. 128-134.
  54. ODES 2005 "16-bit floating point operations for low-end and high-end embedded processors", L.Lacassagne, D. Etiemble, 3rd Workshop on Optimisations for DSP and Embedded Systems, 2005.
  55. Sensors 2004 "CMOS Image sensor versus retina Experience", A Elouardi, S Bouaziz, A Dupret, L Lacassagne, JO Klein, R Reynaud, IEEE Sensors 2004
  56. ICPP 2004 "16-bit FP sub-word parallelism to facilitate compiler vectorization and improve performance of image and media processing", D. Etiemble, L. Lacassagne, Internaltional Conference on Parallel Processing, 2004, pp. 540-547
  57. ICTTA 2004 "Fast reliable level-lines segments extraction", N. Suvonvorn, S. Bouchafa, L. Lacassagne, International Conference on Information & Communication Technologies : from Theory to Applications, 2004, pp. 349-350.
  58. ICTTA 2004, "A Fast image segmentation scheme", T. Kunlin, L. Lacassagne, A. Mérigot, International Conference on Information & Communication Technologies : from Theory to Applications, 2004, pp. 351-352.
  59. ISIVC 2004 "Relaxation markovienne et seuillage par hystérésis pour une détection de mouvement temps réel dans des sequences d'images", G. Mostafaoui, T. Kunlin, L. Lacassagne", International Symposium on Image/Video Communications over fixed and mobile networks, 2004.
  60. ICSPAT 2000 "Masked-Motion-JPEG2000: a new reduced-complexity video sequence compression scheme based on a MRF-Motion Detection Algorithm towards inter-frame masking", P. Garda, L. Lacassagne, F. Lohier, Octobre 2000, Dallas USA.
  61. ICPR 2000 "Object image retrieval with image compactness vectors", C. Achard, J. Devars, L. Lacassagne, International Conference on Pattern Recognition, 2000, pp. 4271-4274.
  62. ICIAP 1999 "Motion detection, labeling, data association and tracking in real time on RISC computer", L. Lacassagne, M. Milgram, P. Garda, Septembre à Venise, Italy (this pdf is correct, no that on IEEE site), International Conference on Image Analysis and Processing, 1999, pp. 520-525.
  63. ICSPAT 1999 "A New methodology to optimize DMA data caching: application towards the Real Time Execution of an MRF-based motion detection algorithm on a multi-processor DSP", F. Lohier, L. Lacassagne, P. Garda, IEEE International Conference on Signal Processing Applications and Technology, 1999.
  64. ICASSP 1999 "A generic methodology for the software managing of caches in multi-processors DSP architectures - Application to the real time implementation of low level image processing on the TMS320C80", F. Lohier, L. Lacassagne, P. Garda, IEEE International Conference on Acoustics, Speech and Signal Processing, pp. 1905-1908.
  65. AIHENP 1999 "When will general purpose micro-processors simulate neural networks in real time for HEP applications ?" B. Granado, L. Lacassagne, P. Garda, International Workshop on Software Engineering Artificial Intelligence and Expert Systems, pp. 75-79
  66. IWANN 1999 "Can general purpose micro-processors simulate neural networks in real time ?" B. Granado, L. Lacassagne, P. Garda, Lecture Note in Computer Science (LNCS SpringerLink) n°1607, vol. 2, pp. 21-29.
  67. ICASSP 1998 "Real Time Execution of Optimal Edge Detectors on RISC and DSP Processors",L. Lacassagne, F. Lohier, P. Garda, Mai '98 à Seattle, USA
  68. DSP World 1998 "Porgramming techniques for real time software implementation of optimal edge detectors: a comparison between state of the Art DSP and RISC architectures", F. Lohier, L. Lacassagne, P. Garda
  69. QCAV 1995 "Vers un opérateur d’analyse mouvement / texture" S. Lelandais, J. Berenguer, J. Decourbe, S. Flamme, L. Lacassagne, R. Zarita, International Conference on Quality Control by Artificial Vision, 1995, pp. 238-249
National Conferences and Workshops
  1. RenPar 2013 "Déploiement automatique de code sur une architecture parallèle embarquée", M. Krumpe, Y. Lhuillier, J. Falcou, L. Lacassagne, COmPAS/RenPAR 2013
  2. CORESA 2012 "Reconnaissance des activités humaines à partir des vecteurs de mouvement quantifiés", H. Tabia, M. Gouiffès, L. Lacassagne, CORESA 2012, France
  3. SYMPA 2009 "IPLG: un outils pour la fusion d'opérateurs en Traitement d'Images", S. Piskorski, L. Lacassagne, D. Etiemble, SYMPA 2009, France
  4. GRETSI 2009 "Parallélisation d'opérateurs de TI: multi-coeurs, Cell ou GPU", P. Courbin, A. Pédron, T. Saidani, L. Lacassagne, GRETSI 2009, France. Version longue (6 pages)
  5. SYMPA 2008 "Programmation par squelettes algorithmiques pour le processeur Cell", J. Falcou, T. Saidani, L. Lacassagne, D. Etiemble, SYMPA 2008, France
  6. SYMPA 2006 "Instruction SIMD flottantes 16 bits pour réduire la consommation dans les processeurs embarqués à jeux d'instructions spécialisables", S. Piskorski, L. Lacassagne, D. Etiemble, SYMPA 2006, France
  7. READ 2005 "Evaluation des performances d'un système de vision à base d'un capteur", A. Elouardi, S. Bouaziz, A. Dupret, L. Lacassagne, J.O. Klein, R. reynaud, READ 2005
  8. GRETSI 2003 "Extraction de trajectoires basées sur la cinématique dans les séquences d'images", G. Mostafaoui, C. Achard, M. Milgram, L. Lacassagne, GRETSI 2003, France
  9. AAA 2000 (soon recompilation) "Light Speed Labelling: un nouvel algorithme d'étiquetage en composantes connexes", L. Lacassagne, M. Milgram, J. Devars, Congrès Adéquation Algorithme Architecture, 2000, France
  10. AAA 2000 "Adéquation des micro-processeurs à la simulation en temps réel des réseaux de neurones", L. Gaborit, B. Granafo, L. Lacassagne, P. Garda cture, Congrès Adéquation Algorithme Architecture, 2000, France
  11. GRETSI 1999 "Generic Programming Methods for the real time implementation of a MRF based Motion Detection Algorithm on a multi-processor DSP with multidimensional DMA", F. Lohier, L. Lacassagne, P. Garda, GRETSI 1999, France
  12. GRETSI 1999 "Implémentation temps réel d'algorithme de détection de mouvement par champs de Markov sur RISC et DSP C6x", L. Lacassagne, F. Lohier, M. Milgram, P. Garda; GRETSI 1999, France
  13. AAA 1998 "Execution temps reel des detecteurs de contours de Deriche par des processeurs RISC", T. Ea, L. Lacassagne, P. Garda, Congrès Adéquation Algorithme Architecture, 1998, France
Livre: Méthodes et architectures pour le traitement du signal et des images en temps réel
Traité Information, Commande et Communication. Hermès. D. Demigny coordinateur, novembre 2001 (Lavoisier/Hermes)
L'objectif de cet ouvrage est d'expliciter la démarche qui partant d'un algorithme conduit jusqu'aux différentes structures de réalisations temps réel possibles, qu'elles soient de type programmées ou câblées. On qualifie communément cette étude "d'Adéquation Algorithme Architecture" ou A3. Pour chaque type de structure de réalisation, seront mis en évidence les stratégies algorithmiques, architecturales et technologiques permettant d'augmenter la rapidité de traitement ou de diminuer les coûts. Les architectures abordées sont les processeurs RISC et CISC (Alpha, HP-PA, Pentium, Power-PC, Ultra-Sparc), les DSP (Sharc, C40, C60, C80) les FPGA (avec reconfiguration dynamique), les ASIC et les rétines.
  1. Méthodologie d’optimisation logicielle pour microprocesseurs superscalaires RISC et CISC
    Notre but est de présenter les techniques d’optimisations logicielles afin de programmer le plus efficacement possible les architectures RISC et CISC pour effectuer le traitement d’images en temps réel. Lorsqu’il n’y a pas de contraintes d’embarquabilité, ces processeurs sont capables d’atteindre la cadence de traitement temps réel. Dans un premier temps nous présentons rapidement l’architectures des processeurs RISC. Puis nous détaillons deux types d’optimisations : l’optimisation des traitements et l’optimisations des accès mémoire. Enfin nous appliquons ces optimisations au cas particuliers des filtres récursifs de détection de contours, sur des processeurs représentatifs de l’état de l’art. Un benchmark permet d’observer le comportement de ces processeurs pour différentes tailles d’images et pour différentes combinaisons d’optimisations. Enfin l’utilisations des jeux d’instructions multimédia est présentée comme perspective dans le cadre du traitement d’images bas niveau.
  2. Méthodologie d’optimisation logicielle pour processeurs VLIW - exemple du DSP C62
    L'intérêt de cette étude est lié à l'émergence des architectures VLIW (Very Long Instruction Word) Ce type d'architecture peut être vu comme l'évolution logique des processeurs RISC superscalaires, où les unités de calcul se sont spécialisées et leur nombre a augmenté. Ces architectures sont très prometteuses, car elles sont très souples dans leur mode de fonctionnement, puisque contrairement aux architectures SIMD (Single Instruction Multiple Data), toutes les unités de calcul n'effectuent pas la même instruction. Cela permet de ne pas se limiter aux algorithmes dits de bas niveau en traitement d'image, mais aussi de viser les algorithmes de moyen niveau où les architectures SIMD sont souvent inefficaces. S'il est relativement simple d'atteindre la puissance crête avec une architecture SIMD, cela est bien plus difficile dans le cas des processeurs VLIW, car il est nécessaire d'utiliser, à chaque cycle, un maximum d'unités de calcul. Notre but est de décrire et d'implémenter les méthodologies d'optimisation logicielle qui sont propres à ce type particulier d'architecture, afin d'en tirer la quintessence et d'obtenir en logiciel des cadences de traitement d'image encore inaccessibles sur processeur RISC (par exemple le 1024x1024 en temps réel). Ce type d'architecture se retrouve soit dans des processeurs spécialisés type DSP (Digital Signal Processor), comme le C62 de Texas Instrument, ou le Trimedia de Phillips, soit dans des processeurs généralistes comme le projet VLIW d'IBM, le Majc de Sun ou le tant attendu Merced/Itanium d'Intel. Réussir à optimiser l'exécution d'un programme sur une architecture VLIW est donc plus que d'actualité. Enfin nous donnons un rapide aperçu de l'architecture du C62, puis nous décrivons les optimisations logicielles qui sont propres à ces architectures. Nous détaillons l'application de ces optimisations au cas du filtrage récursif et nous montrons que ce ne sont pas forcément les optimisations les plus efficaces pour les RISC qui sont les plus efficaces pour les VLIW. Enfin nous testerons les différents outils et langages, nous comparerons les résultats aux limites théoriques atteignables par le DSP et nous conclurons sur les possibilités d'atteindre la puissance crête sur C62.
  3. Implantation sur DSP multiprocesseurs SIMD à mémoire partagée - exemple du C80
    Ce chapitre est consacré aux implantations en temps réel de l'algorithme sur un DSP multiprocesseurs à mémoire partagée : le TMS320C80. Une méthodologie originale de programmation pour ce type de processeurs est décrite. Elle permet la génération automatique de requêtes DMA. Elle a permis le développement d'une bibliothèque de traitement d'images et elle a conduit à des implantations temps réel de Deriche sur le DSP C80. Les différents paramètres influant sur la rapidité de traitement sont mis en évidence et un comparatif des performances est présenté.
Seminars
  1. Canum 2010, Mini-symposium CANUM 2010 "Modélisation et calcul scientifique : les enjeux en génération d’images". Parallélisation d’opérateurs de TI : multi-coeurs, Cell ou GPU
Publications - algorithms, image processing and computer vision
International journal:
  1. JRTIP Journal of Real Time Image Processing "Color tracking with contextual switching: Real-time implementation on CPU" F. Laguzet, A. Roméro, M. Gouiffès, L. Lacassagne, D. Etiemble, 2013 (Springer Link).
  2. JRTIP Journal of Real Time Image Processing 2010 "Light Speed Labeling: Efficient Connected Component Labeling on RISC Architectures" L. Lacassagne, B. Zavidovique (SpringerLink), 2010.
International Conferences:
  1. ICIP 2012 "Total Bregman divergence for multiple object tracking", A. Roméro, M. Gouiffès, L. Lacassagne, IEEE International Conference on Image Processing, 2010
  2. Mirage 2013 " Enhanced Local Binary Covariance Matrices (ELBCM) for texture analysis and object tracking", A. Roméro, M. Gouiffès, L. Lacassagne, International Conference on Computer Vision / Computer Graphics Collaboration Techniques and Applications, ACM International Conference Proceedings Series, 2013
  3. ACCV DTCEP 2012 "Covariance Descriptor Multiple Object Tracking and Re-Identification with Colorspace Evaluation", A. Roméro, M. Gouiffès, L. Lacassagne, IEEE ACCV - Workshop on Detection and Tracking in Challenging Environnements, 2012
  4. ICPR 2012 "Motion histogram quantification for human action recognition", H. Tabia, M. Gouiffès, L. Lacassagne, IEEE International Conference on Pattern Recognition
  5. ISIVC 2012 "Motion modeling for abnormal event detection in crowd scenes", H. Tabia, M. Gouiffès, L. Lacassagne, IEEE International Conference on Pattern Recognition
  6. ICSIPA 2011 "Feature Points tracking adaptative to Saturation", A. Romero, M. Gouiffès, L. Lacassagne, IEEE International Conference on Signal and Image Processing Applications, Best Paper Award
  7. ICSIPA 2011 "Automatic color space switching for robust tracking", F. Laguzet, M. Gouiffès, L. Lacassagne, IEEE International Conference on Signal and Image Processing Applications
  8. ICIP 2010 "Projection Histogram For Mean-Shift Tracking", M.Gouiffès, F. Laguzet, L. Lacassagne, IEEE International Conference on Image Processing, 2010
  9. ICPR 2010 "Color Connectedness Degree For Mean-Shift Tracking", M.Gouiffès, F. Laguzet, L. Lacassagne, International Conference on Pattern Recognition 2010
  10. ICSIPA 2009 "Video rate image segmentation by means of region splitting and merging", K. Aneja, F. Laguzet, L. Lacassagne, A. Mérigot, IEEE International Conference on Signal and Image Processing Applications
  11. ICIP 2009 "Light Speed Labeling for RISC architectures", L. Lacassagne, B. Zavidovique. IEEE International Conference on Image Processing, 2009, pp. 3245-3248.
  12. ICIP 2009 "Motion Detection: Fast and robust algorithms for embedded systems", L. Lacassagne, A. Manzanera, A. Dupret. IEEE International Conference on Image Processing, 2009, 2009, pp. 3265-3268.
  13. ICIP 2007 "Adaptative multiresoluition for low power CMOS image sensor", A. Verdant, P. Villard, A. Dupret, H. Mathias, L. Lacassagne, IEEE ICIP International Conference on Image Processing, 2007, pp. 185-188.
  14. ICTTA 2004 "Fast reliable level-lines segments extraction", N. Suvonvorn, S. Bouchafa, L. Lacassagne, International Conference on Information & Communication Technologies : from Theory to Applications, 2004, pp. 349-350.
  15. ICTTA 2004 "A Fast image segmentation scheme", T. Kunlin, L. Lacassagne, A. Mérigot, International Conference on Information & Communication Technologies : from Theory to Applications, 2004, pp. 351-352.
  16. ISIVC 2004 "Relaxation markovienne et seuillage par hystérésis pour une détection de mouvement temps réel dans des sequences d'images", G. Mostafaoui, T. Kunlin, L. Lacassagne", International Symposium on Image/Video Communications over fixed and mobile networks, 2004.
  17. ICSPAT 2000 "Masked-Motion-JPEG2000: a new reduced-complexity video sequence compression scheme based on a MRF-Motion Detection Algorithm towards inter-frame masking", P. Garda, L. Lacassagne, F. Lohier, Octobre 2000, Dallas USA.
  18. ICPR 2000 "Object image retrieval with image compactness vectors", C. Achard, J. Devars, L. Lacassagne, International Conference on Pattern Recognition, 2000, pp 4271-4274.
  19. ICIAP 1999 "Motion detection, labeling, data association and tracking in real time on RISC computer", L. Lacassagne, M. Milgram, P. Garda, Septembre à Venise, Italy (this pdf is correct, no that on IEEE site), International Conference on Image Analysis and Processing, 1999, pp. 520-525.
  20. QCAV 1995 "Vers un opérateur d’analyse mouvement / texture" S. Lelandais, J. Berenguer, J. Decourbe, S. Flamme, L. Lacassagne, R. Zarita, International Conference on Quality Control by Artificial Vision, 1995, pp. 238-249
National Conference
  1. CORESA 2012 "Reconnaissance des activités humaines à partir des vecteurs de mouvement quantifiés", H. Tabia, M. Gouiffès, L. Lacassagne, CORESA 2012, France
  2. GRETSI 2003 "Extraction de trajectoires basées sur la cinématique dans les séquences d'images", G. Mostafaoui, C. Achard, M. Milgram, L. Lacassagne, GRETSI 2003, France
  3. AAA 2000 (soon recompilation) "Light Speed Labelling: un nouvel algorithme d'étiquetage en composantes connexes", L. Lacassagne, M. Milgram, J. Devars, Congrès Adéquation Algorithme Architecture, 2000, France
Publications - architecture optimization & benchmarking
International journals:
  1. Eurasip Journal on Advances in Signal Processing "Covariance tracking: architecture optimizations for embedded systems" A. Roméro, L. Lacassagne, M. Gouiffès, A. Hassan Zahraee, 2014 (Eurasip Open Access ink).
  2. JRTIP Journal of Real Time Image Processing 2008 "High Performance Motion Detection: Some trends toward new embedded architectures for vision systems" L. Lacassagne, A. Manzanera, J. Denoulet, A. Mérigot.(SpringerLink)
  3. International Journal of Computer Sciences and Application 2008 " A Smart Architecture for Low-Level Image Computing" A. Elouardi, S. Bouaziz, A. Dupret, L. Lacassagne, J.O. Klein and R. Reynaud. Vol 5, issue 3a, Special Issue : New trends in Information and Communicatoin Technologies Applications. pp.1-19. 2008.
  4. MST 2007 IOP Measurement Science and Technology: "Time comparison in image processing: APS sensors versus an artificial retina based vision system", A Elouardi, S Bouaziz, A Dupret, L Lacassagne, J O Klein and R Reynaud
  5. Journal of Applied Physics "A smart sensor based vision system: implementation and evaluation" A. Elouardi, S. Bouaziz, A. Dupret, L. Lacassagne, J.O. Klein, R. Reynaud. Vol. 39, pp1694-1705. 2006.

  6. IEEE Transcations on Instrumentation and Measurement "Image Processing Vision Systems: Standard Image Sensors Versus Retinas" A. Elouardi, S. Bouaziz, A. Dupret, L. Lacassagne, J.O. Klein, R. Reynaud IEEE Transactions on Instrumentation and Measurement, vol. 56, no 4, august 2007
  7. Multimedia Systems Design Magazine 1998 "A DSP implementation of optimal edge detectors" F. Lohier, L. Lacassagne, P. Garda.
National journals:
  1. Traitement du Signal 2010: "Parallélisation d’operateurs de TI : multi-cœurs, Cell ou GPU" A. Pédron, F. Laguzet, T. Saidani, P. Courbin, L. Lacassagne, M. Gouiffès,
International Conferences:
  1. SiPS 2014 "What Is the World’s Fastest Connected Component Labeling Algorithm?", L. Cabaret, L. Lacassagne, IEEE International Workshop on Signal Processing Systems, 2014
  2. DASIP 2014 "A Review of World’s Fastest Connected Component Labeling Algorithms: Speed and Energy Estimation", L. Cabaret, L. Lacassagne, L. Oudni, IEEE International Conference on Design and Architectures for Signal and Image Processing, 2014.
  3. QNDE 2014 "Implementation of a GPU Accelerated Total Focusing Reconstruction Method within Civa Software", G. Rougeron, J. Lambert, E. Iakovleva, L. Lacassagne, N. Dominguez, Review of Progress in Quantitative Nondestructive Evaluation, 2014.
  4. WPMVP 2014 "High Level Transforms for SIMD and Low-Level Computer Vision Algorithms", L. Lacassagne, D. Etiemble, A. Dominguez, P. Vezolle, Workshop on programming models for SIMD/Vector processing, ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming 2014. (ACM Link)
  5. PATMOS 2013 "Optimizing High Level Synthesis with High Level Transforms for signal and image processing operators", H. Ye, L. Lacassagne , J. Falcou, D. Etiemble, L. Cabaret and O. Florent, International Workshop on Power and Timing Modeling, Optimization and Simulation, 2013
  6. DASIP 2013 "Real-time covariance tracking algorithm for embedded systems", A. Roméro, L. Lacassagne, A. Hassan Zahraee, M. Gouiffès, L. Lacassagne, IEEE International Conference on Design and Architectures for Signal and Image Processing, 2013
  7. QNDE 2013 "A fast ultrasonic simulation tool based on massively parallel implementations", J. Lambert, G. Rougeron, L. Lacassagne, Gilles Rougeron, Sylvain Chatillon, Review of Progress in Quantitative Nondestructive Evaluation,2013
  8. SNA-MC 2013 "High Performance simulation of ultrasonic fields for Non Destructive Testing", J. Lambert, L. Lacassagne, G. Rougeron, S. Le Berre, S. Chatillon, International Symposium in Nuclear Application and Monte-Carlo, 2013
  9. ICISP 2012 "Accelerator-based implementation of the Harris algorithm", C. Tadonki, L. Lacassagne, W. Dadi, M. Daoudi, ACM International Conference on Images and Signal Processing ICISP2012
  10. DASIP 2012 "Analysis of multicore CPU and GPU toward parallelization of Total Focusing Method ultrasound reconstruction", J. Lambert, A. Pédron, G. Gens, F. Bimbard, L. Lacassagne, E. Iakovleva, S. Le Berre, IEEE International Conference on Design and Architectures for Signal and Image Processing, 2012, (accepted)
  11. GTC 2012: "Optimization Techniques for GPU and GPP", L. Lacassagne, A. Pédron, Nvidia GPU Technology Conference 2012
  12. DASIP 2011 "Parallelization of an ultrasound reconstruction algorithm for non destructive testing on multicore CPU and GPU", A. Pédron, L. Lacassagne, F. Bimbard, S. Le Berre, IEEE International Conference on Design and Architectures for Signal and Image Processing, 2011, Best Poster Award
  13. DASIP 2011 "A systemC TLM framework for distributed simulation of complex systems with unpredictable communication", J. Peeters, N. Ventroux, T. Sassolas, L. Lacassagne, IEEE International Conference on Design and Architectures for Signal and Image Processing, 2011
  14. Parco 2011 "Performance analysis of an ultrasound reconstruction algorithm for non destructuve testing", A. Pédron, L. Lacassagne, V. Barbillon, F. Bimbard, G. Rougeron, S. Le Berre, IEEE International Conference on Parallel Computing, 2011
  15. HEART 2010 "The Harris algorithm revisited on the Cell processor", C. Tadonki, L. Lacassagne, T. Saïdani, J. Falcou, K. Hamidouche", International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies 2010
  16. PACT MEDEA 2007 "Parallelization Schemes for Memory Optimization on the Cell Processor: A Case Study of Image Processing Algorithm", T. Saidani, S. Piskorski ,L. Lacassagne, S. Bouaziz, Memory performance: Dealing with Applications, systems and architecture, 2007, ACM, pp. 9-16.
  17. ISPA 2007 "Parallelization Strategies for the Points of Interests Algorithm on the Cell Processor", T. Saidani, L. Lacassagne, S. Bouaziz, T. M. Khan, Fifth International Symposium on Parallel and Distributed Processing and Applications, Lecture Notes in Computer Science, (LNCS SpringerLink) 2007, vol. 4742, pp. 104-112.
  18. SITIS 2007"Ultra fast grey scale face detection using vector SIMD programming", O. Vermeulen, A. Manzanera, L. Lacassagne, IEEE Conference on Signal-Image Technologies and Internet-Based System, 2007, pp. 585-592.
  19. ISIE 20006 "A smart sensor for image processing: towards a System on Chip", Introducing image processing and SIMD computations with FPGA soft-cores and customized instructions", A. Elouardi, S. Bouaziz, A. Dupret, L.Lacassagne, J.O. Klein, R. Reynaud, International Symposium on Industrial Electronics, 2006, pp 2857-2862.
  20. Sensact 2005 "A smart sensor for automotive vision applications", A. Elouardi, S. Bouaziz, A. Dupret, L. Lacassagne, J.O. Klein, R. Reynaud, European congres, Sensors & Actuators for advanced Automotive Applications, 2005
  21. CAMP 2005 "Low Power Image Processing: Analog versus Digital Comparison", J.-O. Klein, L.Lacassagne, H. Mathias, S. Moutault, A. Dupret, IEEE Computer Architecture and Machine Perception, 2005, pp. 111-115.
  22. CAMP 2005 "Implementating Motion Markov Detection on General Purpose Processor and Associative Mesh", J. Denoulet, G.Mostafaoui, L.Lacassagne, A. Mérigot, IEEE Computer Architecture and Machine Perception, 2005, pp. 288-283.
  23. ICTIS 2005 "A CMOS Retina Based Vision System", A. Elouardi, S. Bouaziz, A. Dupret, L. Lacassagne, J.O. Klein, R. Reynaud, IEEE Information and Communication Technologies International Symposium, 2005, pp. 128-134.
  24. Sensors 2004 "CMOS Image sensor versus retina Experience", A Elouardi, S Bouaziz, A Dupret, L Lacassagne, JO Klein, R Reynaud, IEEE Sensors 2004
  25. AIHENP 1999 "When will general purpose micro-processors simulate neural networks in real time for HEP applications ?" B. Granado, L. Lacassagne, P. Garda, International Workshop on Software Engineering Artificial Intelligence and Expert Systems, pp. 75-79
  26. IWANN 1999 "Can general purpose micro-processors simulate neural networks in real time ?" B. Granado, L. Lacassagne, P. Garda, Lecture Note in Computer Science (LNCS SpringerLink) n°1607, vol. 2, pp. 21-29.
  27. ICASSP 1998 "Real Time Execution of Optimal Edge Detectors on RISC and DSP Processors",L. Lacassagne, F. Lohier, P. Garda, Mai '98 à Seattle, USA
  28. DSP World 1998 "Porgramming techniques for real time software implementation of optimal edge detectors: a comparison between state of the Art DSP and RISC architectures", F. Lohier, L. Lacassagne, P. Garda
National Conference
  1. GRETSI 2009 "Parallélisation d'opérateurs de TI: multi-coeurs, Cell ou GPU", P. Courbin, A. Pédron, T. Saidani, L. Lacassagne, GRETSI 2009, France. Version longue (6 pages)
  2. READ 2005 "Evaluation des performances d'un système de vision à base d'un capteur", A. Elouardi, S. Bouaziz, A. Dupret, L. Lacassagne, J.O. Klein, R. reynaud, READ 2005
  3. AAA 2000 "Adéquation des micro-processeurs à la simulation en temps réel des réseaux de neurones", L. Gaborit, B. Granafo, L. Lacassagne, P. Garda cture, Congrès Adéquation Algorithme Architecture, 2000, France
  4. GRETSI 1999 "Implémentation temps réel d'algorithme de détection de mouvement par champs de Markov sur RISC et DSP C6x", L. Lacassagne, F. Lohier, M. Milgram, P. Garda; GRETSI 1999, France
  5. AAA 1998 "Execution temps reel des detecteurs de contours de Deriche par des processeurs RISC", T. Ea, L. Lacassagne, P. Garda, Congrès Adéquation Algorithme Architecture, 1998, France
Publications - processor customization
International journals:
  1. International Journal of Computer Sciences and Application 2008 "Altivec Vector Unit Customization for embedded Systems". T. Saidani, J. Falcou, L. Lacassagne, S. Bouaziz. Vol 5, issue 3a, Special Issue : New trends in Information and Communicatoin Technologies Applications. pp.20-32. 2008.
  2. International Journal on Information and Communication Technologies "A Statistical Approach for High Speed Long Word Addition". S. Bouaziz, B. Larnaudie, E. Elouardi, L. Lacassagne 2008.
  3. EURASIP 2007 EURASIP Journal on Embedded Systems "System-Platforms-Based SystemC TLM Design of Image Processing Chains for Embedded Applications", Muhammad Omer Cheema, Lionel Lacassagne, and Omar Hammami, Volume 2007 (2007), Article ID 71043, 14 pages.

National journal:
  1. Technique et Science Informatiques 2005: "Des flottants 16 bits sur microprocesseurs d'usage général pour images et multimédia" D. Etiemble, L. Lacassagne, numéro spécial "Architecture des ordinateurs", 24 n°6/2005
International conferences:
  1. DASIP 2012 "Impact of High Level Transforms on High Level Synthesis for motion detection algorithm", H. Ye, L. Lacassagne, D. Etiemble, L. Cabaret, J. Falcou, A. Romero, O. Florent, IEEE International Conference on Design and Architectures for Signal and Image Processing, 2012, (accepted)
  2. ICTIS 2007 "Efficient Altivec customization for embedded systems", T. Saidani, S. Piskorski, L. Lacassagne, S. Bouaziz, IEEE ICTIS Information and Communication Technologies International Symposium, 3-5 avril 2007, Fez, Maroc
  3. ICTIS 2007, "Active Pixel Sensors and Smart Retinas: Test and Evaluation", A. Elouardi, S. Bouaziz, A. Dupret, L. Lacassagne, J.O. Klein, R. Reynaud, IEEE ICTIS Information and Communication Technologies International Symposium, 2007
  4. CAMPS 2006 "Customizing CPU instructions for embedded vision systems", S. Piskorski , L. Lacassagne, S. Bouaziz, D. Etiemble, IEEE CAMPS Computer Architecture, Machine Perception and Sensors, 2006, pp. 59-64.
  5. CAMPS 2006 "Hardware/ software codesign of image processing applications using transaction level modeling", O. cheema, O. Hammami, L. Lacassagne, A. Mérigot, IEEE CAMPS Computer Architecture, Machine Perception and Sensors, 2006, pp. 46-52
  6. CAMPS 2006 "Low power Motion detection with mow spatial and temporal resolution for CMOS image sensor", A. Verdant, A. Dupret, H. Mathias, P. Villard, L. Lacassagne, IEEE CAMPS Computer Architecture, Machine Perception and Sensors, 2006, pp. 12-17
  7. SCAN 2006 "Efficient floating point interval processing for embedded systems and applications", S. Piskorski , L. Lacassagne, M. Kieffer, D. Etiemble, International Symposium of Scientific computing, Computer Arithmetic and Validated Numerics, 2006, pp. 23-26.
  8. TCHA 20006 "Performance evaluation of Altera C2H compiler on image processing benchmarks", D. Etiemble, S. Piskorski, L. Lacassagne, TCHA: Workshop on Tools And Compiler for Hardware Acceleration, 2006.
  9. WRCE 2006 "Introducing image processing and SIMD computations with FPGA soft-cores and customized instructions", D. Etiemble, Lionel Lacassagne, Workshop on Reconfigurable Computing Education, 1er Mars 2006, Karlruhe, Allemagne, 6 pages
  10. Estimedia 2005 "Customizing 16-bit floating point instruction on a NIOS II processor for FPGA image and media processing", D.Etiemble, L.Lacassagne, S. Bouaziz, IEEE 2005, 3rd Workshop on Embedded Systems for Real-Time Multimedia, pp. 61-66
  11. CAMP 2005 "16-bit Floating Point Instructions for embedded Multimedia Applications", L.Lacassagne, D.Etiemble, S. Kablia, IEEE Computer Architecture and Machine Perception, 2005, 198-209.
  12. ODES 2005 "16-bit floating point operations for low-end and high-end embedded processors", L.Lacassagne, D. Etiemble, 3rd Workshop on Optimisations for DSP and Embedded Systems, 2005.
  13. ICPP 2004 "16-bit FP sub-word parallelism to facilitate compiler vectorization and improve performance of image and media processing", D. Etiemble, L. Lacassagne, Internaltional Conference on Parallel Processing, 2004, pp. 540-547
National Conference
  1. SYMPA 2006 "Instruction SIMD flottantes 16 bits pour réduire la consommation dans les processeurs embarqués à jeux d'instructions spécialisables", S. Piskorski, L. Lacassagne, D. Etiemble, SYMPA 2006, France
Publications - Tools
International Journal
  1. HiPEAC: Transactions on High-Performance Embedded Architectures and Compilers 2008 "Parallelization Schemes for Memory Optimization on the Cell Processor : A Case Study on the Harris Corner Detector" T. Saidani, L. Lacassagne, J. Falcou, C. Tadonki, S. Bouaziz.
International Conference
  1. PATMOS 2013 "Optimizing High Level Synthesis with High Level Transforms for signal and image processing operators", H. Ye, L. Lacassagne , J. Falcou, D. Etiemble, L. Cabaret 2 and O. Florent, International Workshop on Power and Timing Modeling, Optimization and Simulation, 2013
  2. DASIP 2012 "Impact of High Level Transforms on High Level Synthesis for motion detection algorithm", H. Ye, L. Lacassagne, D. Etiemble, L. Cabaret, J. Falcou, A. Romero, O. Florent, IEEE International Conference on Design and Architectures for Signal and Image Processing, 2012
  3. BoostCon 2011 "Cell MPI: Mastering the Cell Broadband Engine architecture through a Boost based parallel communication library", J. Falcou, L.Lacassagne, S. Schaetz, Boost Conference
  4. PACT 2009 "Algorithmic skeletons within an Embedded Domain Specific Language for the Cell processor", T. Saidani, C. Tadonki ,L. Lacassagne, J. Falcou, Daniel Etiemble. Conference on Parallel Architectures and Compilation Techniques, 2009, pp. 67-76
  5. ICSPAT 1999 "A New methodology to optimize DMA data caching: application towards the Real Time Execution of an MRF-based motion detection algorithm on a multi-processor DSP", F. Lohier, L. Lacassagne, P. Garda, IEEE International Conference on Signal Processing Applications and Technology, 1999.
  6. ICASSP 1999 "A generic methodology for the software managing of caches in multi-processors DSP architectures - Application to the real time implementation of low level image processing on the TMS320C80", F. Lohier, L. Lacassagne, P. Garda, IEEE International Conference on Acoustics, Speech and Signal Processing, pp. 1905-1908.
National Conference
  1. RenPar 2013 "Déploiement automatique de code sur une architecture parallèle embarquée", M. Krumpe, Y. Lhuillier, J. Falcou, L. Lacassagne, COmPAS/RenPAR 2013
  2. SYMPA 2009 "IPLG: un outils pour la fusion d'opérateurs en Traitement d'Images", S. Piskorski, L. Lacassagne, D. Etiemble, SYMPA 2009, France
  3. SYMPA 2008 "Programmation par squelettes algorithmiques pour le processeur Cell", J. Falcou, T. Saidani, L. Lacassagne, D. Etiemble, SYMPA 2008, France
  4. GRETSI 1999 "Generic Programming Methods for the real time implementation of a MRF based Motion Detection Algorithm on a multi-processor DSP with multidimensional DMA", F. Lohier, L. Lacassagne, P. Garda, GRETSI 1999, France