To explore the contribution of such technologies, including the integration of non-volatile MRAM technology (Magnetoresistive Random Access Memory)
Identifying and quantifying the levels and systems architecture benefits especially in terms of reliability, energy consumption and performance.
MRAM technology offers very interesting performances for non-volatile memory: access time (order of several nanoseconds), four times the density of SRAM, robustness against SEU (Single Event Upset), energy, endurance ... etc. To facilitate the use of this technology, it is necessary to identify and quantify the benefits that we may get in a context of critical embedded applications, particularly in the field of aeronautics and space. For instance, the robustness of this technology considering SEU is probably an important way of development for this technology. However it is clear that efforts in this project can be adapted to wider application areas.
Our efforts will be on the suitability of this technology based on embedded processors architectures with a focus on two aspects:
The core of the processor and associated memory hierarchy. Regarding the processor core it is clear that innovative solutions will emerge from the technological advances of MRAM, either at the architectural level or logic level while optimizing Reliability / Energy / Performance.
To the memory hierarchy that extends from the registers to the mass memory through the cache, the non-volatility and intrinsic qualities of MRAM will allow to propose new paradigms of storage access within a processor or system in general.
The main novelty of this project is to focus architecture level, at the interface between advanced technology providing a new and profound review on the design of microelectronic embedded systems incoming from the MRAM technology.
IEF & LRI jobs: to evaluate the impact of MRAM on cache (memory architecture) performance and the impact of coding (software optimizations) of general purpose codes (security, CRC), and domain specific codes (image processing) on power consumption
MARS is a project from Agence National pour la Recherche: ANR
SPY goal is to design and evaluate a new autonomous architecture for intelligent video-surveillance for still and mobile systems. SPY will emphasize on better use of wireless network, and mobiles sensors (mike and CCTV camera) to help policemen and firemen to accompish their duty. SPY project will implement advanced algorithms to provide an autonomous support to assist decision making at the tactical level.
The project OPARUS "Optimization and Parallelization for Analysis and Reconstruction of ultrasonic NDT" focuses on the development of modelling tools and treatment for reconstruction of multi-element ultrasonic non destructive testing data. The objective of the project is to optimize the performance of numerical algorithms and to extend significantly the actual limitations on the use of accurate models for visualization, analysis and diagnostic and provide tools for innovative modelling in agreement with the industrial constraints. The kinds of technology pointed are clearly oriented on multi-core processors and GPGPU, all included in single "workstation". The technological barriers concerns both the capacity to exploit the new parallel architectures and to implement optimized algorithms dedicated to the reconstruction of data for analysis. The developments are focused on applications representative of industrial cases. The reconstruction tools based on these developments will be integrated into three systems and software: the M2M acquisition systems, CIVA platform of simulation and analysis and the analysis production software NDT-kit. OPARUS is a 3 years industrial research project which includes industrial end users of NDT (EADS and EDF), high-tech companies, (M2M, which develops multi-elements systems and CAPS-Enterprise, expert in parallel computing solutions), CEA LIST developing the CIVA software platform, and EFI, university laboratories specialist of parallel architectures, image processing and complex systems. Project results will be directly integrated in systems and software already operating in industrial environments. From a scientific point of view results will be communicated through journals and conferences dedicated to non destructive testing, and in journals for research in computer science and architecture.
our job: to develop tools to help user to optimize deployment of large applications over the Teraops parallel plateform. Tools should tackle combined problems of data flow parallelization and Control Flow Parallelization. We are working on low level image processing algorithms (typically convolution kernel) optimization and also intermediate/medium level image processing algorithms (connected component labeling, hysteresis threshold, 2D convex Hull, ...) that are data dependant.
Teraops is a project from Pôle de Competitivite Systematic
Funding: 3568 k€
Tools developpement for Cell processor [2006..2008]
objective: to develop tools for automatic parallelisation of vision and multimedia applications on one or more Cell processors
our job: to create deployment tools for image processing and computer vision algorithms for Cell, but also for GPU stream computing. Tools target current high end architectures (multi-core pulti-processors architectures, Cell processors, GPU - Nvidia and ATI). It and should be also flexible for next generation of architectures, like TILE64 from Tilera or Larabee/Polaris from Intel Terascale project.
OCelle is a project from Agence National pour la Recherche: ANR
objective: to develop image processing algorithm for visible and infra-red 360° impage processing, to develop robust fusion algorithms and to optimize codes for realtime implementation
our job: to develop robust data fusion and supervision/monitoring algorithm, and also to port selected algorithms on multi-core multi-processors (multi-threaded approach), but also GPU and Cell, if possible
Safearound is a project from Pôle de Compétitivité Systematic