Execution scheme in Mips

In the course unit 4I100, one of the goals is to understand the pipelined arechitecture of the Mips processor (and some variants) throughout execution examples of assembly code inside the pipeline. For this, one must represent on a simplified scheme the execution of the instruction cycle by cycle through the pipeline. This page implements the execution scheme for a given code (note: the parser is very simplified).

Architectural parameters

• Length of pipeline stages: IFC : 1 2 3 DEC : 1 2 3 EXE : 1 2 3 MEM : 1 2 3
• Bypass to MEM stage: No Yes
• Stage for computing next instruction address: DEC EXE

Code

_strupper_loop: Lb r8, 0(r4) ; lire src[i] Slt r9, r8, r11 ; src[i] < 'a' Slt r10, r12, r8 ; 'z' < src[i] Or r10, r10, r9 ; et des 2 conditions Bne r10, r0, _strupper_endif ; si 1 des 2 cond vraie Nop Addiu r8, r8, 'A'-'a'; transformer en majuscule Sb r8, 0(r4) _strupper_endif: Addiu r4, r4, 1 ; caractère suivant Bne r8, r0, _strupper_loop Nop

Branches taken

•  Branch 1 taken
•  Branch 2 taken
•  Branch 3 taken

    (subsequent branches will not be taken)

See execution