The team addresses the problem of hardware security by proposing hardware solutions and associated CAD tools and methodologies. Specifically, we are focusing on the following aspects:
- Development of a design methodology for prototyping efficiently and rapidly digital cryptographic algorithms on hardware, taking into account several metrics, such as frequency, area, etc. This methodology is based on a large library of cryptographic basic blocks. Specifically, using this methodology, we proposed a hardware implementation of AEGIS which participates in the CAESAR competition organized by the NIST. We also proposed several implementations of Authenticated Encryption and Elliptic Curve Cryptography depending on throughput, frequency, and area constraints ;
- Side-channel attacks to measure the vulnerability of our architectures or propose verification solutions aiming at establishing efficient countermeasures ;
- Development of a secure FPGA using WDDL logic and the associated design flow, including a simulator-based power analyzer ;
- Development of a portfolio of obfuscation methodologies for equipping analog ICs with a capability that prevents reverse engineering and counterfeiting ;
- Development of spectrum sensing Radio Frequency (RF) circuits that are used to sweep the spectrum and detect malicious RF attacks.
Integrated Systems Dependability
The team’s research activities on dependable circuits and systems include:
- Development of innovative algorithms for fully synchronizing a distributed generation of clocks into large SoCs ;
- Analysis of aging and electromigration phenomena towards design-for-reliability ;
- Diagnosis and failure analysis of mixed analog-digital SoCs towards improving the manufacturing process and boosting yield, facilitating silicon debugging, and identifying the root cause of failures occurring in the field of operation so as to improve safety features in future product generations ;
- Design-for-test and built-in self-test for mixed-signal circuits with the objective of reducing manufacturing test costs and improving outgoing quality ;
- Reusing the existing built-in self-test infrastructure in the field of operation, especially in the context of safety-critical and mission-critical applications, with the aim to perform on-line tests in idle times or concurrently with the operation ;
- Self-calibration and self-healing for mixed-signal circuits and systems aiming at recovering yield loss in post-manufacturing and at achieving fault tolerance and adaptation to the environment in the field of operation.
Design and CAD tools for heterogenous systems
The team’s research activities on Design and CAD tools for heterogenous systems include:
- Designer-centric analog circuit synthesis flow. This CAD flow is fully controlled by the designer and offers an intuitive design approach. It captures the designer knowledge to automatically generate the analog IP design procedure and physical view, ensuring consistency and accuracy. Using both simulation-based and knowledge-based approaches, and addressing both sizing and layout generation, the flow has successfully been used to synthesize transconductors and state of the art analog to digital converters (ADCs) ;
- Low-power RF IPs. Based on its strong experience in the domains of sigma-delta modulation and RF ICs, CIAN has developed an innovative design methodology dedicated to the implementation of state-of-the-art low-power multi-standard RF transceivers capable of dynamically detecting and communicating with surrounding wireless sensors, using the most appropriate communication standard. This requires to specify with great care the RF transceiver operating limits and to control the different operating modes with efficient dedicated reconfigurable digital logic ;
- Energy harvesting and power management at micro-scale level. Internet of Things (IoTs) devices still suffer from energy loss, and this prevails the massive development of large scale networks of communicating heterogeneous systems, composed of sensors, a processing unit, and a RF transceiver. The solution to this issue is to do on-chip energy harvesting so as to optimize energy sources and to efficiently manage the available system energy. Since 2007, CIAN has developed methods, IPs, and interfaces to handle micro-scale energy sources and to soundly integrate them into low-power SoCs. A noticeable result is the operational design of a MEMS electrostatic vibration energy harvester ;
- Virtual prototyping of heterogeneous systems at high level of abstraction. Since 2007, and as a member of the Accellera Systems Initiative, CIAN has participated in the specification, the Language Rule Manual (LRM) and the user’s guide for the analog mixed signal extensions of SystemC. CIAN has developed a strong experience in the modeling and simulation of heterogeneous systems at a high level of abstraction. This allowed the design of a unified yet flexible multi-disciplinary virtual prototyping environment based on SystemC. This environment allows the simulation of a complex heterogeneous system as a whole, for which each component (whatever its related domain is, i.e. digital, analog, RF, optical, fluidic) is described and solved using the most appropriate Model of Computation (MoC).
The team works on the internal architectures of FPGAs and especially the interconnection networks of tree-like. The first objective is to develop a high-performance architecture for embedded FPGA in a SoC (eFPGA). We have proposed a mixed network architecture based on mesh and tree (Tree of Mesh). We also seek to optimize the architecture for implementing specific applications. Studies have been conducted to develop tree architectures in 3D. All studies were made in hardware and software by developing architectures and associated tools (placer, router, partitioner etc.). The current orientation concerns the configuration flows for multi-FPGA systems. The team has also designed and implemented reconfigurable RF receivers that can adapt to several wireless communication standards operating at different frequency bands.
Microelectronics & Society
Microelectronics, a fundamental technology underlying much of the digital world, has important social ramifications. Unlike other research groups in microelectronics, the CIAN team examines the interactions between digital technologies and social groups. An important theme is the study of microelectronics innovation, notably Moore’s Law. The group researches the impact of microelectronics and computer manufacturing on occupational health and environmental pollution. It also examines the intellectual history of concepts underlying digital technics, such as the history of computer logics and the history of specific devices such as field-effect and bipolar transistors. The research team is also interested in the design of “transparent” design technologies. Computer security is critical to many aspects of our society. Security depends on secure-software as well as secure hardware. The behavior of silicon chips may be altered by small modifications of code that does the circuit synthesis. Using Free Open Source Software (FOSS) to synthesize the full chip layout gives a complete insight of the designer’s intents and allows detecting further malicious modifications. FOSS is also interesting to allow low-cost chip designs fabrication for all. This motivates the efforts that the team puts in FOSS CAD for VLSI. On the digital side, the placement and routing have been improved, based on new algorithms (Coriolis project). On the analog side, we have taken advantage of the digital improvements to work on a Place and Route tool for analog and mixed-signal circuits whose importance is growing in the IoT era since they are used for receiving and transmitting data and for interfacing physical data to the digital processor.