Analog hardware security and trust
Sorbonne Universités, UPMC Univ. Paris 6, CNRS, LIP6
Starting between October 2017 and January 2018
3 year PhD grant, ~1700€ monthly gross salary
Haralampos-G. Stratigopoulos, Roselyne Chotin-Avot, Hassan Aboushady, Marie-Minerve Louërat, Dimitri Galayko
Owing to various financial factors, the contemporary semiconductor industry relies on a complex business model, wherein the vast majority of circuit intellectual property (IP) design and integrated circuit (IC) fabrication activities are outsourced to third-party design houses and foundries. The globalized and highly distributed nature of third-party entities results in a semiconductor supply chain model which exhibits several vulnerable points during the design, fabrication, and even the deployment phase of an IC. These vulnerabilities may be exploited by a knowledgeable adversary, thereby introducing various trustworthiness and security threats to the semiconductor industry and the end IC users, namely IP/IC piracy, which includes reverse engineering and counterfeiting, hardware Trojans, side-channel attacks, and fault injection attacks.
This thesis focuses on hardware security aspects specifically for analog ICs. In particular, this thesis envisions developing a large portfolio of the first obfuscation methodologies for analog ICs. Obfuscation aims at transforming the original design into one that is functionally equivalent, but the functionality is well hidden by embedding the design in a larger functional space requiring a secret key to unlock its functionality. Obfuscation will be used as a countermeasure for:
- Reverse engineering which is conducted by an attacker to (a) gain information about the internal blocks of the IC (i.e., architecture, netlist, layout functionality, implementation details, technological data, etc.) aiming at reducing the attacker’s technological disadvantage against the “author” of the IC; (b) gather necessary information for producing a counterfeit circuit; (c) gather valuable information for putting forward a successful and inescapable hardware attack; (d) locate the root-of-trust part of the IC so as to steal secret and sensitive information.
- Counterfeiting which refers to (a) illegal theft of the IC design (i.e., netlist, layout, masks, etc.) aiming at producing and selling a similar or identical (e.g., cloned) IC; (b) reselling as new an old, used, and possibly aged IC; (c) non contractual overproducing of ICs and illegitimate selling of these ICs by an untrusted foundry given that foundries have the fabrication blueprint (e.g. GDS II data).
By the end of thesis, we plan to have demonstrated on silicon an obfuscated version of an RF transceiver.
|||R. S. Chakraborty and S. Bhunia, “HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 10, 1493 – 1502, 2009.|
|||U. Guin, K. Huang, D. DiMase, J. M. Carulli, M. Tehranipoor, and Y. Makris, “Counterfeit Integrated Circuits: A Rising threat in the Global Semiconductor Supply Chain,” Proceedings of the IEEE, vol. 102, no. 8, pp. 1207 – 1228, 2014.|
|||M. Rostami, F. Koushanfar, and R. Karri, “A primer on hardware security: models, methods, and metrics,” Proceedings of the IEEE, vol. 102, no.8, pp. 1283 – 1295, 2014.|
|||Polian, “Security Aspects of Analog and Mixed-signal Circuits,” IEEE International Mixed-Signals Test Workshop, 2016.|
|||A. Vijayakumar, Vinay C. Patil, D. E. Holcomb, C. Paar, and S. Kundu, “Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques, ” IEEE Transactions on Information Forensics and Security, vol. 12., no. 1, pp. 64 – 77, 2017.|
The prospective student should be highly motivated and should have good background knowledge on analog and mixed-signal integrated circuit design, computer-aided integrated circuit design tools (e.g. Cadence), and technical computing languages (e.g. MATLAB). Knowledge on RF circuit design is definitely a plus.
About the institution:
The PhD will be conducted at the Laboratoire d’Informatique de Paris 6 (LIP6). LIP6 has as parent institutions the Centre National de la Recherche Scientific (CNRS) and the Université Pierre et Marie Curie (UPMC) which is part of Sorbonne Universités. Specifically, the student will be integrated in the Circuits Intégrés Analogiques et Numériques (CIAN) team of the Systems-on-Chip (SoC) department of LIP6. The main focuses of LIP6 are (a) safety, security, and reliability; (b) data science, intelligence, and optimization; and (c) smart devices. The CIAN team addresses specifically challenges resulting from the increasing miniaturization and heterogeneity of SoCs, the demand for trusted and reliable hardware, and the advent of emerging technologies, such as the Internet of Things (IoTs), 3D ICs, and Cyber Physical Systems (CPS).
How to apply:
Send by e-mail a detailed CV to Haralampos-G. Stratigopoulos (e-mail: haralampos.stratigopoulos AT lip6 DOT fr). At a later stage you will be requested to provide academic transcripts and recommendation letters.