Different formats and views

A library of Standard Cells provides different descriptions (or views) of each cell. These descriptions are based on different formats and languages. To be compliant with a digital design flow, a cell has to provide at least 3 views:

• Logical level model. It is the model of the functional behaviour represented by a boolean logic function. The model uses the VHDL or the Verilog language. The cell's logic function is used for logic synthesis of a digital circuit. The behavioural model is compatible with event driven simulator for functional verification of a digital circuit. The interface of the cell model (input, output) is used by the place and root operation in the circuit design flow (i.e. circuit layout);
• Transistor level netlist. It is the description of the interconnection of the set of transistors required to generate the logic behavior. It is written in spice format. This model is compatible with transistor-level simulation with ngspice, which may be used for timing characterization of the cell;
• Layout description. It is written according to the GDSII format. It is used by place and route software tools to create the layout of the digital circuit that will be sent by the designer for fabrication in a foundry.

Depending on the cell use, other descriptions may also be required:

• Schematic representation of the boolean logic function, for circuit schematic capture;
• Layout and design abstract information (Lef, Def), used by place and route software tools;
• Timing information, Liberty file (lib), used by logic synthesizers and static timing analyzers;
• Post-layout transistor spice netlist including parasitics, used by static timing analyzer and performance estimation (power, timing, area) tools.

Standards and Formats for standard cell description

• 1076-2019 - IEEE Standard for VHDL Language Reference Manual
• 1364-2005 - IEEE Standard for Verilog Hardware Description Language
• Spice format
• GDSII layout format
• LIB file format

SW EDA Tools (Free and Open Source ones)

• KLayout for layout edition, DRC (Design Rule Check) and LVS (Layout Versus Schematic) operations
• ngspice transistor-level simulator
• ghdl VHDL simulator
• si2 LEF/DEF parsers and drivers

Books

• Carver Mead and Lynn Conway (1980). Introduction to VLSI systems. Reading, Mass.: Addison-Wesley. ISBN 0201043580. OCLC 4641561.
• Computer Aids for VLSI Design, Steven M. Rubin, 1994,
• Sung-Mo Kang and Yusuf Leblebici, CMOS Digital Integrated Circuits, Analysis and Design, Mac Graw Hill, 2003.
• Yannis Tsividis and Colin McAndrew, Operation and Modeling of the MOS Transistor, Third edition, Oxford University Press, 2011.
• Yuhua Cheng and Chenming Hu, MOSFET modeling and BSIM3 User's guide, Kluwer Academic Publisher, 1999.
• Jan M. Rabey, Anantha Chandrakasan and Borivoje Nikolic, Digital Integrated Circuits, A design perspective, Prentice Hall, 2003
• Naveed Sherwani, Algorithms for VLSI Physical Design Automation, Kluwer Academic Publisher, 2004