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MipsTp2: mips_r3000_1m_dp.py

File mips_r3000_1m_dp.py, 20.3 KB (added by cobell, 14 years ago)

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1	#!/usr/bin/env python
2
3	### -------------------------------------------------------------- ###
4	# file : mips_r3000_dp.py #
5	# date : Jan 04 2010 #
6	# version : v1 #
7	# #
8	# origin : this description has been developed at LIP6 #
9	# University Paris 6 - Pierre et Marie Curie #
10	# 4 Place Jussieu 75252 Paris Cedex 05 - France #
11	# #
12	# descr. : data flow description of a five stage pipelined Mips #
13	# R3000 processor #
14	# #
15	# authors : Sophie Belloeil #
16	### -------------------------------------------------------------- ###
17
18	from stratus import *
19
20	class mips_r3000_1m_dp ( Model ) :
21
22	def Interface ( self ) :
23
24	self.INTERACTIVE = self._param['interactive']
25
26	self.ck = SignalIn ( "ck", 1 ) # external clock
27
28	self.i = SignalIn ( "i", 32 ) # instruction
29
30	self.d_in = SignalIn ( "d_in", 32 ) # data (input)
31	self.d_out = SignalOut ( "d_out", 32 ) # data (output)
32
33	self.addr = SignalOut ( "addr", 32 ) # address
34
35	self.rsdnbr_sd = SignalIn ( "rsdnbr_sd", 32 ) # source reg nbr
36	self.rtdnbr_sd = SignalIn ( "rtdnbr_sd", 32 ) # source reg nbr
37
38	self.hz_sdm_sd = SignalIn ( "hz_sdm_sd", 1 ) # s = d(i-2)
39	self.hz_sdmw_sd = SignalIn ( "hz_sdmw_sd", 1 ) # s = d(i-3,i-2)
40	self.hz_tdm_sd = SignalIn ( "hz_tdm_sd", 1 ) # t = d(i-2)
41	self.hz_tdmw_sd = SignalIn ( "hz_tdmw_sd", 1 ) # t = d(i-3,i-2)
42
43	self.hz_sdm_se = SignalIn ( "hz_sdm_se", 1 ) # s = d(i-1)
44	self.hz_sdmw_se = SignalIn ( "hz_sdmw_se", 1 ) # s = d(i-2,i-1)
45	self.hz_tdm_se = SignalIn ( "hz_tdm_se", 1 ) # t = d(i-1)
46	self.hz_tdmw_se = SignalIn ( "hz_tdmw_se", 1 ) # t = d(i-2,i-1)
47
48	self.i_jr_sd = SignalIn ( "i_jr_sd", 1 ) # jump register
49	self.btaken_sd = SignalIn ( "btaken_sd", 1 ) # branch taken
50	self.i_allj_sd = SignalIn ( "i_allj_sd", 1 ) # all jumps
51	self.i_link_sd = SignalIn ( "i_link_sd", 1 ) # link inst
52
53	self.iopsel_sd = SignalIn ( "iopsel_sd", 4 ) # i oper select
54
55	self.imdsgn_sd = SignalIn ( "imdsgn_sd", 1 ) # signed operands
56	self.i_rsgnd_se = SignalIn ( "i_rsgnd_se", 1 ) # signed result
57
58	self.i_ifmt_se = SignalIn ( "i_ifmt_se", 1 ) # i format
59	self.i_oper_se = SignalIn ( "i_oper_se", 7 ) # alu operation
60	self.i_logic_se = SignalIn ( "i_logic_se", 2 ) # logic operation
61	self.i_sub_se = SignalIn ( "i_sub_se", 1 ) # subtract
62	self.i_right_se = SignalIn ( "i_right_se", 1 ) # shift right
63
64	self.setbit_se = SignalIn ( "setbit_se", 1 ) # result for set
65
66	self.datext_sm = SignalIn ( "datext_sm", 1 ) # data extension
67	self.bytsub_sm = SignalIn ( "bytsub_sm", 3, 1 ) # byte substitute
68	self.daccess_sm = SignalIn ( "daccess_sm", 1 ) # data access
69	self.read_sm = SignalIn ( "read_sm", 1 ) # read operation
70
71	self.bubble_si = SignalIn ( "bubble_si", 1 ) # introduce bubble
72	self.hold_si = SignalIn ( "hold_si", 1 ) # hold the inst
73	self.nothold_si = SignalIn ( "nothold_si", 1 ) # don't hold the inst
74	self.shift_si = SignalIn ( "shift_si", 1 ) # shift new inst
75	self.keep_si = SignalIn ( "keep_si", 1 ) # keep the data
76	self.load_si = SignalIn ( "load_si", 1 ) # load a new data
77
78	self.notstall_sd = SignalIn ( "notstall_sd", 1 ) # don't holdt inst
79	self.bubble_sd = SignalIn ( "bubble_sd", 1 ) # introduce bubble
80	self.hold_sd = SignalIn ( "hold_sd", 1 ) # hold the inst
81	self.nothold_sd = SignalIn ( "nothold_sd", 1 ) # don't hold the inst
82	self.shift_sd = SignalIn ( "shift_sd", 1 ) # shift new inst
83	self.keep_sd = SignalIn ( "keep_sd", 1 ) # keep the data
84	self.load_sd = SignalIn ( "load_sd", 1 ) # load a new data
85
86	self.bubble_se = SignalIn ( "bubble_se", 1 ) # introduce bubble
87	self.hold_se = SignalIn ( "hold_se", 1 ) # hold the inst
88	self.nothold_se = SignalIn ( "nothold_se", 1 ) # don't hold the inst
89	self.shift_se = SignalIn ( "shift_se", 1 ) # shift new inst
90	self.keep_se = SignalIn ( "keep_se", 1 ) # keep the data
91	self.load_se = SignalIn ( "load_se", 1 ) # load a new data
92
93	self.bubble_sm = SignalIn ( "bubble_sm", 1 ) # introduce bubble
94	self.hold_sm = SignalIn ( "hold_sm", 1 ) # hold the inst
95	self.nothold_sm = SignalIn ( "nothold_sm", 1 ) # don't hold the inst
96	self.shift_sm = SignalIn ( "shift_sm", 1 ) # shift new inst
97	self.keep_sm = SignalIn ( "keep_sm", 1 ) # keep the data
98	self.load_sm = SignalIn ( "load_sm", 1 ) # load a new data
99
100	self.wreg_sw = SignalIn ( "wreg_sw", 32 ) # integer reg wen
101	self.wredopc_se = SignalIn ( "wredopc_se", 1 ) # redopc write en
102
103	self.wlo_sw = SignalIn ( "wlo_sw", 1 ) # low reg write en
104	self.whi_sw = SignalIn ( "whi_sw", 1 ) # high reg write en
105
106	self.wepc_xx = SignalIn ( "wepc_xx", 1 ) # epc write en
107	self.wepc_xm = SignalIn ( "wepc_xm", 1 ) # epc write en
108
109	self.bootev_xx = SignalIn ( "bootev_xx", 1 ) # bootstrap exc
110
111	self.badia_xm = SignalIn ( "badia_xm", 1 ) # bad inst adr
112	self.badda_xm = SignalIn ( "badda_xm", 1 ) # bad data adr
113
114	self.lui_sd = SignalIn ( "lui_sd", 1 ) # lui inst
115
116	self.shamt_se = SignalIn ( "shamt_se", 5 ) # shift amount
117
118	self.reset_xx = SignalIn ( "reset_xx", 1 ) # synchro reset
119	self.wnxtpc_xx = SignalIn ( "wnxtpc_xx", 1 ) # nxt inst ad wen
120
121	self.sr_cr_sd = SignalIn ( "sr_cr_sd", 32 ) # status/cause
122	self.be_sd = SignalIn ( "be_sd", 1 ) # bad ad reg/epc
123	self.scbe_sd = SignalIn ( "scbe_sd", 1 ) # c0 reg selection
124
125	self.bdslot_se = SignalIn ( "bdslot_se", 1 )
126	self.bdslot_sm = SignalIn ( "bdslot_sm", 1 )
127
128	self.carith_32_se= SignalOut ( "carith_32_se", 1 )
129	self.carith_31_se= SignalOut ( "carith_31_se", 1 )
130	self.rarith_31_se= SignalOut ( "rarith_31_se", 1 )
131	self.nextpc_1_se = SignalOut ( "nextpc_1_se", 1 )
132	self.nextpc_0_se = SignalOut ( "nextpc_0_se", 1 )
133	self.nextpc_31_se= SignalOut ( "nextpc_31_se", 1 )
134
135	self.res_sm = SignalOut ( "res_sm", 32 )
136
137	self.s_31_sd = SignalOut ( "s_31_sd", 1 ) # s (31)
138	self.s_eq_t_sd = SignalOut ( "s_eq_t_sd", 1 ) # s = t
139	self.s_eq_z_sd = SignalOut ( "s_eq_z_sd", 1 ) # s = 0
140
141	self.s_4_0_se = SignalOut ( "s_4_0_se", 5 ) # s (4 downto 0)
142
143	self.test = SignalIn ( "test", 1 ) # test mode
144	self.scin = SignalIn ( "scin", 1 ) # scan in
145	self.scout = SignalOut ( "scout", 1 ) # scan out
146
147	self.vdd = VddIn ( "vdd" )
148	self.vss = VssIn ( "vss" )
149
150	def Netlist (self) :
151	### Signaux internes ###
152	# A COMPLETER, MODIFIER ... Copie conforme de la liste du fichier vbe la uniquement pour vous faire gagner du temps d'Ã©criture
153	ck_sx = Signal ( "ck_sx", 1 ) # internal clock
154
155	i_ri = Signal ( "i_ri", 32 ) # instruction reg
156	i_rd = Signal ( "i_rd", 32 ) # instruction reg
157	i_re = Signal ( "i_re", 32 ) # instruction reg
158	i_rm = Signal ( "i_rm", 32 ) # instruction reg
159
160	jadr_sd = Signal ( "jadr_sd", 32 ) # next inst address
161	badr_sd = Signal ( "badr_sd", 32 ) # next inst address
162	nextpc_sd = Signal ( "nextpc_sd", 32 ) # next inst address
163	nextpc_xx = Signal ( "nextpc_xx", 32 ) # next inst adr (hw)
164	nextpc_rd = Signal ( "nextpc_rd", 32 ) # next inst address
165	nextpc_re = Signal ( "nextpc_re", 32 ) # next inst address
166
167	pc_ri = Signal ( "pc_ri", 32 ) # instruction address
168	pc_rd = Signal ( "pc_rd", 32 ) # instruction address
169	pc_re = Signal ( "pc_re", 32 ) # instruction address
170	redopc_re = Signal ( "redopc_re", 32 ) # old inst address
171
172	s_sd = Signal ( "s_sd", 32 ) # s from reg bank
173	s_mw_sd = Signal ( "s_mw_sd", 32 ) # effective s oper
174	soper_sd = Signal ( "soper_sd", 32 ) # effective s oper
175	soper_rd = Signal ( "soper_rd", 32 ) # effective s oper
176
177	t_sd = Signal ( "t_sd", 32 ) # t from reg bank
178	t_mw_sd = Signal ( "t_mw_sd", 32 ) # effective t oper
179	toper_sd = Signal ( "toper_sd", 32 ) # effective t oper
180	effto_sd = Signal ( "effto_sd", 32 ) # effective t oper
181	toper_rd = Signal ( "toper_rd", 32 ) # effective t oper
182
183	s_mw_se = Signal ( "s_mw_se", 32 ) # s operand
184	soper_se = Signal ( "soper_se", 32 ) # s operand
185	xarith_se = Signal ( "xarith_se", 32 ) # x oper for arithm
186
187	t_mw_se = Signal ( "t_mw_se", 32 ) # t operand
188	toper_se = Signal ( "toper_se", 32 ) # t operand
189	yarith_se = Signal ( "yarith_se", 32 ) # y oper for arithm
190
191	cop0op_sd = Signal ( "cop0op_sd", 32 ) # cop 0 source opr
192	br_epc_sd = Signal ( "br_epc_sd", 32 ) # bad ad reg/epc
193
194	otheri_sd = Signal ( "otheri_sd", 32 ) # immediate oper
195	ioper_sd = Signal ( "ioper_sd", 32 ) # eff immediate oper
196	ioper_rd = Signal ( "ioper_rd", 32 ) # eff immediate oper
197
198	s_cp_t_sd = Signal ( "s_cp_t_sd", 32 ) # compare s & t
199
200	imdsex_sd = Signal ( "imdsex_sd", 16 ) # offset extension
201	offset_sd = Signal ( "offset_sd", 32 ) # address offset
202
203	seqadr_sd = Signal ( "seqadr_sd", 32 ) # sequential inst adr
204	seqcry_sd = Signal ( "seqcry_sd", 33 ) # carry (+ 4)
205
206	jmpadr_sd = Signal ( "jmpadr_sd", 32 ) # jump adress
207	braadr_sd = Signal ( "braadr_sd", 32 ) # branch adress
208	bracry_sd = Signal ( "bracry_sd", 33 ) # carry (+ offset)
209
210	r1_rw = Signal ( "r1_rw", 32 ) # integer reg # 1
211	r2_rw = Signal ( "r2_rw", 32 ) # integer reg # 2
212	r3_rw = Signal ( "r3_rw", 32 ) # integer reg # 3
213	r4_rw = Signal ( "r4_rw", 32 ) # integer reg # 4
214	r5_rw = Signal ( "r5_rw", 32 ) # integer reg # 5
215	r6_rw = Signal ( "r6_rw", 32 ) # integer reg # 6
216	r7_rw = Signal ( "r7_rw", 32 ) # integer reg # 7
217	r8_rw = Signal ( "r8_rw", 32 ) # integer reg # 8
218	r9_rw = Signal ( "r9_rw", 32 ) # integer reg # 9
219	r10_rw = Signal ( "r10_rw", 32 ) # integer reg # 10
220	r11_rw = Signal ( "r11_rw", 32 ) # integer reg # 11
221	r12_rw = Signal ( "r12_rw", 32 ) # integer reg # 12
222	r13_rw = Signal ( "r13_rw", 32 ) # integer reg # 13
223	r14_rw = Signal ( "r14_rw", 32 ) # integer reg # 14
224	r15_rw = Signal ( "r15_rw", 32 ) # integer reg # 15
225	r16_rw = Signal ( "r16_rw", 32 ) # integer reg # 16
226	r17_rw = Signal ( "r17_rw", 32 ) # integer reg # 17
227	r18_rw = Signal ( "r18_rw", 32 ) # integer reg # 18
228	r19_rw = Signal ( "r19_rw", 32 ) # integer reg # 19
229	r20_rw = Signal ( "r20_rw", 32 ) # integer reg # 20
230	r21_rw = Signal ( "r21_rw", 32 ) # integer reg # 21
231	r22_rw = Signal ( "r22_rw", 32 ) # integer reg # 22
232	r23_rw = Signal ( "r23_rw", 32 ) # integer reg # 23
233	r24_rw = Signal ( "r24_rw", 32 ) # integer reg # 24
234	r25_rw = Signal ( "r25_rw", 32 ) # integer reg # 25
235	r26_rw = Signal ( "r26_rw", 32 ) # integer reg # 26
236	r27_rw = Signal ( "r27_rw", 32 ) # integer reg # 27
237	r28_rw = Signal ( "r28_rw", 32 ) # integer reg # 28
238	r29_rw = Signal ( "r29_rw", 32 ) # integer reg # 29
239	r30_rw = Signal ( "r30_rw", 32 ) # integer reg # 30
240	r31_rw = Signal ( "r31_rw", 32 ) # integer reg # 31
241	lo_rw = Signal ( "lo_rw", 32 ) # low register
242	hi_rw = Signal ( "hi_rw", 32 ) # high register
243	carith_se = Signal ( "carith_se", 32 ) # carry in arithm
244	rarith_se = Signal ( "rarith_se", 32 ) # result of arithm
245
246	xoper_se = Signal ( "xoper_se", 32 ) # effective x operand
247	yoper_se = Signal ( "yoper_se", 32 ) # effective y operand
248
249	shiftin_se = Signal ( "shiftin_se", 32 ) # shift in
250	shright_se = Signal ( "shright_se", 32 ) # right shift result
251	shlieft_se = Signal ( "shleft_se", 32 ) # left shift result
252	rshift_se = Signal ( "rshift_se", 32 ) # shifter's result
253
254	and_se = Signal ( "and_se", 32 ) # logic oper. result
255	or_se = Signal ( "or_se", 32 ) # logic oper. result
256	xor_se = Signal ( "xor_se", 32 ) # logic oper. result
257	ornor_se = Signal ( "ornor_se", 32 ) # logic oper. result
258	andxor_se = Signal ( "andxor_se", 32 ) # logic oper. result
259	rlogic_se = Signal ( "rlogic_se", 32 ) # logic oper. result
260
261	rtest_se = Signal ( "rtest_se", 32 ) # test oper. result
262
263	ra_rt_se = Signal ( "ra_rt_se", 32 ) # arith/test result
264	so_to_se = Signal ( "so_to_se", 32 ) # soper/toper
265	i_s_t_se = Signal ( "i_s_t_se", 32 ) # ioper/soper/toper
266
267	res_se = Signal ( "res_se", 32 ) # result out of alu
268	res_re = Signal ( "res_re", 32 ) # result out of alu
269
270	wdata_re = Signal ( "wdata_re", 32 ) # data bus output reg
271
272	d_15x_sm = Signal ( "d_15x_sm", 24, 8 ) # read data
273	d_31x_sm = Signal ( "d_31x_sm", 24, 8 ) # read data
274	d_ext_sm = Signal ( "d_ext_sm", 24, 8 ) # read data
275	data_e_sm = Signal ( "data_e_sm", 32 ) # read data
276	data_o_sm = Signal ( "data_o_sm", 32 ) # read data
277	data_x_sm = Signal ( "data_x_sm", 32 ) # read data
278
279	reddat_sm = Signal ( "reddat_sm", 32 ) # aligned data
280
281	data_sm = Signal ( "data_sm", 32 ) # data bus / res
282	data_rm = Signal ( "data_rm", 32 ) # data bus input reg
283
284	badvadr_rm = Signal ( "badvadr_rm", 32 ) # bad virtual adr reg
285
286	epc_xx = Signal ( "epc_xx", 32 ) # exc pg counter
287	epc_xm = Signal ( "epc_xm", 32 ) # exc pg counter
288	epc_rx = Signal ( "epc_rx", 32 ) # exc pg counter reg
289
290	r0_rw = Signal ( "r0_rw", 32 )
291
292	nop_i = Signal ( "nop_i", 32 ) # addu 0,0,0
293
294	m_writ_w = Signal ( "m_writ_w", 2 ) # write word
295	m_writ_h = Signal ( "m_writ_h", 2 ) # write half
296	m_writ_b = Signal ( "m_writ_b", 2 ) # write bit
297	m_read_b = Signal ( "m_read_b", 2 ) # read bit
298
299	excphnd_a = Signal ( "excphnd_a", 32 ) # handler adr
300	boothnd_a = Signal ( "boothnd_a", 32 ) # handler adr
301	reset_a = Signal ( "reset_a", 32 ) # reset adr
302
303	badvaddr_s = Signal ( "badvaddr_s", 5 ) # badvaddr
304	status_s = Signal ( "status_s", 5 ) # status
305	cause_s = Signal ( "cause_s", 5 ) # cause
306	epc_s = Signal ( "epc_s", 5 ) # epc
307	prid_s = Signal ( "prid_s", 5 ) # prid
308
309	r_fmt_o = Signal ( "r_fmt_o", 4 ) # r format
310	i_fmt_o = Signal ( "i_fmt_o", 4 ) # i format
311	j_fmt_o = Signal ( "j_fmt_o", 4 ) # j format
312	illgl_o = Signal ( "illgl_o", 4 ) # illegal ins
313
314	d_use_st_o = Signal ( "d_use_st_o", 4 ) # dec use st
315	d_use_s_o = Signal ( "d_use_s_o", 4 ) # dec use s
316	d_use_t_o = Signal ( "d_use_t_o", 4 ) # dec use t
317	e_use_st_o = Signal ( "e_use_st_o", 4 ) # exe use st
318	e_use_s_o = Signal ( "e_use_s_o", 4 ) # exe use s
319	e_use_t_o = Signal ( "e_use_t_o", 4 ) # exe use t
320	no_use_o = Signal ( "no_use_o", 4 ) # no oper
321
322	o_signd_o = Signal ( "o_signd_o", 1 ) # signed
323	o_usign_o = Signal ( "o_usign_o", 1 ) # unsigned
324
325	arith_o = Signal ( "arith_o", 7 ) # arith oper
326	test_o = Signal ( "test_o", 7 ) # test oper
327	logic_o = Signal ( "logic_o", 7 ) # logic oper
328	shift_o = Signal ( "shift_o", 7 ) # shift oper
329	soper_o = Signal ( "soper_o", 7 ) # take s oper
330	toper_o = Signal ( "toper_o", 7 ) # take t oper
331	ioper_o = Signal ( "ioper_o", 7 ) # take i oper
332
333	add_o = Signal ( "add_o", 2 ) # add oper
334	sub_o = Signal ( "sub_o", 2 ) # sub oper
335
336	sleft_o = Signal ( "sleft_o", 2 ) # shift left
337	sright_o = Signal ( "sright_o", 2 ) # shift right
338
339	or_o = Signal ( "or_o", 2 ) # or oper
340	and_o = Signal ( "and_o", 2 ) # and oper
341	xor_o = Signal ( "xor_o", 2 ) # xor oper
342	nor_o = Signal ( "nor_o", 2 ) # nor oper
343
344	r_signd_o = Signal ( "r_signd_o", 1 ) # sign res
345	r_usign_o = Signal ( "r_usign_o", 1 ) # unsign res
346
347	ovr_o = Signal ( "ovr_o", 1 ) # overflow
348	nov_o = Signal ( "nov_o", 1 ) # no overflow
349
350	e_pdc_rd_o = Signal ( "e_pdc_rd_o", 3 ) # res out exe
351	e_pdc_31_o = Signal ( "e_pdc_31_o", 3 ) # res out exe
352	m_pdc_rd_o = Signal ( "m_pdc_rd_o", 3 ) # res out mem
353	no_pdc_o = Signal ( "no_pdc_o", 3 ) # no result
354
355	nobra_o = Signal ( "nobra_o", 1 ) # no branch
356	brnch_o = Signal ( "brnch_o", 1 ) # branch
357
358	loadw_o = Signal ( "loadw_o", 5 ) # load word
359	loadh_o = Signal ( "loadh_o", 5 ) # load half
360	loadb_o = Signal ( "loadb_o", 5 ) # load byte
361	storw_o = Signal ( "storw_o", 5 ) # store word
362	storh_o = Signal ( "storh_o", 5 ) # store half
363	storb_o = Signal ( "storb_o", 5 ) # store byte
364	swapw_o = Signal ( "swapw_o", 5 ) # swap word
365	nomem_o = Signal ( "nomem_o", 5 ) # no access
366
367
368	### Creation des Generateurs utiles ###
369	# A COMPLETER, MODIFIER ...
370	Generate('DpgenConst', "instnop_i", param= { 'nbit' : 32, 'const' : "0x00000021" } )
371	Generate('DpgenConst', "instexcphnd_a", param= { 'nbit' : 32, 'const' : "0x80000080" } )
372	Generate('DpgenConst', "instboothnd_a", param= { 'nbit' : 32, 'const' : "0xbfc00180" } )
373	Generate('DpgenConst', "instreset_a", param= { 'nbit' : 32, 'const' : "0xbfc00000" } )
374	Generate("DpgenConst", 'const0000', param= { 'nbit' : 16, 'const' : "0x0000" } )
375	Generate("DpgenConst", 'const0_2', param= { 'nbit' : 2, 'const' : "0b00" } )
376	Generate("DpgenConst", 'const4_32', param= { 'nbit' : 32, 'const' : "0x00000004" } )
377	Generate('DpgenConst', "const0_1", param= { 'nbit' : 1, 'const' : "0b0" } )
378	Generate('DpgenConst', "const1_1", param= { 'nbit' : 1, 'const' : "0b1" } )
379	Generate("DpgenConst", 'const0_31', param= { 'nbit': 31, 'const' : "0b0000000000000000000000000000000" } )
380
381
382	### Instanciation ###
383	# A FAIRE

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