Changes between Version 4 and Version 5 of partners


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Timestamp:
Jun 16, 2008, 3:52:13 PM (16 years ago)
Author:
fpecheux
Comment:

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  • partners

    v4 v5  
    2121*       evaluating the applicability on realistic application scenarios of distributed adaptive and recursive mapping strategies for parallel MPSoC architectures
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     23'''Fabien CLERMIDY''' was born in Bourg-en-Bresse, France, in 1971. He received the Electronic Engineering Diploma from ENSIMEV in 1994 and his Ph.D. Degree in Microelectronics from the National Polytechnic Institute of Grenoble, France, in 1999.In 2000, he joined the CEA-LIST laboratory in Paris. He was involved in the design of an application specific parallel computer as designer. In 2003, he moved to the CEA-LETI in the Center for Innovation in micro & nanotechnology (MINATEC), Grenoble. From 2003 to 2006, he was the architect of the FAUST NoC structure and was in charge of chip verification. In 2006, he took the lead of the FAUST2 project for software and cognitive radio. He has published 11 papers in conferences. He holds 8 patents in the fields of fault-tolerant architectures, cryptography, NoC architectures, GALS structures and molecular electronics.
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     25'''Edith BEIGNE''' was born in Lamastre, France, in 1975. She received the Electronic Engineering Diploma from the National Polytechnic Institute of Grenoble, France, in 1998. In 1998, she joined the CEA/LETI laboratory in the Center for Innovation in micro & nanotechnology (MINATEC), Grenoble. She was first involved in contactless RFID mixed signal systems. In 2001, she began the asynchronous logic design activity in cryptographic and contactless systems. As regards the development of the FAUST project, she designed a part of the asynchronous Network-On-Chip. Since 2006, she has been in charge of ALPIN project, a power aware GALS SoC implementing dynamic and static low power techniques based on an asynchronous NoC.
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     27'''Christian BERNARD''' was born  in 1956, and received its engineer degree  at ENSIMAG (Ecole Nationale Superieure d’Informatique et Mathematiques appliquées de Grenoble) in 1979. He was formerly designer and architect at Bull (Les Clayes sous Bois, France) and participated to the design of the Bull Mainframes during 19 years. He joined MINATEC-LETI in October 2001, and was project leader and designed several chips and reconfigurables blocks for telecom applications.
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     29'''François BERTRAND''' received a PhD degree in Microelectronics and Integrated Circuits Design from INPG (Polytechnics Institute at Grenoble). He worked as a researcher at the INPG/TIMA laboratory, as a senior project engineer in a private company for the design of very complex integrated circuits (BULL mainframe), and joined CEA/LETI in 1988. At CEA/LETI, he has successively the head of the Architecture and Integrated Programs of LETI, Director of JESSI programs on microelectronics for SMEs, and the head of the IAN laboratory at MINATEC/LETI since 1996. The IAN laboratory (30 permanent staff members) is developing digital integrated
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