[1] | 1 | /* |
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| 2 | * hal_context.c - implementation of Thread Context API for TSAR-MIPS32 |
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| 3 | * |
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| 4 | * Author Alain Greiner (2016) |
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| 5 | * |
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| 6 | * Copyright (c) UPMC Sorbonne Universites |
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| 7 | * |
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| 8 | * This file is part of ALMOS-MKH. |
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| 9 | * |
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| 10 | * ALMOS-MKH.is free software; you can redistribute it and/or modify it |
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| 11 | * under the terms of the GNU General Public License as published by |
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| 12 | * the Free Software Foundation; version 2.0 of the License. |
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| 13 | * |
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| 14 | * ALMOS-MKH.is distributed in the hope that it will be useful, but |
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| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 17 | * General Public License for more details. |
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| 18 | * |
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| 19 | * You should have received a copy of the GNU General Public License |
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| 20 | * along with ALMOS-MKH.; if not, write to the Free Software Foundation, |
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| 21 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 22 | */ |
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| 23 | |
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| 24 | #include <hal_types.h> |
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[317] | 25 | #include <hal_switch.h> |
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[1] | 26 | #include <memcpy.h> |
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| 27 | #include <thread.h> |
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| 28 | #include <string.h> |
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| 29 | #include <process.h> |
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[8] | 30 | #include <printk.h> |
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[1] | 31 | #include <vmm.h> |
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| 32 | #include <core.h> |
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| 33 | #include <cluster.h> |
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| 34 | #include <hal_context.h> |
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[406] | 35 | #include <hal_kentry.h> |
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[1] | 36 | |
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[151] | 37 | ///////////////////////////////////////////////////////////////////////////////////////// |
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| 38 | // Define various SR values for TSAR-MIPS32 |
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| 39 | ///////////////////////////////////////////////////////////////////////////////////////// |
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| 40 | |
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[406] | 41 | #define SR_USR_MODE 0x0000FC13 |
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| 42 | #define SR_USR_MODE_FPU 0x2000FC13 |
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| 43 | #define SR_SYS_MODE 0x0000FC00 |
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[151] | 44 | |
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| 45 | ///////////////////////////////////////////////////////////////////////////////////////// |
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[406] | 46 | // This structuree defines the cpu_context for TSAR MIPS32. |
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[151] | 47 | // These registers are saved/restored at each context switch. |
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[406] | 48 | // WARNING : check the two CONFIG_CPU_CTX_SIZE & CONFIG_FPU_CTX_SIZE configuration |
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| 49 | // parameterss when modifying this structure. |
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[151] | 50 | ///////////////////////////////////////////////////////////////////////////////////////// |
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| 51 | |
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| 52 | typedef struct hal_cpu_context_s |
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| 53 | { |
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[296] | 54 | uint32_t c0_epc; // slot 0 |
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| 55 | uint32_t at_01; // slot 1 |
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| 56 | uint32_t v0_02; // slot 2 |
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| 57 | uint32_t v1_03; // slot 3 |
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| 58 | uint32_t a0_04; // slot 4 |
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| 59 | uint32_t a1_05; // slot 5 |
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| 60 | uint32_t a2_06; // slot 6 |
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| 61 | uint32_t a3_07; // slot 7 |
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| 62 | |
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| 63 | uint32_t t0_08; // slot 8 |
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| 64 | uint32_t t1_09; // slot 9 |
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| 65 | uint32_t t2_10; // slot 10 |
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| 66 | uint32_t t3_11; // slot 11 |
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| 67 | uint32_t t4_12; // slot 12 |
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| 68 | uint32_t t5_13; // slot 13 |
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| 69 | uint32_t t6_14; // slot 14 |
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| 70 | uint32_t t7_15; // slot 15 |
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| 71 | |
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| 72 | uint32_t s0_16; // slot 16 |
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| 73 | uint32_t s1_17; // slot 17 |
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| 74 | uint32_t s2_18; // slot 18 |
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| 75 | uint32_t s3_19; // slot 19 |
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| 76 | uint32_t s4_20; // slot 20 |
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| 77 | uint32_t s5_21; // slot 21 |
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| 78 | uint32_t s6_22; // slot 22 |
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| 79 | uint32_t s7_23; // slot 23 |
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| 80 | |
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| 81 | uint32_t t8_24; // slot 24 |
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[406] | 82 | uint32_t t9_25; // slot 25 |
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[296] | 83 | uint32_t hi_26; // slot 26 |
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| 84 | uint32_t lo_27; // slot 27 |
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| 85 | uint32_t gp_28; // slot 28 |
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| 86 | uint32_t sp_29; // slot 29 |
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| 87 | uint32_t fp_30; // slot 30 |
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| 88 | uint32_t ra_31; // slot 31 |
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| 89 | |
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| 90 | uint32_t c2_ptpr; // slot 32 |
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| 91 | uint32_t c2_mode; // slot 33 |
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| 92 | |
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| 93 | uint32_t c0_sr; // slot 34 |
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| 94 | uint32_t c0_th; // slot 35 |
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[151] | 95 | } |
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| 96 | hal_cpu_context_t; |
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| 97 | |
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| 98 | ///////////////////////////////////////////////////////////////////////////////////////// |
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| 99 | // This structure defines the fpu_context for TSAR MIPS32. |
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| 100 | ///////////////////////////////////////////////////////////////////////////////////////// |
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| 101 | |
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| 102 | typedef struct hal_fpu_context_s |
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| 103 | { |
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| 104 | uint32_t fpu_regs[32]; |
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| 105 | } |
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| 106 | hal_fpu_context_t; |
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| 107 | |
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[296] | 108 | |
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| 109 | ///////////////////////////////////////////////////////////////////////////////////////// |
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| 110 | // CPU context access functions |
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| 111 | ///////////////////////////////////////////////////////////////////////////////////////// |
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| 112 | |
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| 113 | ///////////////////////////////////////////////////////////////////////////////////////// |
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[406] | 114 | // This function allocates and initializes the cpu_context stucture in thread descriptor. |
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| 115 | // The following context slots are initialised by this function: |
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| 116 | // GPR : a0_04 / sp_29 / fp_30 / ra_31 |
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| 117 | // CP0 : c0_sr / c0_th / c0_epc |
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[296] | 118 | // CP2 : c2_ptpr / c2_mode |
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| 119 | ///////////////////////////////////////////////////////////////////////////////////////// |
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| 120 | error_t hal_cpu_context_create( thread_t * thread ) |
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[1] | 121 | { |
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| 122 | kmem_req_t req; |
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| 123 | |
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[406] | 124 | assert( (sizeof(hal_cpu_context_t) <= CONFIG_CPU_CTX_SIZE) , __FUNCTION__ , |
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| 125 | "inconsistent CPU context size" ); |
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| 126 | |
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| 127 | context_dmsg("\n[DMSG] %s : enters for thread %x in process %x\n", |
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[8] | 128 | __FUNCTION__ , thread->trdid , thread->process->pid ); |
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| 129 | |
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[1] | 130 | // allocate memory for cpu_context |
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[8] | 131 | req.type = KMEM_CPU_CTX; |
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[1] | 132 | req.flags = AF_KERNEL | AF_ZERO; |
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| 133 | |
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| 134 | hal_cpu_context_t * context = (hal_cpu_context_t *)kmem_alloc( &req ); |
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| 135 | if( context == NULL ) return ENOMEM; |
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| 136 | |
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| 137 | // set cpu context pointer in thread |
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| 138 | thread->cpu_context = (void*)context; |
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| 139 | |
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| 140 | // stack pointer, status register and mmu_mode depends on thread type |
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| 141 | uint32_t sp_29; |
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| 142 | uint32_t c0_sr; |
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| 143 | uint32_t c2_mode; |
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| 144 | if( thread->type == THREAD_USER ) |
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| 145 | { |
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| 146 | sp_29 = ((uint32_t)thread->u_stack_base) + thread->u_stack_size; |
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| 147 | c0_sr = SR_USR_MODE; |
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| 148 | c2_mode = 0xF; |
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| 149 | } |
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| 150 | else |
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| 151 | { |
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| 152 | sp_29 = ((uint32_t)thread->k_stack_base) + thread->k_stack_size; |
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| 153 | c0_sr = SR_SYS_MODE; |
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| 154 | c2_mode = 0x3; |
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| 155 | } |
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| 156 | |
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| 157 | // align stack pointer on a double word boundary |
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| 158 | sp_29 = (sp_29 - 8) & (~ 0x7); |
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| 159 | |
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| 160 | // initialise context |
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[406] | 161 | context->a0_04 = (uint32_t)thread->entry_args; |
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[1] | 162 | context->sp_29 = sp_29; |
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[406] | 163 | context->fp_30 = sp_29; // TODO check this [AG] |
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| 164 | context->ra_31 = (uint32_t)&hal_kentry_eret; |
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| 165 | context->c0_epc = (uint32_t)thread->entry_func; |
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[1] | 166 | context->c0_sr = c0_sr; |
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| 167 | context->c0_th = (uint32_t)thread; |
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| 168 | context->c2_ptpr = (uint32_t)((thread->process->vmm.gpt.ppn) >> 1); |
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| 169 | context->c2_mode = c2_mode; |
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| 170 | |
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[406] | 171 | context_dmsg("\n[DMSG] %s : exit for thread %x in process %x\n" |
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| 172 | " - a0 = %x\n" |
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| 173 | " - sp = %x\n" |
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| 174 | " - fp = %x\n" |
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| 175 | " - ra = %x\n" |
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| 176 | " - sr = %x\n" |
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| 177 | " - th = %x\n" |
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| 178 | " - epc = %x\n" |
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| 179 | " - ptpr = %x\n" |
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| 180 | " - mode = %x\n", |
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| 181 | __FUNCTION__ , thread->trdid , thread->process->pid, |
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| 182 | context->a0_04, context->sp_29, context->fp_30, context->ra_31, |
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| 183 | context->c0_sr, context->c0_th, context->c0_epc, |
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| 184 | context->c2_ptpr, context->c2_mode ); |
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| 185 | return 0; |
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[8] | 186 | |
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[1] | 187 | } // end hal_cpu_context_create() |
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| 188 | |
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[296] | 189 | ///////////////////////////////////////////////// |
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| 190 | void hal_cpu_context_display( thread_t * thread ) |
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| 191 | { |
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| 192 | hal_cpu_context_t * ctx = (hal_cpu_context_t *)thread->cpu_context; |
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| 193 | |
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[406] | 194 | printk("\n***** CPU context for thread %x in process %x / cycle %d\n" |
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[296] | 195 | " gp_28 = %X sp_29 = %X ra_31 = %X\n" |
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| 196 | " c0_sr = %X c0_epc = %X c0_th = %X\n" |
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| 197 | " c2_ptpr = %X c2_mode = %X\n", |
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[406] | 198 | thread->trdid, thread->process->pid, hal_time_stamp(), |
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[296] | 199 | ctx->gp_28 , ctx->sp_29 , ctx->ra_31, |
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| 200 | ctx->c0_sr , ctx->c0_epc , ctx->c0_th, |
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| 201 | ctx->c2_ptpr , ctx->c2_mode ); |
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| 202 | |
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[317] | 203 | } // end hal_context_display() |
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| 204 | |
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| 205 | ///////////////////////////////////////////////////////////////////////////////////////// |
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| 206 | // These registers are saved/restored to/from CPU context defined by <ctx> argument. |
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| 207 | // - GPR : all, but (zero, k0, k1), plus (hi, lo) |
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[406] | 208 | // - CP0 : c0_th , c0_sr , C0_epc |
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| 209 | // - CP2 : c2_ptpr , C2_mode |
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[317] | 210 | ///////////////////////////////////////////////////////////////////////////////////////// |
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[406] | 211 | // old_thread : pointer on current thread descriptor |
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| 212 | // new_thread : pointer on new thread descriptor |
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| 213 | ///////////////////////////////////////////////////////////////////////////////////////// |
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| 214 | void hal_cpu_context_switch( thread_t * old_thread, |
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| 215 | thread_t * new_thread ) |
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[311] | 216 | { |
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[406] | 217 | hal_cpu_context_t * ctx_old = old_thread->cpu_context; |
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| 218 | hal_cpu_context_t * ctx_new = new_thread->cpu_context; |
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[317] | 219 | |
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| 220 | #if CONFIG_CONTEXT_DEBUG |
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[406] | 221 | hal_cpu_context_display( old_thread ); |
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| 222 | hal_cpu_context_display( new_thread ); |
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[317] | 223 | #endif |
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| 224 | |
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[406] | 225 | // reset loadable field in new thread descriptor |
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| 226 | new_thread->flags &= ~THREAD_FLAG_LOADABLE; |
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| 227 | |
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[317] | 228 | hal_do_switch( ctx_old , ctx_new ); |
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[311] | 229 | } |
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| 230 | |
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[1] | 231 | ///////////////////////////////////////////// |
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| 232 | error_t hal_cpu_context_copy( thread_t * dst, |
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| 233 | thread_t * src ) |
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| 234 | { |
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| 235 | kmem_req_t req; |
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| 236 | |
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| 237 | // allocate memory for dst cpu_context |
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[8] | 238 | req.type = KMEM_CPU_CTX; |
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[1] | 239 | req.size = sizeof(hal_cpu_context_t); |
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| 240 | req.flags = AF_KERNEL | AF_ZERO; |
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| 241 | |
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| 242 | hal_cpu_context_t * dst_context = (hal_cpu_context_t *)kmem_alloc( &req ); |
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| 243 | if( dst_context == NULL ) return ENOMEM; |
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| 244 | |
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| 245 | // set cpu context pointer in dst thread |
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| 246 | dst->cpu_context = dst_context; |
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| 247 | |
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| 248 | // get cpu context pointer from src thread |
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| 249 | hal_cpu_context_t * src_context = src->cpu_context; |
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| 250 | |
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| 251 | // copy CPU context from src to dst |
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| 252 | memcpy( dst_context , src_context , sizeof(hal_cpu_context_t) ); |
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| 253 | |
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| 254 | return 0; |
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[317] | 255 | |
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[1] | 256 | } // end hal_cpu_context_copy() |
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| 257 | |
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| 258 | ///////////////////////////////////////////////// |
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| 259 | void hal_cpu_context_destroy( thread_t * thread ) |
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| 260 | { |
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| 261 | kmem_req_t req; |
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| 262 | |
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[8] | 263 | req.type = KMEM_CPU_CTX; |
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[1] | 264 | req.ptr = thread->cpu_context; |
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| 265 | kmem_free( &req ); |
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| 266 | |
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| 267 | } // end hal_cpu_context_destroy() |
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| 268 | |
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[317] | 269 | |
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[1] | 270 | /////////////////////////////////////////////////// |
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| 271 | error_t hal_fpu_context_create( thread_t * thread ) |
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| 272 | { |
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| 273 | kmem_req_t req; |
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| 274 | |
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[406] | 275 | assert( (sizeof(hal_fpu_context_t) <= CONFIG_FPU_CTX_SIZE) , __FUNCTION__ , |
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| 276 | "inconsistent FPU context size" ); |
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| 277 | |
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[1] | 278 | // allocate memory for uzone |
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[8] | 279 | req.type = KMEM_FPU_CTX; |
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[1] | 280 | req.flags = AF_KERNEL | AF_ZERO; |
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| 281 | |
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| 282 | hal_fpu_context_t * context = (hal_fpu_context_t *)kmem_alloc( &req ); |
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| 283 | if( context == NULL ) return ENOMEM; |
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| 284 | |
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| 285 | // set fpu context pointer in thread |
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| 286 | thread->fpu_context = (void*)context; |
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| 287 | |
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| 288 | return 0; |
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| 289 | } // hal_fpu_context_create() |
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| 290 | |
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| 291 | ///////////////////////////////////////////// |
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| 292 | error_t hal_fpu_context_copy( thread_t * dst, |
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| 293 | thread_t * src ) |
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| 294 | { |
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| 295 | kmem_req_t req; |
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| 296 | |
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| 297 | // allocate memory for dst fpu_context |
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[8] | 298 | req.type = KMEM_FPU_CTX; |
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[1] | 299 | req.flags = AF_KERNEL | AF_ZERO; |
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| 300 | |
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| 301 | hal_fpu_context_t * dst_context = (hal_fpu_context_t *)kmem_alloc( &req ); |
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| 302 | if( dst_context == NULL ) return ENOMEM; |
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| 303 | |
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| 304 | // set fpu context pointer in dst thread |
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| 305 | dst->fpu_context = (void*)dst_context; |
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| 306 | |
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| 307 | // get fpu context pointer from src thread |
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| 308 | hal_fpu_context_t * src_context = src->fpu_context; |
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| 309 | |
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| 310 | // copy CPU context from src to dst |
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| 311 | memcpy( dst_context , src_context , sizeof(hal_fpu_context_t) ); |
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| 312 | |
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| 313 | return 0; |
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| 314 | } // end hal_fpu_context_copy() |
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| 315 | |
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| 316 | ///////////////////////////////////////////////// |
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| 317 | void hal_fpu_context_destroy( thread_t * thread ) |
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| 318 | { |
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| 319 | kmem_req_t req; |
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| 320 | |
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[8] | 321 | req.type = KMEM_FPU_CTX; |
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[1] | 322 | req.ptr = thread->fpu_context; |
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| 323 | kmem_free( &req ); |
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| 324 | |
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| 325 | } // end hal_fpu_context_destroy() |
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| 326 | |
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| 327 | ////////////////////////////////////////////// |
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| 328 | void hal_fpu_context_save( thread_t * thread ) |
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| 329 | { |
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| 330 | uint32_t ctx = (uint32_t)thread->fpu_context; |
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| 331 | |
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| 332 | asm volatile( |
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| 333 | ".set noreorder \n" |
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| 334 | "swc1 $f0, 0*4(%0) \n" |
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| 335 | "swc1 $f1, 1*4(%0) \n" |
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| 336 | "swc1 $f2, 2*4(%0) \n" |
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| 337 | "swc1 $f3, 3*4(%0) \n" |
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| 338 | "swc1 $f4, 4*4(%0) \n" |
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| 339 | "swc1 $f5, 5*4(%0) \n" |
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| 340 | "swc1 $f6, 6*4(%0) \n" |
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| 341 | "swc1 $f7, 7*4(%0) \n" |
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| 342 | "swc1 $f8, 8*4(%0) \n" |
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| 343 | "swc1 $f9, 9*4(%0) \n" |
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| 344 | "swc1 $f10, 10*4(%0) \n" |
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| 345 | "swc1 $f11, 11*4(%0) \n" |
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| 346 | "swc1 $f12, 12*4(%0) \n" |
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| 347 | "swc1 $f13, 13*4(%0) \n" |
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| 348 | "swc1 $f14, 14*4(%0) \n" |
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| 349 | "swc1 $f15, 15*4(%0) \n" |
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| 350 | "swc1 $f16, 16*4(%0) \n" |
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| 351 | "swc1 $f17, 17*4(%0) \n" |
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| 352 | "swc1 $f18, 18*4(%0) \n" |
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| 353 | "swc1 $f19, 19*4(%0) \n" |
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| 354 | "swc1 $f20, 20*4(%0) \n" |
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| 355 | "swc1 $f21, 21*4(%0) \n" |
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| 356 | "swc1 $f22, 22*4(%0) \n" |
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| 357 | "swc1 $f23, 23*4(%0) \n" |
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| 358 | "swc1 $f24, 24*4(%0) \n" |
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| 359 | "swc1 $f25, 25*4(%0) \n" |
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| 360 | "swc1 $f26, 26*4(%0) \n" |
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| 361 | "swc1 $f27, 27*4(%0) \n" |
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| 362 | "swc1 $f28, 28*4(%0) \n" |
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| 363 | "swc1 $f29, 29*4(%0) \n" |
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| 364 | "swc1 $f30, 30*4(%0) \n" |
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| 365 | "swc1 $f31, 31*4(%0) \n" |
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| 366 | ".set reorder \n" |
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| 367 | : : "r"(ctx) ); |
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| 368 | |
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| 369 | } // end hal_cpu_context_save() |
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| 370 | |
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| 371 | ///////////////////////////////////////////////// |
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| 372 | void hal_fpu_context_restore( thread_t * thread ) |
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| 373 | { |
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| 374 | uint32_t ctx = (uint32_t)thread->fpu_context; |
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| 375 | |
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| 376 | asm volatile( |
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| 377 | ".set noreorder \n" |
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| 378 | "lwc1 $f0, 0*4(%0) \n" |
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| 379 | "lwc1 $f1, 1*4(%0) \n" |
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| 380 | "lwc1 $f2, 2*4(%0) \n" |
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| 381 | "lwc1 $f3, 3*4(%0) \n" |
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| 382 | "lwc1 $f4, 4*4(%0) \n" |
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| 383 | "lwc1 $f5, 5*4(%0) \n" |
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| 384 | "lwc1 $f6, 6*4(%0) \n" |
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| 385 | "lwc1 $f7, 7*4(%0) \n" |
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| 386 | "lwc1 $f8, 8*4(%0) \n" |
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| 387 | "lwc1 $f9, 9*4(%0) \n" |
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| 388 | "lwc1 $f10, 10*4(%0) \n" |
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| 389 | "lwc1 $f11, 11*4(%0) \n" |
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| 390 | "lwc1 $f12, 12*4(%0) \n" |
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| 391 | "lwc1 $f13, 13*4(%0) \n" |
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| 392 | "lwc1 $f14, 14*4(%0) \n" |
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| 393 | "lwc1 $f15, 15*4(%0) \n" |
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| 394 | "lwc1 $f16, 16*4(%0) \n" |
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| 395 | "lwc1 $f17, 17*4(%0) \n" |
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| 396 | "lwc1 $f18, 18*4(%0) \n" |
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| 397 | "lwc1 $f19, 19*4(%0) \n" |
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| 398 | "lwc1 $f20, 20*4(%0) \n" |
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| 399 | "lwc1 $f21, 21*4(%0) \n" |
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| 400 | "lwc1 $f22, 22*4(%0) \n" |
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| 401 | "lwc1 $f23, 23*4(%0) \n" |
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| 402 | "lwc1 $f24, 24*4(%0) \n" |
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| 403 | "lwc1 $f25, 25*4(%0) \n" |
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| 404 | "lwc1 $f26, 26*4(%0) \n" |
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| 405 | "lwc1 $f27, 27*4(%0) \n" |
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| 406 | "lwc1 $f28, 28*4(%0) \n" |
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| 407 | "lwc1 $f29, 29*4(%0) \n" |
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| 408 | "lwc1 $f30, 30*4(%0) \n" |
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| 409 | "lwc1 $f31, 31*4(%0) \n" |
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| 410 | ".set reorder \n" |
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| 411 | : : "r"(ctx) ); |
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| 412 | |
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| 413 | } // end hal_cpu_context_restore() |
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| 414 | |
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| 415 | ///////////////////////////////////// |
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| 416 | void hal_fpu_context_dup( xptr_t dst, |
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| 417 | xptr_t src ) |
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| 418 | { |
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| 419 | hal_remote_memcpy( dst , src , sizeof(hal_fpu_context_t) ); |
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| 420 | } |
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| 421 | |
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