[1] | 1 | /* |
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| 2 | * hal_gpt.c - implementation of the Generic Page Table API for TSAR-MIPS32 |
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| 3 | * |
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| 4 | * Author Alain Greiner (2016) |
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| 5 | * |
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| 6 | * Copyright (c) UPMC Sorbonne Universites |
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| 7 | * |
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| 8 | * This file is part of ALMOS-MKH. |
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| 9 | * |
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| 10 | * ALMOS-MKH.is free software; you can redistribute it and/or modify it |
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| 11 | * under the terms of the GNU General Public License as published by |
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| 12 | * the Free Software Foundation; version 2.0 of the License. |
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| 13 | * |
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| 14 | * ALMOS-MKH.is distributed in the hope that it will be useful, but |
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| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 17 | * General Public License for more details. |
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| 18 | * |
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| 19 | * You should have received a copy of the GNU General Public License |
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| 20 | * along with ALMOS-MKH.; if not, write to the Free Software Foundation, |
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| 21 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 22 | */ |
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| 23 | |
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| 24 | #include <hal_types.h> |
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| 25 | #include <hal_gpt.h> |
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| 26 | #include <hal_special.h> |
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| 27 | #include <printk.h> |
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| 28 | #include <bits.h> |
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| 29 | #include <process.h> |
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| 30 | #include <kmem.h> |
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| 31 | #include <thread.h> |
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| 32 | #include <cluster.h> |
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| 33 | #include <ppm.h> |
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| 34 | #include <page.h> |
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| 35 | |
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| 36 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 37 | // This define the masks for the TSAR MMU PTE attributes. (from TSAR MMU specification) |
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| 38 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 39 | |
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| 40 | #define TSAR_MMU_PRESENT 0x80000000 |
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| 41 | #define TSAR_MMU_PTD1 0x40000000 |
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| 42 | #define TSAR_MMU_LOCAL 0x20000000 |
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| 43 | #define TSAR_MMU_REMOTE 0x10000000 |
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| 44 | #define TSAR_MMU_CACHABLE 0x08000000 |
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| 45 | #define TSAR_MMU_WRITABLE 0x04000000 |
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| 46 | #define TSAR_MMU_EXECUTABLE 0x02000000 |
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| 47 | #define TSAR_MMU_USER 0x01000000 |
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| 48 | #define TSAR_MMU_GLOBAL 0x00800000 |
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| 49 | #define TSAR_MMU_DIRTY 0x00400000 |
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| 50 | |
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| 51 | #define TSAR_MMU_COW 0x00000001 |
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| 52 | #define TSAR_MMU_SWAP 0x00000004 |
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| 53 | #define TSAR_MMU_LOCKED 0x00000008 |
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| 54 | |
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| 55 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 56 | // TSAR MMU related macros (from the TSAR MMU specification) |
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| 57 | // - IX1 on 11 bits |
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| 58 | // - IX2 on 9 bits |
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| 59 | // - PPN on 28 bits |
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| 60 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 61 | |
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| 62 | #define TSAR_MMU_IX1_WIDTH 11 |
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| 63 | #define TSAR_MMU_IX2_WIDTH 9 |
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| 64 | #define TSAR_MMU_PPN_WIDTH 28 |
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| 65 | |
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| 66 | #define TSAR_MMU_IX1_FROM_VPN( vpn ) ((vpn >> 9) & 0x7FF) |
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| 67 | #define TSAR_MMU_IX2_FROM_VPN( vpn ) (vpn & 0x1FF) |
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| 68 | |
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[315] | 69 | #define TSAR_MMU_PTBA_FROM_PTE1( pte1 ) (pte1 & 0x0FFFFFFF) |
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| 70 | #define TSAR_MMU_PPN_FROM_PTE1( pte1 ) ((pte1 & 0x0007FFFF)<<9) |
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[1] | 71 | #define TSAR_MMU_ATTR_FROM_PTE1( pte1 ) (pte1 & 0xFFC00000) |
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| 72 | |
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| 73 | #define TSAR_MMU_PPN_FROM_PTE2( pte2 ) (pte2 & 0x0FFFFFFF) |
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| 74 | #define TSAR_MMU_ATTR_FROM_PTE2( pte2 ) (pte2 & 0xFFC000FF) |
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| 75 | |
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| 76 | ///////////////////////////////////// |
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| 77 | error_t hal_gpt_create( gpt_t * gpt ) |
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| 78 | { |
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| 79 | page_t * page; |
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[315] | 80 | xptr_t page_xp; |
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[1] | 81 | |
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| 82 | // check page size |
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[50] | 83 | if( CONFIG_PPM_PAGE_SIZE != 4096 ) |
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[1] | 84 | { |
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| 85 | printk("\n[PANIC] in %s : For TSAR, the page must be 4 Kbytes\n", __FUNCTION__ ); |
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| 86 | hal_core_sleep(); |
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| 87 | } |
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| 88 | |
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| 89 | // allocates 2 physical pages for PT1 |
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| 90 | kmem_req_t req; |
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| 91 | req.type = KMEM_PAGE; |
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| 92 | req.size = 1; // 2 small pages |
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| 93 | req.flags = AF_KERNEL | AF_ZERO; |
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| 94 | page = (page_t *)kmem_alloc( &req ); |
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| 95 | |
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| 96 | if( page == NULL ) |
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| 97 | { |
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| 98 | printk("\n[ERROR] in %s : cannot allocate physical memory for PT1\n", __FUNCTION__ ); |
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| 99 | return ENOMEM; |
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| 100 | } |
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| 101 | |
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| 102 | // initialize generic page table descriptor |
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[315] | 103 | page_xp = XPTR( local_cxy , page ); |
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[1] | 104 | |
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[315] | 105 | gpt->ptr = GET_PTR( ppm_page2base( page_xp ) ); |
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| 106 | gpt->ppn = ppm_page2ppn( page_xp ); |
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| 107 | gpt->page = GET_PTR( page_xp ); |
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| 108 | |
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[391] | 109 | /* |
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[1] | 110 | // initialize PTE entries attributes masks |
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| 111 | GPT_MAPPED = TSAR_MMU_PRESENT; |
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| 112 | GPT_SMALL = TSAR_MMU_PTD1; |
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| 113 | GPT_READABLE = TSAR_MMU_PRESENT; |
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| 114 | GPT_WRITABLE = TSAR_MMU_WRITABLE; |
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| 115 | GPT_EXECUTABLE = TSAR_MMU_EXECUTABLE; |
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| 116 | GPT_CACHABLE = TSAR_MMU_CACHABLE; |
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| 117 | GPT_USER = TSAR_MMU_USER; |
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| 118 | GPT_DIRTY = TSAR_MMU_DIRTY; |
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| 119 | GPT_ACCESSED = TSAR_MMU_LOCAL | TSAR_MMU_REMOTE; |
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| 120 | GPT_GLOBAL = TSAR_MMU_GLOBAL; |
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| 121 | GPT_COW = TSAR_MMU_COW; |
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| 122 | GPT_SWAP = TSAR_MMU_SWAP; |
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| 123 | GPT_LOCKED = TSAR_MMU_LOCKED; |
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[391] | 124 | */ |
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[1] | 125 | return 0; |
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| 126 | } // end hal_gpt_create() |
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| 127 | |
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| 128 | |
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| 129 | /////////////////////////////////// |
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| 130 | void hal_gpt_destroy( gpt_t * gpt ) |
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| 131 | { |
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| 132 | uint32_t ix1; |
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| 133 | uint32_t ix2; |
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| 134 | uint32_t * pt1; |
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| 135 | uint32_t pte1; |
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| 136 | ppn_t pt2_ppn; |
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| 137 | uint32_t * pt2; |
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| 138 | uint32_t attr; |
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| 139 | vpn_t vpn; |
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| 140 | kmem_req_t req; |
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| 141 | bool_t is_ref; |
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| 142 | |
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| 143 | // get pointer on calling process |
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| 144 | process_t * process = CURRENT_THREAD->process; |
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| 145 | |
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| 146 | // compute is_ref |
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[23] | 147 | is_ref = ( GET_CXY( process->ref_xp ) == local_cxy ); |
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[1] | 148 | |
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| 149 | // get pointer on PT1 |
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| 150 | pt1 = (uint32_t *)gpt->ptr; |
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| 151 | |
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| 152 | // scan the PT1 |
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| 153 | for( ix1 = 0 ; ix1 < 2048 ; ix1++ ) |
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| 154 | { |
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| 155 | pte1 = pt1[ix1]; |
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[391] | 156 | if( (pte1 & TSAR_MMU_PRESENT) != 0 ) // PTE1 valid |
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[1] | 157 | { |
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[391] | 158 | if( (pte1 & TSAR_MMU_PTD1) == 0 ) // BIG page |
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[1] | 159 | { |
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[391] | 160 | if( (pte1 & TSAR_MMU_USER) != 0 ) |
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[1] | 161 | { |
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| 162 | // warning message |
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| 163 | printk("\n[WARNING] in %s : found an USER BIG page / ix1 = %d\n", |
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[391] | 164 | __FUNCTION__ , ix1 ); |
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[1] | 165 | |
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| 166 | // release the big physical page if reference cluster |
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| 167 | if( is_ref ) |
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| 168 | { |
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| 169 | vpn = (vpn_t)(ix1 << TSAR_MMU_IX2_WIDTH); |
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| 170 | hal_gpt_reset_pte( gpt , vpn ); |
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| 171 | } |
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| 172 | } |
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| 173 | } |
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[391] | 174 | else // SMALL page |
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[1] | 175 | { |
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[315] | 176 | // get local pointer on PT2 |
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[1] | 177 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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[315] | 178 | xptr_t base_xp = ppm_ppn2base( pt2_ppn ); |
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| 179 | pt2 = (uint32_t *)GET_PTR( base_xp ); |
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[1] | 180 | |
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| 181 | // scan the PT2 to release all entries VALID and USER if reference cluster |
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| 182 | if( is_ref ) |
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| 183 | { |
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| 184 | for( ix2 = 0 ; ix2 < 512 ; ix2++ ) |
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| 185 | { |
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| 186 | attr = TSAR_MMU_ATTR_FROM_PTE2( pt2[2 * ix2] ); |
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[391] | 187 | if( ((attr & TSAR_MMU_PRESENT) != 0 ) && ((attr & TSAR_MMU_USER) != 0) ) |
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[1] | 188 | { |
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| 189 | // release the physical page |
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| 190 | vpn = (vpn_t)((ix1 << TSAR_MMU_IX2_WIDTH) | ix2); |
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| 191 | hal_gpt_reset_pte( gpt , vpn ); |
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| 192 | } |
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| 193 | } |
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| 194 | } |
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| 195 | |
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| 196 | // release the PT2 |
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| 197 | req.type = KMEM_PAGE; |
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[315] | 198 | req.ptr = GET_PTR( ppm_base2page( XPTR(local_cxy , pt2 ) ) ); |
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[1] | 199 | kmem_free( &req ); |
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| 200 | } |
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| 201 | } |
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| 202 | } |
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| 203 | |
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| 204 | // release the PT1 |
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| 205 | req.type = KMEM_PAGE; |
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[315] | 206 | req.ptr = GET_PTR( ppm_base2page( XPTR(local_cxy , pt1 ) ) ); |
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[1] | 207 | kmem_free( &req ); |
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| 208 | |
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| 209 | } // end hal_gpt_destroy() |
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| 210 | |
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| 211 | ///////////////////////////////// |
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| 212 | void hal_gpt_print( gpt_t * gpt ) |
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| 213 | { |
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| 214 | uint32_t ix1; |
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| 215 | uint32_t ix2; |
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| 216 | uint32_t * pt1; |
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| 217 | uint32_t pte1; |
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| 218 | ppn_t pt2_ppn; |
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| 219 | uint32_t * pt2; |
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| 220 | uint32_t pte2_attr; |
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| 221 | ppn_t pte2_ppn; |
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| 222 | |
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| 223 | printk("*** Page Table for process %x in cluster %x ***\n", |
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[23] | 224 | CURRENT_THREAD->process->pid , local_cxy ); |
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[1] | 225 | |
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| 226 | pt1 = (uint32_t *)gpt->ptr; |
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| 227 | |
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| 228 | // scan the PT1 |
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| 229 | for( ix1 = 0 ; ix1 < 2048 ; ix1++ ) |
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| 230 | { |
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| 231 | pte1 = pt1[ix1]; |
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[391] | 232 | if( (pte1 & TSAR_MMU_PRESENT) != 0 ) |
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[1] | 233 | { |
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[391] | 234 | if( (pte1 & TSAR_MMU_PTD1) == 0 ) // BIG page |
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[1] | 235 | { |
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| 236 | printk(" - BIG : pt1[%d] = %x\n", ix1 , pte1 ); |
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| 237 | } |
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| 238 | else // SMALL pages |
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| 239 | { |
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| 240 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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[315] | 241 | xptr_t base_xp = ppm_ppn2base ( pt2_ppn ); |
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| 242 | pt2 = (uint32_t *)GET_PTR( base_xp ); |
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[1] | 243 | |
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| 244 | // scan the PT2 |
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| 245 | for( ix2 = 0 ; ix2 < 512 ; ix2++ ) |
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| 246 | { |
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| 247 | pte2_attr = TSAR_MMU_ATTR_FROM_PTE2( pt2[2 * ix2] ); |
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| 248 | pte2_ppn = TSAR_MMU_PPN_FROM_PTE2( pt2[2 * ix2 + 1] ); |
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[391] | 249 | if( (pte2_attr & TSAR_MMU_PRESENT) != 0 ) |
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[1] | 250 | { |
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| 251 | printk(" - SMALL : pt1[%d] = %x / pt2[%d] / pt2[%d]\n", |
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| 252 | ix1 , pt1[ix1] , 2*ix2 , pte2_attr , 2*ix2+1 , pte2_ppn ); |
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| 253 | } |
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| 254 | } |
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| 255 | } |
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| 256 | } |
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| 257 | } |
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| 258 | } // end hal_gpt_print() |
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| 259 | |
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| 260 | |
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| 261 | /////////////////////////////////////// |
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| 262 | error_t hal_gpt_set_pte( gpt_t * gpt, |
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| 263 | vpn_t vpn, |
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| 264 | ppn_t ppn, |
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| 265 | uint32_t attr ) |
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| 266 | { |
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| 267 | uint32_t * pt1; // virtual base addres of PT1 |
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| 268 | volatile uint32_t * pte1_ptr; // pointer on PT1 entry |
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| 269 | uint32_t pte1; // PT1 entry value |
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| 270 | |
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| 271 | ppn_t pt2_ppn; // PPN of PT2 |
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| 272 | uint32_t * pt2; // virtual base address of PT2 |
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| 273 | |
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| 274 | uint32_t small; // requested PTE is for a small page |
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[315] | 275 | bool_t atomic; |
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| 276 | |
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[1] | 277 | page_t * page; // pointer on new physical page descriptor |
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[315] | 278 | xptr_t page_xp; // extended pointer on new page descriptor |
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[1] | 279 | |
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| 280 | uint32_t ix1; // index in PT1 |
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| 281 | uint32_t ix2; // index in PT2 |
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| 282 | |
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| 283 | // compute indexes in PT1 and PT2 |
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| 284 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
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| 285 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
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| 286 | |
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| 287 | pt1 = gpt->ptr; |
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[391] | 288 | small = (attr & TSAR_MMU_PTD1); |
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[1] | 289 | |
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| 290 | // get PT1 entry value |
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| 291 | pte1_ptr = &pt1[ix1]; |
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| 292 | pte1 = *pte1_ptr; |
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| 293 | |
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| 294 | // Big pages (PTE1) are only set for the kernel vsegs, in the kernel init phase. |
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| 295 | // There is no risk of concurrent access. |
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| 296 | if( small == 0 ) |
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| 297 | { |
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| 298 | if( (pte1 != 0) || (attr & GPT_COW) ) |
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| 299 | { |
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| 300 | printk("\n[ERROR] in %s : set a big page in a mapped PT1 entry / PT1[%d] = %x\n", |
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| 301 | __FUNCTION__ , ix1 , pte1 ); |
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| 302 | return EINVAL; |
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| 303 | } |
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| 304 | |
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| 305 | // set the PTE1 |
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| 306 | *pte1_ptr = attr | (ppn >> 9); |
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[124] | 307 | hal_fence(); |
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[1] | 308 | return 0; |
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| 309 | } |
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| 310 | |
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| 311 | // From this point, the requested PTE is a PTE2 (small page) |
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| 312 | |
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[391] | 313 | if( (pte1 & TSAR_MMU_PRESENT) == 0 ) // the PT1 entry is not valid |
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[1] | 314 | { |
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| 315 | // allocate one physical page for the PT2 |
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| 316 | kmem_req_t req; |
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| 317 | req.type = KMEM_PAGE; |
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| 318 | req.size = 0; // 1 small page |
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| 319 | req.flags = AF_KERNEL | AF_ZERO; |
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| 320 | page = (page_t *)kmem_alloc( &req ); |
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| 321 | if( page == NULL ) |
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| 322 | { |
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| 323 | printk("\n[ERROR] in %s : try to set a small page but cannot allocate PT2\n", |
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| 324 | __FUNCTION__ ); |
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| 325 | return ENOMEM; |
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| 326 | } |
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| 327 | |
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[315] | 328 | page_xp = XPTR( local_cxy , page ); |
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| 329 | pt2_ppn = ppm_page2ppn( page_xp ); |
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| 330 | pt2 = (uint32_t *)GET_PTR( ppm_page2base( page_xp ) ); |
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| 331 | |
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[1] | 332 | // try to atomicaly set a PTD1 in the PT1 entry |
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| 333 | do |
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| 334 | { |
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| 335 | atomic = hal_atomic_cas( (void*)pte1, 0 , |
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| 336 | TSAR_MMU_PRESENT | TSAR_MMU_PTD1 | pt2_ppn ); |
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| 337 | } |
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| 338 | while( (atomic == false) && (*pte1_ptr == 0) ); |
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| 339 | |
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| 340 | if( atomic == false ) // the mapping has been done by another thread !!! |
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| 341 | { |
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| 342 | // release the allocated page |
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| 343 | ppm_free_pages( page ); |
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| 344 | |
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| 345 | // read PT1 entry again |
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| 346 | pte1 = *pte1_ptr; |
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| 347 | |
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| 348 | // compute PPN of PT2 base |
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| 349 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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| 350 | |
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| 351 | // compute pointer on PT2 base |
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[315] | 352 | pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
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[1] | 353 | } |
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| 354 | } |
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| 355 | else // The PT1 entry is valid |
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| 356 | { |
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| 357 | // This valid entry must be a PTD1 |
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[391] | 358 | if( (pte1 & TSAR_MMU_PTD1) == 0 ) |
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[1] | 359 | { |
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| 360 | printk("\n[ERROR] in %s : set a small page in a big PT1 entry / PT1[%d] = %x\n", |
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| 361 | __FUNCTION__ , ix1 , pte1 ); |
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| 362 | return EINVAL; |
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| 363 | } |
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| 364 | |
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| 365 | // compute PPN of PT2 base |
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| 366 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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| 367 | |
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| 368 | // compute pointer on PT2 base |
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[315] | 369 | pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
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[1] | 370 | } |
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| 371 | |
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| 372 | // set PTE2 in this order |
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| 373 | pt2[2 * ix2 + 1] = ppn; |
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[124] | 374 | hal_fence(); |
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[1] | 375 | pt2[2 * ix2] = attr; |
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[124] | 376 | hal_fence(); |
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[1] | 377 | |
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| 378 | return 0; |
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| 379 | } // end of hal_gpt_set_pte() |
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| 380 | |
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| 381 | ///////////////////////////////////// |
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| 382 | void hal_gpt_get_pte( gpt_t * gpt, |
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| 383 | vpn_t vpn, |
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| 384 | uint32_t * attr, |
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| 385 | ppn_t * ppn ) |
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| 386 | { |
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| 387 | uint32_t * pt1; |
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| 388 | uint32_t pte1; |
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| 389 | |
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| 390 | uint32_t * pt2; |
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| 391 | ppn_t pt2_ppn; |
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| 392 | |
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| 393 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
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| 394 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
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| 395 | |
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| 396 | // get PTE1 value |
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| 397 | pt1 = gpt->ptr; |
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| 398 | pte1 = pt1[ix1]; |
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| 399 | |
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[391] | 400 | if( (pte1 & TSAR_MMU_PRESENT) == 0 ) // PT1 entry not present |
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[1] | 401 | { |
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| 402 | *attr = 0; |
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| 403 | *ppn = 0; |
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| 404 | } |
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| 405 | |
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[391] | 406 | if( (pte1 & TSAR_MMU_PTD1) == 0 ) // it's a PTE1 |
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[1] | 407 | { |
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| 408 | *attr = TSAR_MMU_ATTR_FROM_PTE1( pte1 ); |
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| 409 | *ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ) | (vpn & ((1<<TSAR_MMU_IX2_WIDTH)-1)); |
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| 410 | } |
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| 411 | else // it's a PTD1 |
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| 412 | { |
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| 413 | // compute PT2 base address |
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| 414 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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[315] | 415 | pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
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[1] | 416 | |
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| 417 | *ppn = pt2[2*ix2+1] & ((1<<TSAR_MMU_PPN_WIDTH)-1); |
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| 418 | *attr = pt2[2*ix2]; |
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| 419 | } |
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| 420 | } // end hal_gpt_get_pte() |
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| 421 | |
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| 422 | //////////////////////////////////// |
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| 423 | void hal_gpt_reset_pte( gpt_t * gpt, |
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| 424 | vpn_t vpn ) |
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| 425 | { |
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| 426 | uint32_t * pt1; // PT1 base address |
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| 427 | uint32_t pte1; // PT1 entry value |
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| 428 | |
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| 429 | ppn_t pt2_ppn; // PPN of PT2 |
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| 430 | uint32_t * pt2; // PT2 base address |
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| 431 | |
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| 432 | ppn_t ppn; // PPN of page to be released |
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| 433 | |
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| 434 | kmem_req_t req; |
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| 435 | |
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[391] | 436 | // get ix1 & ix2 indexes |
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[1] | 437 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
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| 438 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
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| 439 | |
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[391] | 440 | // get pointer on calling process |
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| 441 | process_t * process = CURRENT_THREAD->process; |
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| 442 | |
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| 443 | // compute is_ref |
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| 444 | bool_t is_ref = ( GET_CXY( process->ref_xp ) == local_cxy ); |
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| 445 | |
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[1] | 446 | // get PTE1 value |
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| 447 | pt1 = gpt->ptr; |
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| 448 | pte1 = pt1[ix1]; |
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| 449 | |
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[391] | 450 | if( (pte1 & TSAR_MMU_PRESENT) == 0 ) // PT1 entry not present |
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[1] | 451 | { |
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| 452 | return; |
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| 453 | } |
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| 454 | |
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[391] | 455 | if( (pte1 & TSAR_MMU_PTD1) == 0 ) // it's a PTE1 |
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[1] | 456 | { |
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| 457 | // get PPN |
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| 458 | ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ); |
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| 459 | |
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| 460 | // unmap the big page |
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| 461 | pt1[ix1] = 0; |
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[124] | 462 | hal_fence(); |
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[1] | 463 | |
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[391] | 464 | // releases the physical page if local |
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| 465 | // req.type = KMEM_PAGE; |
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| 466 | // req.size = 9; |
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| 467 | // req.ptr = (void*)(ppn << CONFIG_PPM_PAGE_SHIFT); |
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| 468 | // kmem_free( &req ); |
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[1] | 469 | |
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| 470 | return; |
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| 471 | } |
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[391] | 472 | else // it's a PTD1 |
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[1] | 473 | { |
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| 474 | // compute PT2 base address |
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| 475 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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[315] | 476 | pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
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[1] | 477 | |
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| 478 | // get PPN |
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| 479 | ppn = TSAR_MMU_PPN_FROM_PTE2( pt2[2*ix2+1] ); |
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| 480 | |
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| 481 | // unmap the small page |
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[391] | 482 | pt2[2*ix2] = 0; // only attr is reset |
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| 483 | hal_fence(); |
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[1] | 484 | |
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[391] | 485 | // releases the small page |
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| 486 | // req.type = KMEM_PAGE; |
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| 487 | // req.size = 0; |
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| 488 | // req.ptr = (void*)(ppn << CONFIG_PPM_PAGE_SHIFT); |
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| 489 | // kmem_free( &req ); |
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[1] | 490 | |
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| 491 | return; |
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| 492 | } |
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| 493 | } // end hal_gpt_reset_pte() |
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| 494 | |
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| 495 | ////////////////////////////////////// |
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| 496 | error_t hal_gpt_lock_pte( gpt_t * gpt, |
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| 497 | vpn_t vpn ) |
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| 498 | { |
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| 499 | uint32_t * pt1; // PT1 base address |
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| 500 | volatile uint32_t * pte1_ptr; // address of PT1 entry |
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| 501 | uint32_t pte1; // value of PT1 entry |
---|
| 502 | |
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| 503 | uint32_t * pt2; // PT2 base address |
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| 504 | ppn_t pt2_ppn; // PPN of PT2 page if missing PT2 |
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| 505 | volatile uint32_t * pte2_ptr; // address of PT2 entry |
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| 506 | |
---|
| 507 | uint32_t attr; |
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| 508 | bool_t atomic; |
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| 509 | page_t * page; |
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[315] | 510 | xptr_t page_xp; |
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[1] | 511 | |
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| 512 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); // index in PT1 |
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| 513 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); // index in PT2 |
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| 514 | |
---|
| 515 | // get the PTE1 value |
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| 516 | pt1 = gpt->ptr; |
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| 517 | pte1_ptr = &pt1[ix1]; |
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| 518 | pte1 = *pte1_ptr; |
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| 519 | |
---|
| 520 | // If present, the page must be small |
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[391] | 521 | if( ((pte1 & TSAR_MMU_PRESENT) != 0) && ((pte1 & TSAR_MMU_PTD1) == 0) ) |
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[1] | 522 | { |
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| 523 | printk("\n[ERROR] in %s : try to lock a big page / PT1[%d] = %x\n", |
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| 524 | __FUNCTION__ , ix1 , pte1 ); |
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| 525 | return EINVAL; |
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| 526 | } |
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| 527 | |
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[391] | 528 | if( (pte1 & TSAR_MMU_PRESENT) == 0 ) // missing PT1 entry |
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[1] | 529 | { |
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| 530 | // allocate one physical page for PT2 |
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| 531 | kmem_req_t req; |
---|
| 532 | req.type = KMEM_PAGE; |
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| 533 | req.size = 0; // 1 small page |
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| 534 | req.flags = AF_KERNEL | AF_ZERO; |
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| 535 | page = (page_t *)kmem_alloc( &req ); |
---|
[23] | 536 | |
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[1] | 537 | if( page == NULL ) |
---|
| 538 | { |
---|
| 539 | printk("\n[ERROR] in %s : try to set a small page but cannot allocate PT2\n", |
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| 540 | __FUNCTION__ ); |
---|
| 541 | return ENOMEM; |
---|
| 542 | } |
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[23] | 543 | |
---|
[315] | 544 | page_xp = XPTR( local_cxy , page ); |
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| 545 | pt2_ppn = ppm_page2ppn( page_xp ); |
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| 546 | pt2 = (uint32_t *)GET_PTR( ppm_page2base( page_xp ) ); |
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[1] | 547 | |
---|
| 548 | // try to set the PT1 entry |
---|
| 549 | do |
---|
| 550 | { |
---|
| 551 | atomic = hal_atomic_cas( (void*)pte1_ptr , 0 , |
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| 552 | TSAR_MMU_PRESENT | TSAR_MMU_PTD1 | pt2_ppn ); |
---|
| 553 | } |
---|
| 554 | while( (atomic == false) && (*pte1_ptr == 0) ); |
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| 555 | |
---|
| 556 | if( atomic == false ) // missing PT2 has been allocate by another core |
---|
| 557 | { |
---|
| 558 | // release the allocated page |
---|
| 559 | ppm_free_pages( page ); |
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| 560 | |
---|
| 561 | // read again the PTE1 |
---|
| 562 | pte1 = *pte1_ptr; |
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| 563 | |
---|
| 564 | // get the PT2 base address |
---|
| 565 | pt2_ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ); |
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[315] | 566 | pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
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[1] | 567 | } |
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| 568 | } |
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| 569 | else |
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| 570 | { |
---|
| 571 | // This valid entry must be a PTD1 |
---|
[391] | 572 | if( (pte1 & TSAR_MMU_PTD1) == 0 ) |
---|
[1] | 573 | { |
---|
| 574 | printk("\n[ERROR] in %s : set a small page in a big PT1 entry / PT1[%d] = %x\n", |
---|
| 575 | __FUNCTION__ , ix1 , pte1 ); |
---|
| 576 | return EINVAL; |
---|
| 577 | } |
---|
| 578 | |
---|
| 579 | // compute PPN of PT2 base |
---|
| 580 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
| 581 | |
---|
| 582 | // compute pointer on PT2 base |
---|
[315] | 583 | pt2 = (uint32_t *)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[1] | 584 | } |
---|
| 585 | |
---|
| 586 | // from here we have the PT2 pointer |
---|
| 587 | |
---|
| 588 | // compute pointer on PTE2 |
---|
| 589 | pte2_ptr = &pt2[2 * ix2]; |
---|
| 590 | |
---|
| 591 | // try to atomically lock the PTE2 until success |
---|
| 592 | do |
---|
| 593 | { |
---|
| 594 | // busy waiting until GPT_LOCK == 0 |
---|
| 595 | do |
---|
| 596 | { |
---|
| 597 | attr = *pte2_ptr; |
---|
| 598 | hal_rdbar(); |
---|
| 599 | } |
---|
| 600 | while( (attr & GPT_LOCKED) != 0 ); |
---|
| 601 | |
---|
| 602 | // try to set the GPT_LOCK wit a CAS |
---|
| 603 | atomic = hal_atomic_cas( (void*)pte2_ptr, attr , (attr | GPT_LOCKED) ); |
---|
| 604 | } |
---|
| 605 | while( atomic == 0 ); |
---|
| 606 | |
---|
| 607 | return 0; |
---|
| 608 | } // end hal_gpt_lock_pte() |
---|
| 609 | |
---|
| 610 | //////////////////////////////////////// |
---|
| 611 | error_t hal_gpt_unlock_pte( gpt_t * gpt, |
---|
| 612 | vpn_t vpn ) |
---|
| 613 | { |
---|
| 614 | uint32_t * pt1; // PT1 base address |
---|
| 615 | uint32_t pte1; // value of PT1 entry |
---|
| 616 | |
---|
| 617 | uint32_t * pt2; // PT2 base address |
---|
| 618 | ppn_t pt2_ppn; // PPN of PT2 page if missing PT2 |
---|
| 619 | uint32_t * pte2_ptr; // address of PT2 entry |
---|
| 620 | |
---|
| 621 | uint32_t attr; // PTE2 attribute |
---|
| 622 | |
---|
| 623 | // compute indexes in P1 and PT2 |
---|
| 624 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); // index in PT1 |
---|
| 625 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); // index in PT2 |
---|
| 626 | |
---|
| 627 | // get pointer on PT1 base |
---|
| 628 | pt1 = (uint32_t*)gpt->ptr; |
---|
| 629 | |
---|
| 630 | // get PTE1 |
---|
| 631 | pte1 = pt1[ix1]; |
---|
| 632 | |
---|
| 633 | // check PTE1 present and small page |
---|
[391] | 634 | if( ((pte1 & TSAR_MMU_PRESENT) == 0) || ((pte1 & TSAR_MMU_PTD1) == 0) ) |
---|
[1] | 635 | { |
---|
| 636 | printk("\n[ERROR] in %s : try to unlock a big or undefined page / PT1[%d] = %x\n", |
---|
| 637 | __FUNCTION__ , ix1 , pte1 ); |
---|
| 638 | return EINVAL; |
---|
| 639 | } |
---|
| 640 | |
---|
| 641 | // get pointer on PT2 base |
---|
| 642 | pt2_ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ); |
---|
[315] | 643 | pt2 = (uint32_t *)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[1] | 644 | |
---|
| 645 | // get pointer on PTE2 |
---|
| 646 | pte2_ptr = &pt2[2 * ix2]; |
---|
| 647 | |
---|
| 648 | // get PTE2_ATTR |
---|
| 649 | attr = *pte2_ptr; |
---|
| 650 | |
---|
| 651 | // check PTE2 present and locked |
---|
[391] | 652 | if( ((attr & TSAR_MMU_PRESENT) == 0) || ((attr & GPT_LOCKED) == 0) ); |
---|
[1] | 653 | { |
---|
| 654 | printk("\n[ERROR] in %s : try to unlock an undefined page / PT1[%d] = %x\n", |
---|
| 655 | __FUNCTION__ , ix1 , pte1 ); |
---|
| 656 | return EINVAL; |
---|
| 657 | } |
---|
| 658 | |
---|
| 659 | // reset GPT_LOCK |
---|
| 660 | *pte2_ptr = attr & !GPT_LOCKED; |
---|
| 661 | |
---|
| 662 | return 0; |
---|
| 663 | } // end hal_gpt_unlock_pte() |
---|
| 664 | |
---|
[23] | 665 | /////////////////////////////////////// |
---|
| 666 | error_t hal_gpt_copy( gpt_t * dst_gpt, |
---|
| 667 | gpt_t * src_gpt, |
---|
| 668 | bool_t cow ) |
---|
| 669 | { |
---|
| 670 | uint32_t ix1; // index in PT1 |
---|
| 671 | uint32_t ix2; // index in PT2 |
---|
[1] | 672 | |
---|
[23] | 673 | uint32_t * src_pt1; // local pointer on PT1 for SRC_GPT |
---|
| 674 | uint32_t * dst_pt1; // local pointer on PT1 for DST_GPT |
---|
| 675 | uint32_t * dst_pt2; // local pointer on PT2 for DST_GPT |
---|
| 676 | uint32_t * src_pt2; // local pointer on PT2 for SRC_GPT |
---|
[1] | 677 | |
---|
[23] | 678 | uint32_t pte1; |
---|
| 679 | uint32_t pte2_attr; |
---|
| 680 | uint32_t pte2_ppn; |
---|
| 681 | uint32_t pte2_writable; |
---|
[1] | 682 | |
---|
[23] | 683 | page_t * page; |
---|
[315] | 684 | xptr_t page_xp; |
---|
[1] | 685 | |
---|
[23] | 686 | ppn_t src_pt2_ppn; |
---|
| 687 | ppn_t dst_pt2_ppn; |
---|
[1] | 688 | |
---|
[23] | 689 | // get pointers on PT1 for src_gpt & dst_gpt |
---|
| 690 | src_pt1 = (uint32_t *)src_gpt->ptr; |
---|
| 691 | dst_pt1 = (uint32_t *)dst_gpt->ptr; |
---|
[1] | 692 | |
---|
[23] | 693 | // scan the SRC_PT1 |
---|
| 694 | for( ix1 = 0 ; ix1 < 2048 ; ix1++ ) |
---|
| 695 | { |
---|
| 696 | pte1 = src_pt1[ix1]; |
---|
[391] | 697 | if( (pte1 & TSAR_MMU_PRESENT) != 0 ) |
---|
[23] | 698 | { |
---|
[391] | 699 | if( (pte1 & TSAR_MMU_PTD1) == 0 ) // PTE1 => big kernel page |
---|
[23] | 700 | { |
---|
| 701 | // big kernel pages are shared by all processes => copy it |
---|
| 702 | dst_pt1[ix1] = pte1; |
---|
| 703 | } |
---|
| 704 | else // PTD1 => smal pages |
---|
| 705 | { |
---|
| 706 | // allocate one physical page for a PT2 in DST_GPT |
---|
| 707 | kmem_req_t req; |
---|
| 708 | req.type = KMEM_PAGE; |
---|
| 709 | req.size = 0; // 1 small page |
---|
| 710 | req.flags = AF_KERNEL | AF_ZERO; |
---|
| 711 | page = (page_t *)kmem_alloc( &req ); |
---|
[1] | 712 | |
---|
[23] | 713 | if( page == NULL ) |
---|
| 714 | { |
---|
| 715 | // TODO release all memory allocated to DST_GPT |
---|
| 716 | printk("\n[ERROR] in %s : cannot allocate PT2\n", __FUNCTION__ ); |
---|
| 717 | return ENOMEM; |
---|
| 718 | } |
---|
| 719 | |
---|
[315] | 720 | // get extended pointer on page descriptor |
---|
| 721 | page_xp = XPTR( local_cxy , page ); |
---|
| 722 | |
---|
[23] | 723 | // get pointer on new PT2 in DST_GPT |
---|
[315] | 724 | xptr_t base_xp = ppm_page2base( page_xp ); |
---|
| 725 | dst_pt2 = (uint32_t *)GET_PTR( base_xp ); |
---|
[23] | 726 | |
---|
| 727 | // set a new PTD1 in DST_GPT |
---|
[315] | 728 | dst_pt2_ppn = (ppn_t)ppm_page2ppn( page_xp ); |
---|
[23] | 729 | dst_pt1[ix1] = TSAR_MMU_PRESENT | TSAR_MMU_PTD1 | dst_pt2_ppn; |
---|
| 730 | |
---|
| 731 | // get pointer on PT2 in SRC_GPT |
---|
| 732 | src_pt2_ppn = (ppn_t)TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
[315] | 733 | src_pt2 = (uint32_t *)GET_PTR( ppm_ppn2base( src_pt2_ppn ) ); |
---|
[23] | 734 | |
---|
| 735 | // scan the SRC_PT2 |
---|
| 736 | for( ix2 = 0 ; ix2 < 512 ; ix2++ ) |
---|
| 737 | { |
---|
| 738 | // get attr & ppn from PTE2 |
---|
| 739 | pte2_attr = TSAR_MMU_ATTR_FROM_PTE2( src_pt2[2 * ix2] ); |
---|
| 740 | |
---|
[391] | 741 | if( (pte2_attr & TSAR_MMU_PRESENT) != 0 ) // valid PTE2 in SRC_GPT |
---|
[23] | 742 | { |
---|
| 743 | // get GPT_WRITABLE & PPN |
---|
| 744 | pte2_writable = pte2_attr & GPT_WRITABLE; |
---|
| 745 | pte2_ppn = TSAR_MMU_PPN_FROM_PTE2( src_pt2[2 * ix2 + 1] ); |
---|
| 746 | |
---|
| 747 | // set a new PTE2 in DST_GPT |
---|
| 748 | dst_pt2[2*ix2] = pte2_attr; |
---|
| 749 | dst_pt2[2*ix2 + 1] = pte2_ppn; |
---|
| 750 | |
---|
| 751 | // handle Copy-On-Write |
---|
| 752 | if( cow && pte2_writable ) |
---|
| 753 | { |
---|
| 754 | // reset GPT_WRITABLE in both SRC_GPT and DST_GPT |
---|
| 755 | hal_atomic_and( &dst_pt2[2*ix2] , ~GPT_WRITABLE ); |
---|
| 756 | hal_atomic_and( &src_pt2[2*ix2] , ~GPT_WRITABLE ); |
---|
| 757 | |
---|
| 758 | // register PG_COW in page descriptor |
---|
[315] | 759 | page = (page_t *)GET_PTR( ppm_ppn2page( pte2_ppn ) ); |
---|
[23] | 760 | hal_atomic_or( &page->flags , PG_COW ); |
---|
| 761 | hal_atomic_add( &page->fork_nr , 1 ); |
---|
| 762 | } |
---|
| 763 | } |
---|
| 764 | } // end loop on ix2 |
---|
| 765 | } |
---|
| 766 | } |
---|
| 767 | } // end loop ix1 |
---|
| 768 | |
---|
[124] | 769 | hal_fence(); |
---|
[23] | 770 | |
---|
| 771 | return 0; |
---|
| 772 | |
---|
| 773 | } // end hal_gpt_copy() |
---|
| 774 | |
---|