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source: trunk/hal/tsar_mips32/core/hal_gpt.c @ 407

Last change on this file since 407 was 407, checked in by alain, 6 years ago
First implementation of fork/exec.
File size: 31.8 KB

Rev	Line
[1]	1	/*
	2	* hal_gpt.c - implementation of the Generic Page Table API for TSAR-MIPS32
	3	*
	4	* Author Alain Greiner (2016)
	5	*
	6	* Copyright (c) UPMC Sorbonne Universites
	7	*
	8	* This file is part of ALMOS-MKH.
	9	*
	10	* ALMOS-MKH.is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2.0 of the License.
	13	*
	14	* ALMOS-MKH.is distributed in the hope that it will be useful, but
	15	* WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	17	* General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with ALMOS-MKH.; if not, write to the Free Software Foundation,
	21	* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	22	*/
	23
	24	#include <hal_types.h>
	25	#include <hal_gpt.h>
	26	#include <hal_special.h>
	27	#include <printk.h>
	28	#include <bits.h>
	29	#include <process.h>
	30	#include <kmem.h>
	31	#include <thread.h>
	32	#include <cluster.h>
	33	#include <ppm.h>
	34	#include <page.h>
	35
	36	////////////////////////////////////////////////////////////////////////////////////////
[401]	37	// This define the masks for the TSAR MMU PTE attributes (from TSAR MMU specification)
[1]	38	////////////////////////////////////////////////////////////////////////////////////////
	39
[401]	40	#define TSAR_MMU_MAPPED 0x80000000
	41	#define TSAR_MMU_SMALL 0x40000000
[1]	42	#define TSAR_MMU_LOCAL 0x20000000
	43	#define TSAR_MMU_REMOTE 0x10000000
	44	#define TSAR_MMU_CACHABLE 0x08000000
	45	#define TSAR_MMU_WRITABLE 0x04000000
	46	#define TSAR_MMU_EXECUTABLE 0x02000000
	47	#define TSAR_MMU_USER 0x01000000
	48	#define TSAR_MMU_GLOBAL 0x00800000
	49	#define TSAR_MMU_DIRTY 0x00400000
	50
[401]	51	#define TSAR_MMU_COW 0x00000001 // only for small pages
	52	#define TSAR_MMU_SWAP 0x00000004 // only for small pages
	53	#define TSAR_MMU_LOCKED 0x00000008 // only for small pages
[1]	54
	55	////////////////////////////////////////////////////////////////////////////////////////
	56	// TSAR MMU related macros (from the TSAR MMU specification)
	57	// - IX1 on 11 bits
	58	// - IX2 on 9 bits
	59	// - PPN on 28 bits
	60	////////////////////////////////////////////////////////////////////////////////////////
	61
	62	#define TSAR_MMU_IX1_WIDTH 11
	63	#define TSAR_MMU_IX2_WIDTH 9
	64	#define TSAR_MMU_PPN_WIDTH 28
	65
[401]	66	#define TSAR_MMU_PTE1_ATTR_MASK 0xFFC00000
	67	#define TSAR_MMU_PTE1_PPN_MASK 0x0007FFFF
	68
[1]	69	#define TSAR_MMU_IX1_FROM_VPN( vpn ) ((vpn >> 9) & 0x7FF)
	70	#define TSAR_MMU_IX2_FROM_VPN( vpn ) (vpn & 0x1FF)
	71
[315]	72	#define TSAR_MMU_PTBA_FROM_PTE1( pte1 ) (pte1 & 0x0FFFFFFF)
	73	#define TSAR_MMU_PPN_FROM_PTE1( pte1 ) ((pte1 & 0x0007FFFF)<<9)
[1]	74	#define TSAR_MMU_ATTR_FROM_PTE1( pte1 ) (pte1 & 0xFFC00000)
	75
	76	#define TSAR_MMU_PPN_FROM_PTE2( pte2 ) (pte2 & 0x0FFFFFFF)
	77	#define TSAR_MMU_ATTR_FROM_PTE2( pte2 ) (pte2 & 0xFFC000FF)
	78
[401]	79
	80	///////////////////////////////////////////////////////////////////////////////////////
	81	// This static function translates the GPT attributes to the TSAR attributes
	82	///////////////////////////////////////////////////////////////////////////////////////
	83	static inline uint32_t gpt2tsar( uint32_t gpt_attr )
	84	{
	85	uint32_t tsar_attr = 0;
	86
	87	if( gpt_attr & GPT_MAPPED ) tsar_attr \|= TSAR_MMU_MAPPED;
	88	if( gpt_attr & GPT_SMALL ) tsar_attr \|= TSAR_MMU_SMALL;
	89	if( gpt_attr & GPT_WRITABLE ) tsar_attr \|= TSAR_MMU_WRITABLE;
	90	if( gpt_attr & GPT_EXECUTABLE ) tsar_attr \|= TSAR_MMU_EXECUTABLE;
	91	if( gpt_attr & GPT_CACHABLE ) tsar_attr \|= TSAR_MMU_CACHABLE;
	92	if( gpt_attr & GPT_USER ) tsar_attr \|= TSAR_MMU_USER;
	93	if( gpt_attr & GPT_DIRTY ) tsar_attr \|= TSAR_MMU_DIRTY;
	94	if( gpt_attr & GPT_ACCESSED ) tsar_attr \|= TSAR_MMU_LOCAL;
	95	if( gpt_attr & GPT_GLOBAL ) tsar_attr \|= TSAR_MMU_GLOBAL;
	96	if( gpt_attr & GPT_COW ) tsar_attr \|= TSAR_MMU_COW;
	97	if( gpt_attr & GPT_SWAP ) tsar_attr \|= TSAR_MMU_SWAP;
	98	if( gpt_attr & GPT_LOCKED ) tsar_attr \|= TSAR_MMU_LOCKED;
	99
	100	return tsar_attr;
	101	}
	102
	103	///////////////////////////////////////////////////////////////////////////////////////
	104	// This static function translates the TSAR attributes to the GPT attributes
	105	///////////////////////////////////////////////////////////////////////////////////////
	106	static inline uint32_t tsar2gpt( uint32_t tsar_attr )
	107	{
	108	uint32_t gpt_attr = 0;
	109
	110	if( tsar_attr & TSAR_MMU_MAPPED ) gpt_attr \|= GPT_MAPPED;
	111	if( tsar_attr & TSAR_MMU_MAPPED ) gpt_attr \|= GPT_READABLE;
	112	if( tsar_attr & TSAR_MMU_SMALL ) gpt_attr \|= GPT_SMALL;
	113	if( tsar_attr & TSAR_MMU_WRITABLE ) gpt_attr \|= GPT_WRITABLE;
	114	if( tsar_attr & TSAR_MMU_EXECUTABLE ) gpt_attr \|= GPT_EXECUTABLE;
	115	if( tsar_attr & TSAR_MMU_CACHABLE ) gpt_attr \|= GPT_CACHABLE;
	116	if( tsar_attr & TSAR_MMU_USER ) gpt_attr \|= GPT_USER;
	117	if( tsar_attr & TSAR_MMU_DIRTY ) gpt_attr \|= GPT_DIRTY;
	118	if( tsar_attr & TSAR_MMU_LOCAL ) gpt_attr \|= GPT_ACCESSED;
	119	if( tsar_attr & TSAR_MMU_REMOTE ) gpt_attr \|= GPT_ACCESSED;
	120	if( tsar_attr & TSAR_MMU_GLOBAL ) gpt_attr \|= GPT_GLOBAL;
	121	if( tsar_attr & TSAR_MMU_COW ) gpt_attr \|= GPT_COW;
	122	if( tsar_attr & TSAR_MMU_SWAP ) gpt_attr \|= GPT_SWAP;
	123	if( tsar_attr & TSAR_MMU_LOCKED ) gpt_attr \|= GPT_LOCKED;
	124
	125	return gpt_attr;
	126	}
	127
[1]	128	/////////////////////////////////////
	129	error_t hal_gpt_create( gpt_t * gpt )
	130	{
	131	page_t * page;
[315]	132	xptr_t page_xp;
[406]	133	vpn_t vpn;
	134	error_t error;
	135	uint32_t attr;
[1]	136
[407]	137	gpt_dmsg("\n[DBG] %s : core[%x,%d] enter\n",
	138	__FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid );
[406]	139
[1]	140	// check page size
[406]	141	assert( (CONFIG_PPM_PAGE_SIZE == 4096) , __FUNCTION__ ,
	142	"for TSAR, the page must be 4 Kbytes\n" );
[1]	143
	144	// allocates 2 physical pages for PT1
	145	kmem_req_t req;
	146	req.type = KMEM_PAGE;
	147	req.size = 1; // 2 small pages
	148	req.flags = AF_KERNEL \| AF_ZERO;
	149	page = (page_t *)kmem_alloc( &req );
	150
[406]	151	if( page == NULL )
[1]	152	{
[406]	153	printk("\n[ERROR] in %s : cannot allocate memory for PT1\n", __FUNCTION__ );
[1]	154	return ENOMEM;
[406]	155	}
[1]	156
	157	// initialize generic page table descriptor
[315]	158	page_xp = XPTR( local_cxy , page );
	159	gpt->ptr = GET_PTR( ppm_page2base( page_xp ) );
	160	gpt->ppn = ppm_page2ppn( page_xp );
	161
[406]	162	// identity map the kentry_vseg (must exist for all processes)
	163	attr = GPT_MAPPED \| GPT_SMALL \| GPT_EXECUTABLE \| GPT_CACHABLE \| GPT_GLOBAL;
	164	for( vpn = CONFIG_VMM_KENTRY_BASE;
	165	vpn < (CONFIG_VMM_KENTRY_BASE + CONFIG_VMM_KENTRY_SIZE); vpn++ )
	166	{
	167
[407]	168	gpt_dmsg("\n[DBG] %s : identity map vpn %d\n", __FUNCTION__ , vpn );
	169
[406]	170	error = hal_gpt_set_pte( gpt,
	171	vpn,
	172	(local_cxy<<20) \| (vpn & 0xFFFFF),
	173	attr );
	174
	175	if( error )
	176	{
	177	printk("\n[ERROR] in %s : cannot identity map kentry vseg\n", __FUNCTION__ );
	178	return ENOMEM;
	179	}
	180	}
	181
[407]	182	gpt_dmsg("\n[DBG] %s : core[%x,%d] exit\n",
	183	__FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid );
[406]	184
[1]	185	return 0;
[406]	186
[1]	187	} // end hal_gpt_create()
	188
	189
	190	///////////////////////////////////
	191	void hal_gpt_destroy( gpt_t * gpt )
	192	{
	193	uint32_t ix1;
	194	uint32_t ix2;
	195	uint32_t * pt1;
	196	uint32_t pte1;
	197	ppn_t pt2_ppn;
	198	uint32_t * pt2;
	199	uint32_t attr;
	200	vpn_t vpn;
	201	kmem_req_t req;
	202	bool_t is_ref;
	203
	204	// get pointer on calling process
	205	process_t * process = CURRENT_THREAD->process;
	206
	207	// compute is_ref
[23]	208	is_ref = ( GET_CXY( process->ref_xp ) == local_cxy );
[1]	209
	210	// get pointer on PT1
	211	pt1 = (uint32_t *)gpt->ptr;
	212
	213	// scan the PT1
	214	for( ix1 = 0 ; ix1 < 2048 ; ix1++ )
	215	{
	216	pte1 = pt1[ix1];
[401]	217	if( (pte1 & TSAR_MMU_MAPPED) != 0 ) // PTE1 valid
[1]	218	{
[401]	219	if( (pte1 & TSAR_MMU_SMALL) == 0 ) // BIG page
[1]	220	{
[391]	221	if( (pte1 & TSAR_MMU_USER) != 0 )
[1]	222	{
	223	// warning message
	224	printk("\n[WARNING] in %s : found an USER BIG page / ix1 = %d\n",
[391]	225	__FUNCTION__ , ix1 );
[1]	226
	227	// release the big physical page if reference cluster
	228	if( is_ref )
	229	{
	230	vpn = (vpn_t)(ix1 << TSAR_MMU_IX2_WIDTH);
	231	hal_gpt_reset_pte( gpt , vpn );
	232	}
	233	}
	234	}
[391]	235	else // SMALL page
[1]	236	{
[315]	237	// get local pointer on PT2
[1]	238	pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 );
[315]	239	xptr_t base_xp = ppm_ppn2base( pt2_ppn );
	240	pt2 = (uint32_t *)GET_PTR( base_xp );
[1]	241
	242	// scan the PT2 to release all entries VALID and USER if reference cluster
	243	if( is_ref )
	244	{
	245	for( ix2 = 0 ; ix2 < 512 ; ix2++ )
	246	{
	247	attr = TSAR_MMU_ATTR_FROM_PTE2( pt2[2 * ix2] );
[401]	248	if( ((attr & TSAR_MMU_MAPPED) != 0 ) && ((attr & TSAR_MMU_USER) != 0) )
[1]	249	{
	250	// release the physical page
	251	vpn = (vpn_t)((ix1 << TSAR_MMU_IX2_WIDTH) \| ix2);
	252	hal_gpt_reset_pte( gpt , vpn );
	253	}
	254	}
	255	}
	256
	257	// release the PT2
	258	req.type = KMEM_PAGE;
[315]	259	req.ptr = GET_PTR( ppm_base2page( XPTR(local_cxy , pt2 ) ) );
[1]	260	kmem_free( &req );
	261	}
	262	}
	263	}
	264
	265	// release the PT1
	266	req.type = KMEM_PAGE;
[315]	267	req.ptr = GET_PTR( ppm_base2page( XPTR(local_cxy , pt1 ) ) );
[1]	268	kmem_free( &req );
	269
	270	} // end hal_gpt_destroy()
	271
[407]	272	///////////////////////////////////////////
	273	void hal_gpt_display( process_t * process )
[1]	274	{
[407]	275	gpt_t * gpt;
[1]	276	uint32_t ix1;
	277	uint32_t ix2;
	278	uint32_t * pt1;
	279	uint32_t pte1;
	280	ppn_t pt2_ppn;
	281	uint32_t * pt2;
	282	uint32_t pte2_attr;
	283	ppn_t pte2_ppn;
[406]	284	vpn_t vpn;
[1]	285
[407]	286	assert( (process != NULL) , __FUNCTION__ , "NULL process pointer\n");
[1]	287
[407]	288	// get pointer on gpt
	289	gpt = &(process->vmm.gpt);
	290
	291	// get pointer on PT1
[1]	292	pt1 = (uint32_t *)gpt->ptr;
	293
[406]	294	printk("\n***** Generic Page Table for process %x : &gpt = %x / &pt1 = %x\n\n",
[407]	295	process->pid , gpt , pt1 );
[406]	296
[1]	297	// scan the PT1
	298	for( ix1 = 0 ; ix1 < 2048 ; ix1++ )
	299	{
	300	pte1 = pt1[ix1];
[401]	301	if( (pte1 & TSAR_MMU_MAPPED) != 0 )
[1]	302	{
[401]	303	if( (pte1 & TSAR_MMU_SMALL) == 0 ) // BIG page
[1]	304	{
[406]	305	vpn = ix1 << 9;
	306	printk(" - BIG : vpn = %x / pt1[%d] = %X\n", vpn , ix1 , pte1 );
[1]	307	}
	308	else // SMALL pages
	309	{
	310	pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 );
[315]	311	xptr_t base_xp = ppm_ppn2base ( pt2_ppn );
	312	pt2 = (uint32_t *)GET_PTR( base_xp );
[1]	313
	314	// scan the PT2
	315	for( ix2 = 0 ; ix2 < 512 ; ix2++ )
	316	{
	317	pte2_attr = TSAR_MMU_ATTR_FROM_PTE2( pt2[2 * ix2] );
	318	pte2_ppn = TSAR_MMU_PPN_FROM_PTE2( pt2[2 * ix2 + 1] );
[406]	319
[401]	320	if( (pte2_attr & TSAR_MMU_MAPPED) != 0 )
[1]	321	{
[406]	322	vpn = (ix1 << 9) \| ix2;
	323	printk(" - SMALL : vpn = %x / PT2[%d] = %x / pt2[%d] = %x\n",
	324	vpn , 2ix2 , pte2_attr , 2ix2+1 , pte2_ppn );
[1]	325	}
	326	}
	327	}
	328	}
	329	}
[407]	330	} // end hal_gpt_display()
[1]	331
	332
	333	///////////////////////////////////////
	334	error_t hal_gpt_set_pte( gpt_t * gpt,
	335	vpn_t vpn,
	336	ppn_t ppn,
[401]	337	uint32_t attr ) // generic GPT attributes
[1]	338	{
[406]	339	uint32_t * pt1; // PT1 base addres
	340	uint32_t * pte1_ptr; // pointer on PT1 entry
[401]	341	uint32_t pte1; // PT1 entry value
[1]	342
[401]	343	ppn_t pt2_ppn; // PPN of PT2
[406]	344	uint32_t * pt2; // PT2 base address
[1]	345
[401]	346	uint32_t small; // requested PTE is for a small page
[406]	347	bool_t success; // exit condition for while loop below
[315]	348
[401]	349	page_t * page; // pointer on new physical page descriptor
	350	xptr_t page_xp; // extended pointer on new page descriptor
[1]	351
[401]	352	uint32_t ix1; // index in PT1
	353	uint32_t ix2; // index in PT2
[1]	354
[401]	355	uint32_t tsar_attr; // PTE attributes for TSAR MMU
	356
[407]	357	gpt_dmsg("\n[DBG] %s : core[%x,%d] enter for vpn = %x / ppn = %x / gpt_attr = %x\n",
[406]	358	__FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , vpn , ppn , attr );
	359
[1]	360	// compute indexes in PT1 and PT2
	361	ix1 = TSAR_MMU_IX1_FROM_VPN( vpn );
	362	ix2 = TSAR_MMU_IX2_FROM_VPN( vpn );
	363
	364	pt1 = gpt->ptr;
[401]	365	small = attr & GPT_SMALL;
[1]	366
[401]	367	// compute tsar_attr from generic attributes
	368	tsar_attr = gpt2tsar( attr );
	369
[407]	370	gpt_dmsg("\n[DBG] %s : core[%x,%d] / vpn = %x / &pt1 = %x / tsar_attr = %x\n",
[406]	371	__FUNCTION__, local_cxy , CURRENT_THREAD->core->lid , vpn , pt1 , tsar_attr );
	372
	373	// get pointer on PT1[ix1]
[1]	374	pte1_ptr = &pt1[ix1];
	375
[406]	376	// PTE1 (big page) are only set for the kernel vsegs, in the kernel init phase.
[1]	377	// There is no risk of concurrent access.
[401]	378	if( small == 0 )
	379	{
[406]	380	// get current pte1 value
	381	pte1 = *pte1_ptr;
	382
	383	assert( (pte1 == 0) , __FUNCTION__ ,
	384	"try to set a big page in a mapped PT1 entry / PT1[%d] = %x\n", ix1 , pte1 );
[1]	385
	386	// set the PTE1
[401]	387	*pte1_ptr = (tsar_attr & TSAR_MMU_PTE1_ATTR_MASK) \|
	388	((ppn >> 9) & TSAR_MMU_PTE1_PPN_MASK);
[124]	389	hal_fence();
[1]	390	return 0;
	391	}
	392
	393	// From this point, the requested PTE is a PTE2 (small page)
	394
[406]	395	// loop to access PTE1 and get pointer on PT2
	396	success = false;
	397	do
	398	{
	399	// get current pte1 value
	400	pte1 = *pte1_ptr;
	401
[407]	402	gpt_dmsg("\n[DBG] %s : core[%x,%d] / vpn = %x / current_pte1 = %x\n",
[406]	403	__FUNCTION__, local_cxy , CURRENT_THREAD->core->lid , vpn , pte1 );
	404
	405	// allocate a PT2 if PT1 entry not valid
	406	if( (pte1 & TSAR_MMU_MAPPED) == 0 ) // PT1 entry not valid
	407	{
	408	// allocate one physical page for the PT2
	409	kmem_req_t req;
	410	req.type = KMEM_PAGE;
	411	req.size = 0; // 1 small page
	412	req.flags = AF_KERNEL \| AF_ZERO;
	413	page = (page_t *)kmem_alloc( &req );
	414	if( page == NULL )
	415	{
	416	printk("\n[ERROR] in %s : cannot allocate PT2\n", __FUNCTION__ );
	417	return ENOMEM;
	418	}
[1]	419
[406]	420	// get the PT2 PPN
	421	page_xp = XPTR( local_cxy , page );
	422	pt2_ppn = ppm_page2ppn( page_xp );
[315]	423
[406]	424	// try to atomicaly set the PT1 entry
	425	pte1 = TSAR_MMU_MAPPED \| TSAR_MMU_SMALL \| pt2_ppn;
	426	success = hal_atomic_cas( pte1_ptr , 0 , pte1 );
[1]	427
[406]	428	// release allocated PT2 if PT1 entry modified by another thread
	429	if( success == false ) ppm_free_pages( page );
	430	}
	431	else // PT1 entry is valid
[1]	432	{
[406]	433	// This valid entry must be a PTD1
	434	assert( (pte1 & TSAR_MMU_SMALL) , __FUNCTION__ ,
	435	"try to set a small page in a big PT1 entry / PT1[%d] = %x\n", ix1 , pte1 );
[1]	436
[406]	437	success = true;
[1]	438	}
	439
[406]	440	// get PT2 base from pte1
	441	pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 );
	442	pt2 = (uint32_t *)GET_PTR( ppm_ppn2base( pt2_ppn ) );
[1]	443
[407]	444	gpt_dmsg("\n[DBG] %s : core[%x,%d] / vpn = %x / pte1 = %x / &pt2 = %x\n",
[406]	445	__FUNCTION__, local_cxy , CURRENT_THREAD->core->lid , vpn , pte1 , pt2 );
	446
	447	}
	448	while (success == false);
[1]	449
	450	// set PTE2 in this order
	451	pt2[2 * ix2 + 1] = ppn;
[124]	452	hal_fence();
[401]	453	pt2[2 * ix2] = tsar_attr;
[124]	454	hal_fence();
[1]	455
[407]	456	gpt_dmsg("\n[DBG] %s : core[%x,%d] exit / vpn = %x / pte2_attr = %x / pte2_ppn = %x\n",
[406]	457	__FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , vpn ,
	458	pt2[2 * ix2] , pt2[2 * ix2 + 1] );
	459
[1]	460	return 0;
[401]	461
[1]	462	} // end of hal_gpt_set_pte()
	463
[406]	464
[1]	465	/////////////////////////////////////
	466	void hal_gpt_get_pte( gpt_t * gpt,
	467	vpn_t vpn,
	468	uint32_t * attr,
	469	ppn_t * ppn )
	470	{
	471	uint32_t * pt1;
	472	uint32_t pte1;
	473
	474	uint32_t * pt2;
	475	ppn_t pt2_ppn;
	476
	477	uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn );
	478	uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn );
	479
	480	// get PTE1 value
	481	pt1 = gpt->ptr;
	482	pte1 = pt1[ix1];
	483
[401]	484	if( (pte1 & TSAR_MMU_MAPPED) == 0 ) // PT1 entry not present
[1]	485	{
	486	*attr = 0;
	487	*ppn = 0;
	488	}
	489
[401]	490	if( (pte1 & TSAR_MMU_SMALL) == 0 ) // it's a PTE1
[1]	491	{
[401]	492	*attr = tsar2gpt( TSAR_MMU_ATTR_FROM_PTE1( pte1 ) );
[1]	493	*ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ) \| (vpn & ((1<<TSAR_MMU_IX2_WIDTH)-1));
	494	}
	495	else // it's a PTD1
	496	{
	497	// compute PT2 base address
	498	pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 );
[315]	499	pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) );
[1]	500
	501	ppn = pt2[2ix2+1] & ((1<<TSAR_MMU_PPN_WIDTH)-1);
[401]	502	attr = tsar2gpt( pt2[2ix2] );
[1]	503	}
	504	} // end hal_gpt_get_pte()
	505
	506	////////////////////////////////////
	507	void hal_gpt_reset_pte( gpt_t * gpt,
	508	vpn_t vpn )
	509	{
	510	uint32_t * pt1; // PT1 base address
	511	uint32_t pte1; // PT1 entry value
	512
	513	ppn_t pt2_ppn; // PPN of PT2
	514	uint32_t * pt2; // PT2 base address
	515
	516	ppn_t ppn; // PPN of page to be released
	517
[391]	518	// get ix1 & ix2 indexes
[1]	519	uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn );
	520	uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn );
	521
	522	// get PTE1 value
	523	pt1 = gpt->ptr;
	524	pte1 = pt1[ix1];
	525
[401]	526	if( (pte1 & TSAR_MMU_MAPPED) == 0 ) // PT1 entry not present
[1]	527	{
	528	return;
	529	}
	530
[401]	531	if( (pte1 & TSAR_MMU_SMALL) == 0 ) // it's a PTE1
[1]	532	{
	533	// get PPN
	534	ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 );
	535
	536	// unmap the big page
	537	pt1[ix1] = 0;
[124]	538	hal_fence();
[1]	539
	540	return;
	541	}
[391]	542	else // it's a PTD1
[1]	543	{
	544	// compute PT2 base address
	545	pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 );
[315]	546	pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) );
[1]	547
	548	// get PPN
	549	ppn = TSAR_MMU_PPN_FROM_PTE2( pt2[2*ix2+1] );
	550
	551	// unmap the small page
[391]	552	pt2[2*ix2] = 0; // only attr is reset
	553	hal_fence();
[1]	554
	555	return;
	556	}
	557	} // end hal_gpt_reset_pte()
	558
	559	//////////////////////////////////////
	560	error_t hal_gpt_lock_pte( gpt_t * gpt,
	561	vpn_t vpn )
	562	{
	563	uint32_t * pt1; // PT1 base address
	564	volatile uint32_t * pte1_ptr; // address of PT1 entry
	565	uint32_t pte1; // value of PT1 entry
	566
	567	uint32_t * pt2; // PT2 base address
	568	ppn_t pt2_ppn; // PPN of PT2 page if missing PT2
	569	volatile uint32_t * pte2_ptr; // address of PT2 entry
	570
	571	uint32_t attr;
	572	bool_t atomic;
	573	page_t * page;
[315]	574	xptr_t page_xp;
[1]	575
	576	uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); // index in PT1
	577	uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); // index in PT2
	578
	579	// get the PTE1 value
	580	pt1 = gpt->ptr;
	581	pte1_ptr = &pt1[ix1];
	582	pte1 = *pte1_ptr;
	583
	584	// If present, the page must be small
[401]	585	if( ((pte1 & TSAR_MMU_MAPPED) != 0) && ((pte1 & TSAR_MMU_SMALL) == 0) )
[1]	586	{
	587	printk("\n[ERROR] in %s : try to lock a big page / PT1[%d] = %x\n",
	588	__FUNCTION__ , ix1 , pte1 );
	589	return EINVAL;
	590	}
	591
[401]	592	if( (pte1 & TSAR_MMU_MAPPED) == 0 ) // missing PT1 entry
[1]	593	{
	594	// allocate one physical page for PT2
	595	kmem_req_t req;
	596	req.type = KMEM_PAGE;
	597	req.size = 0; // 1 small page
	598	req.flags = AF_KERNEL \| AF_ZERO;
	599	page = (page_t *)kmem_alloc( &req );
[23]	600
[1]	601	if( page == NULL )
	602	{
	603	printk("\n[ERROR] in %s : try to set a small page but cannot allocate PT2\n",
	604	__FUNCTION__ );
	605	return ENOMEM;
	606	}
[23]	607
[315]	608	page_xp = XPTR( local_cxy , page );
	609	pt2_ppn = ppm_page2ppn( page_xp );
	610	pt2 = (uint32_t *)GET_PTR( ppm_page2base( page_xp ) );
[1]	611
	612	// try to set the PT1 entry
	613	do
	614	{
	615	atomic = hal_atomic_cas( (void*)pte1_ptr , 0 ,
[401]	616	TSAR_MMU_MAPPED \| TSAR_MMU_SMALL \| pt2_ppn );
[1]	617	}
	618	while( (atomic == false) && (*pte1_ptr == 0) );
	619
	620	if( atomic == false ) // missing PT2 has been allocate by another core
	621	{
	622	// release the allocated page
	623	ppm_free_pages( page );
	624
	625	// read again the PTE1
	626	pte1 = *pte1_ptr;
	627
	628	// get the PT2 base address
	629	pt2_ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 );
[315]	630	pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) );
[1]	631	}
	632	}
	633	else
	634	{
	635	// This valid entry must be a PTD1
[401]	636	if( (pte1 & TSAR_MMU_SMALL) == 0 )
[1]	637	{
	638	printk("\n[ERROR] in %s : set a small page in a big PT1 entry / PT1[%d] = %x\n",
	639	__FUNCTION__ , ix1 , pte1 );
	640	return EINVAL;
	641	}
	642
	643	// compute PPN of PT2 base
	644	pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 );
	645
	646	// compute pointer on PT2 base
[315]	647	pt2 = (uint32_t *)GET_PTR( ppm_ppn2base( pt2_ppn ) );
[1]	648	}
	649
	650	// from here we have the PT2 pointer
	651
	652	// compute pointer on PTE2
	653	pte2_ptr = &pt2[2 * ix2];
	654
	655	// try to atomically lock the PTE2 until success
	656	do
	657	{
[401]	658	// busy waiting until TSAR_MMU_LOCK == 0
[1]	659	do
	660	{
	661	attr = *pte2_ptr;
	662	hal_rdbar();
	663	}
[401]	664	while( (attr & TSAR_MMU_LOCKED) != 0 );
[1]	665
[401]	666	atomic = hal_atomic_cas( (void*)pte2_ptr, attr , (attr \| TSAR_MMU_LOCKED) );
[1]	667	}
	668	while( atomic == 0 );
	669
	670	return 0;
[401]	671
[1]	672	} // end hal_gpt_lock_pte()
	673
	674	////////////////////////////////////////
	675	error_t hal_gpt_unlock_pte( gpt_t * gpt,
	676	vpn_t vpn )
	677	{
	678	uint32_t * pt1; // PT1 base address
	679	uint32_t pte1; // value of PT1 entry
	680
	681	uint32_t * pt2; // PT2 base address
	682	ppn_t pt2_ppn; // PPN of PT2 page if missing PT2
	683	uint32_t * pte2_ptr; // address of PT2 entry
	684
	685	uint32_t attr; // PTE2 attribute
	686
	687	// compute indexes in P1 and PT2
	688	uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); // index in PT1
	689	uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); // index in PT2
	690
	691	// get pointer on PT1 base
	692	pt1 = (uint32_t*)gpt->ptr;
	693
	694	// get PTE1
	695	pte1 = pt1[ix1];
	696
	697	// check PTE1 present and small page
[401]	698	if( ((pte1 & TSAR_MMU_MAPPED) == 0) \|\| ((pte1 & TSAR_MMU_SMALL) == 0) )
[1]	699	{
	700	printk("\n[ERROR] in %s : try to unlock a big or undefined page / PT1[%d] = %x\n",
	701	__FUNCTION__ , ix1 , pte1 );
	702	return EINVAL;
	703	}
	704
	705	// get pointer on PT2 base
	706	pt2_ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 );
[315]	707	pt2 = (uint32_t *)GET_PTR( ppm_ppn2base( pt2_ppn ) );
[1]	708
	709	// get pointer on PTE2
	710	pte2_ptr = &pt2[2 * ix2];
	711
	712	// get PTE2_ATTR
	713	attr = *pte2_ptr;
	714
	715	// check PTE2 present and locked
[401]	716	if( ((attr & TSAR_MMU_MAPPED) == 0) \|\| ((attr & TSAR_MMU_LOCKED) == 0) );
[1]	717	{
[401]	718	printk("\n[ERROR] in %s : unlock an unlocked/unmapped page / PT1[%d] = %x\n",
[1]	719	__FUNCTION__ , ix1 , pte1 );
	720	return EINVAL;
	721	}
	722
	723	// reset GPT_LOCK
[401]	724	*pte2_ptr = attr & ~TSAR_MMU_LOCKED;
[1]	725
	726	return 0;
[401]	727
[1]	728	} // end hal_gpt_unlock_pte()
	729
[23]	730	///////////////////////////////////////
	731	error_t hal_gpt_copy( gpt_t * dst_gpt,
	732	gpt_t * src_gpt,
[407]	733	vpn_t vpn_base,
	734	vpn_t vpn_size,
[23]	735	bool_t cow )
	736	{
[407]	737	vpn_t vpn; // current vpn
	738
[23]	739	uint32_t ix1; // index in PT1
	740	uint32_t ix2; // index in PT2
[1]	741
[23]	742	uint32_t * src_pt1; // local pointer on PT1 for SRC_GPT
	743	uint32_t * dst_pt1; // local pointer on PT1 for DST_GPT
	744	uint32_t * dst_pt2; // local pointer on PT2 for DST_GPT
	745	uint32_t * src_pt2; // local pointer on PT2 for SRC_GPT
[1]	746
[407]	747	kmem_req_t req; // for dynamic PT2 allocation
	748
	749	uint32_t src_pte1;
	750	uint32_t dst_pte1;
	751
[23]	752	uint32_t pte2_attr;
	753	uint32_t pte2_ppn;
[1]	754
[23]	755	page_t * page;
[315]	756	xptr_t page_xp;
[1]	757
[23]	758	ppn_t src_pt2_ppn;
	759	ppn_t dst_pt2_ppn;
[1]	760
[407]	761	gpt_dmsg("\n[DBG] %s : core[%x,%d] enter\n",
	762	__FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid );
	763
	764	// check page size
	765	assert( (CONFIG_PPM_PAGE_SIZE == 4096) , __FUNCTION__ ,
	766	"for TSAR, the page must be 4 Kbytes\n" );
	767
	768	// check SRC_PT1 and DST_PT1 existence
	769	assert( (src_gpt->ptr != NULL) , __FUNCTION__ , "SRC_PT1 does not exist\n");
	770	assert( (dst_gpt->ptr != NULL) , __FUNCTION__ , "DST_PT1 does not exist\n");
	771
	772	// get pointers on SRC_PT1 and DST_PT1
[23]	773	src_pt1 = (uint32_t *)src_gpt->ptr;
	774	dst_pt1 = (uint32_t *)dst_gpt->ptr;
[1]	775
[407]	776	// scan pages in vseg
	777	for( vpn = vpn_base ; vpn < (vpn_base + vpn_size) ; vpn++ )
	778	{
	779	ix1 = TSAR_MMU_IX1_FROM_VPN( vpn );
	780	ix2 = TSAR_MMU_IX2_FROM_VPN( vpn );
	781
	782	// get SRC_PT1 entry
	783	src_pte1 = src_pt1[ix1];
	784
	785	// do nothing if SRC_PTE1 unmapped
	786	if( (src_pte1 & TSAR_MMU_MAPPED) != 0 ) // SRC_PTE1 is mapped
	787	{
	788	assert( (src_pte1 & TSAR_MMU_SMALL) , __FUNCTION__ ,
	789	"no BIG page for user process in TSAR architecture\n" );
	790
	791	// get DST_PT1 entry
	792	dst_pte1 = dst_pt1[ix1];
	793
	794	// map dst_pte1 if required
	795	if( (dst_pte1 & TSAR_MMU_MAPPED) == 0 )
	796	{
	797	// allocate one physical page for a new DST_PT2
	798	req.type = KMEM_PAGE;
	799	req.size = 0; // 1 small page
	800	req.flags = AF_KERNEL \| AF_ZERO;
	801	page = (page_t *)kmem_alloc( &req );
	802
	803	if( page == NULL )
	804	{
	805	printk("\n[ERROR] in %s : cannot allocate PT2\n", __FUNCTION__ );
	806	return ENOMEM;
	807	}
	808
	809	// build extended pointer on page descriptor
	810	page_xp = XPTR( local_cxy , page );
	811
	812	// get PPN for this new DST_PT2
	813	dst_pt2_ppn = (ppn_t)ppm_page2ppn( page_xp );
	814
	815	// build the new dst_pte1
	816	dst_pte1 = TSAR_MMU_MAPPED \| TSAR_MMU_SMALL \| dst_pt2_ppn;
	817
	818	// register it in DST_GPT
	819	dst_pt1[ix1] = dst_pte1;
	820	}
	821
	822	// get PPN and pointer on SRC_PT2
	823	src_pt2_ppn = (ppn_t)TSAR_MMU_PTBA_FROM_PTE1( src_pte1 );
	824	src_pt2 = (uint32_t *)GET_PTR( ppm_ppn2base( src_pt2_ppn ) );
	825
	826	// get PPN and pointer on DST_PT2
	827	dst_pt2_ppn = (ppn_t)TSAR_MMU_PTBA_FROM_PTE1( dst_pte1 );
	828	dst_pt2 = (uint32_t *)GET_PTR( ppm_ppn2base( dst_pt2_ppn ) );
	829
	830	// get attr and ppn from SRC_PT2
	831	pte2_attr = TSAR_MMU_ATTR_FROM_PTE2( src_pt2[2 * ix2] );
	832	pte2_ppn = TSAR_MMU_PPN_FROM_PTE2( src_pt2[2 * ix2 + 1] );
	833
	834	// no copy if SRC_PTE2 unmapped
	835	if( (pte2_attr & TSAR_MMU_MAPPED) != 0 ) // valid PTE2 in SRC_GPT
	836	{
	837	// set a new PTE2 in DST_PT2
	838	dst_pt2[2*ix2] = pte2_attr;
	839	dst_pt2[2*ix2 + 1] = pte2_ppn;
	840
	841	// FIXME increment page descriptor refcount for the referenced page
	842
	843	// handle Copy-On-Write
	844	if( cow && (pte2_attr & TSAR_MMU_WRITABLE) )
	845	{
	846	// reset WRITABLE flag in DST_GPT
	847	hal_atomic_and( &dst_pt2[2*ix2] , ~TSAR_MMU_WRITABLE );
	848
	849	// set COW flag in DST_GPT
	850	hal_atomic_or( &dst_pt2[2*ix2] , TSAR_MMU_COW );
	851	}
	852	}
	853	} // end if PTE1 mapped
	854	} // end loop on vpn
	855
	856	hal_fence();
	857
	858	gpt_dmsg("\n[DBG] %s : core[%x,%d] exit\n",
	859	__FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid );
	860
	861	return 0;
	862
	863	} // end hal_gpt_copy()
	864
	865	///////////////////////////////////////
	866	bool_t hal_gpt_pte_is_cow( gpt_t * gpt,
	867	vpn_t vpn )
	868	{
	869	uint32_t * pt1;
	870	uint32_t pte1;
	871
	872	uint32_t * pt2;
	873	ppn_t pt2_ppn;
	874
	875	uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn );
	876	uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn );
	877
	878	// get PTE1 value
	879	pt1 = gpt->ptr;
	880	pte1 = pt1[ix1];
	881
	882	if( (pte1 & TSAR_MMU_MAPPED) == 0 ) // PT1 entry not mapped
	883	{
	884	return false;
	885	}
	886
	887	if( (pte1 & TSAR_MMU_SMALL) == 0 ) // it's a PTE1
	888	{
	889	return false;
	890	}
	891	else // it's a PTD1
	892	{
	893	// compute PT2 base address
	894	pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 );
	895	pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) );
	896
	897	if( pt2[2*ix2] & TSAR_MMU_COW ) return true;
	898	else return false;
	899	}
	900	} // end hal_gpt_pte_is_cow()
	901
	902
	903
	904
	905
	906
	907
	908
	909
	910
	911
	912
	913	/* deprecated : old hal_gpt_copy [AG]
	914
[23]	915	// scan the SRC_PT1
	916	for( ix1 = 0 ; ix1 < 2048 ; ix1++ )
	917	{
	918	pte1 = src_pt1[ix1];
[401]	919	if( (pte1 & TSAR_MMU_MAPPED) != 0 )
[23]	920	{
[401]	921	if( (pte1 & TSAR_MMU_SMALL) == 0 ) // PTE1 => big kernel page
[23]	922	{
	923	// big kernel pages are shared by all processes => copy it
	924	dst_pt1[ix1] = pte1;
	925	}
	926	else // PTD1 => smal pages
	927	{
	928	// allocate one physical page for a PT2 in DST_GPT
	929	kmem_req_t req;
	930	req.type = KMEM_PAGE;
	931	req.size = 0; // 1 small page
	932	req.flags = AF_KERNEL \| AF_ZERO;
	933	page = (page_t *)kmem_alloc( &req );
[1]	934
[23]	935	if( page == NULL )
	936	{
	937	// TODO release all memory allocated to DST_GPT
	938	printk("\n[ERROR] in %s : cannot allocate PT2\n", __FUNCTION__ );
	939	return ENOMEM;
	940	}
	941
[315]	942	// get extended pointer on page descriptor
	943	page_xp = XPTR( local_cxy , page );
	944
[23]	945	// get pointer on new PT2 in DST_GPT
[315]	946	xptr_t base_xp = ppm_page2base( page_xp );
	947	dst_pt2 = (uint32_t *)GET_PTR( base_xp );
[23]	948
	949	// set a new PTD1 in DST_GPT
[315]	950	dst_pt2_ppn = (ppn_t)ppm_page2ppn( page_xp );
[401]	951	dst_pt1[ix1] = TSAR_MMU_MAPPED \| TSAR_MMU_SMALL \| dst_pt2_ppn;
[23]	952
	953	// get pointer on PT2 in SRC_GPT
	954	src_pt2_ppn = (ppn_t)TSAR_MMU_PTBA_FROM_PTE1( pte1 );
[315]	955	src_pt2 = (uint32_t *)GET_PTR( ppm_ppn2base( src_pt2_ppn ) );
[23]	956
	957	// scan the SRC_PT2
	958	for( ix2 = 0 ; ix2 < 512 ; ix2++ )
	959	{
	960	// get attr & ppn from PTE2
	961	pte2_attr = TSAR_MMU_ATTR_FROM_PTE2( src_pt2[2 * ix2] );
	962
[401]	963	if( (pte2_attr & TSAR_MMU_MAPPED) != 0 ) // valid PTE2 in SRC_GPT
[23]	964	{
	965	// get GPT_WRITABLE & PPN
	966	pte2_writable = pte2_attr & GPT_WRITABLE;
	967	pte2_ppn = TSAR_MMU_PPN_FROM_PTE2( src_pt2[2 * ix2 + 1] );
	968
	969	// set a new PTE2 in DST_GPT
	970	dst_pt2[2*ix2] = pte2_attr;
	971	dst_pt2[2*ix2 + 1] = pte2_ppn;
	972
	973	// handle Copy-On-Write
	974	if( cow && pte2_writable )
	975	{
	976	// reset GPT_WRITABLE in both SRC_GPT and DST_GPT
	977	hal_atomic_and( &dst_pt2[2*ix2] , ~GPT_WRITABLE );
	978	hal_atomic_and( &src_pt2[2*ix2] , ~GPT_WRITABLE );
	979
	980	// register PG_COW in page descriptor
[315]	981	page = (page_t *)GET_PTR( ppm_ppn2page( pte2_ppn ) );
[23]	982	hal_atomic_or( &page->flags , PG_COW );
	983	hal_atomic_add( &page->fork_nr , 1 );
	984	}
	985	}
	986	} // end loop on ix2
	987	}
	988	}
	989	} // end loop ix1
	990
[124]	991	hal_fence();
[23]	992
	993	return 0;
	994
	995	} // end hal_gpt_copy()
	996
[407]	997	*/

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