[1] | 1 | /* |
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| 2 | * hal_gpt.c - implementation of the Generic Page Table API for TSAR-MIPS32 |
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| 3 | * |
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[445] | 4 | * Author Alain Greiner (2016,2017,2018) |
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[1] | 5 | * |
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| 6 | * Copyright (c) UPMC Sorbonne Universites |
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| 7 | * |
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| 8 | * This file is part of ALMOS-MKH. |
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| 9 | * |
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| 10 | * ALMOS-MKH.is free software; you can redistribute it and/or modify it |
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| 11 | * under the terms of the GNU General Public License as published by |
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| 12 | * the Free Software Foundation; version 2.0 of the License. |
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| 13 | * |
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| 14 | * ALMOS-MKH.is distributed in the hope that it will be useful, but |
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| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 17 | * General Public License for more details. |
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| 18 | * |
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| 19 | * You should have received a copy of the GNU General Public License |
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| 20 | * along with ALMOS-MKH.; if not, write to the Free Software Foundation, |
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| 21 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 22 | */ |
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| 23 | |
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[457] | 24 | #include <hal_kernel_types.h> |
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[1] | 25 | #include <hal_gpt.h> |
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| 26 | #include <hal_special.h> |
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| 27 | #include <printk.h> |
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| 28 | #include <bits.h> |
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| 29 | #include <process.h> |
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| 30 | #include <kmem.h> |
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| 31 | #include <thread.h> |
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| 32 | #include <cluster.h> |
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| 33 | #include <ppm.h> |
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| 34 | #include <page.h> |
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| 35 | |
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| 36 | //////////////////////////////////////////////////////////////////////////////////////// |
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[401] | 37 | // This define the masks for the TSAR MMU PTE attributes (from TSAR MMU specification) |
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[1] | 38 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 39 | |
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[401] | 40 | #define TSAR_MMU_MAPPED 0x80000000 |
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| 41 | #define TSAR_MMU_SMALL 0x40000000 |
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[1] | 42 | #define TSAR_MMU_LOCAL 0x20000000 |
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| 43 | #define TSAR_MMU_REMOTE 0x10000000 |
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| 44 | #define TSAR_MMU_CACHABLE 0x08000000 |
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| 45 | #define TSAR_MMU_WRITABLE 0x04000000 |
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| 46 | #define TSAR_MMU_EXECUTABLE 0x02000000 |
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| 47 | #define TSAR_MMU_USER 0x01000000 |
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| 48 | #define TSAR_MMU_GLOBAL 0x00800000 |
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| 49 | #define TSAR_MMU_DIRTY 0x00400000 |
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| 50 | |
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[401] | 51 | #define TSAR_MMU_COW 0x00000001 // only for small pages |
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| 52 | #define TSAR_MMU_SWAP 0x00000004 // only for small pages |
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| 53 | #define TSAR_MMU_LOCKED 0x00000008 // only for small pages |
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[1] | 54 | |
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| 55 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 56 | // TSAR MMU related macros (from the TSAR MMU specification) |
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| 57 | // - IX1 on 11 bits |
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| 58 | // - IX2 on 9 bits |
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| 59 | // - PPN on 28 bits |
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| 60 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 61 | |
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| 62 | #define TSAR_MMU_IX1_WIDTH 11 |
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| 63 | #define TSAR_MMU_IX2_WIDTH 9 |
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| 64 | #define TSAR_MMU_PPN_WIDTH 28 |
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| 65 | |
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[401] | 66 | #define TSAR_MMU_PTE1_ATTR_MASK 0xFFC00000 |
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| 67 | #define TSAR_MMU_PTE1_PPN_MASK 0x0007FFFF |
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| 68 | |
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[1] | 69 | #define TSAR_MMU_IX1_FROM_VPN( vpn ) ((vpn >> 9) & 0x7FF) |
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| 70 | #define TSAR_MMU_IX2_FROM_VPN( vpn ) (vpn & 0x1FF) |
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| 71 | |
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[315] | 72 | #define TSAR_MMU_PTBA_FROM_PTE1( pte1 ) (pte1 & 0x0FFFFFFF) |
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| 73 | #define TSAR_MMU_PPN_FROM_PTE1( pte1 ) ((pte1 & 0x0007FFFF)<<9) |
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[1] | 74 | #define TSAR_MMU_ATTR_FROM_PTE1( pte1 ) (pte1 & 0xFFC00000) |
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| 75 | |
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| 76 | #define TSAR_MMU_PPN_FROM_PTE2( pte2 ) (pte2 & 0x0FFFFFFF) |
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| 77 | #define TSAR_MMU_ATTR_FROM_PTE2( pte2 ) (pte2 & 0xFFC000FF) |
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| 78 | |
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[401] | 79 | |
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| 80 | /////////////////////////////////////////////////////////////////////////////////////// |
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| 81 | // This static function translates the GPT attributes to the TSAR attributes |
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| 82 | /////////////////////////////////////////////////////////////////////////////////////// |
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| 83 | static inline uint32_t gpt2tsar( uint32_t gpt_attr ) |
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| 84 | { |
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| 85 | uint32_t tsar_attr = 0; |
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| 86 | |
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| 87 | if( gpt_attr & GPT_MAPPED ) tsar_attr |= TSAR_MMU_MAPPED; |
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| 88 | if( gpt_attr & GPT_SMALL ) tsar_attr |= TSAR_MMU_SMALL; |
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| 89 | if( gpt_attr & GPT_WRITABLE ) tsar_attr |= TSAR_MMU_WRITABLE; |
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| 90 | if( gpt_attr & GPT_EXECUTABLE ) tsar_attr |= TSAR_MMU_EXECUTABLE; |
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| 91 | if( gpt_attr & GPT_CACHABLE ) tsar_attr |= TSAR_MMU_CACHABLE; |
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| 92 | if( gpt_attr & GPT_USER ) tsar_attr |= TSAR_MMU_USER; |
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| 93 | if( gpt_attr & GPT_DIRTY ) tsar_attr |= TSAR_MMU_DIRTY; |
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| 94 | if( gpt_attr & GPT_ACCESSED ) tsar_attr |= TSAR_MMU_LOCAL; |
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| 95 | if( gpt_attr & GPT_GLOBAL ) tsar_attr |= TSAR_MMU_GLOBAL; |
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| 96 | if( gpt_attr & GPT_COW ) tsar_attr |= TSAR_MMU_COW; |
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| 97 | if( gpt_attr & GPT_SWAP ) tsar_attr |= TSAR_MMU_SWAP; |
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| 98 | if( gpt_attr & GPT_LOCKED ) tsar_attr |= TSAR_MMU_LOCKED; |
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| 99 | |
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| 100 | return tsar_attr; |
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| 101 | } |
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| 102 | |
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| 103 | /////////////////////////////////////////////////////////////////////////////////////// |
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| 104 | // This static function translates the TSAR attributes to the GPT attributes |
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| 105 | /////////////////////////////////////////////////////////////////////////////////////// |
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| 106 | static inline uint32_t tsar2gpt( uint32_t tsar_attr ) |
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| 107 | { |
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| 108 | uint32_t gpt_attr = 0; |
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| 109 | |
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| 110 | if( tsar_attr & TSAR_MMU_MAPPED ) gpt_attr |= GPT_MAPPED; |
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| 111 | if( tsar_attr & TSAR_MMU_MAPPED ) gpt_attr |= GPT_READABLE; |
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| 112 | if( tsar_attr & TSAR_MMU_SMALL ) gpt_attr |= GPT_SMALL; |
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| 113 | if( tsar_attr & TSAR_MMU_WRITABLE ) gpt_attr |= GPT_WRITABLE; |
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| 114 | if( tsar_attr & TSAR_MMU_EXECUTABLE ) gpt_attr |= GPT_EXECUTABLE; |
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| 115 | if( tsar_attr & TSAR_MMU_CACHABLE ) gpt_attr |= GPT_CACHABLE; |
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| 116 | if( tsar_attr & TSAR_MMU_USER ) gpt_attr |= GPT_USER; |
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| 117 | if( tsar_attr & TSAR_MMU_DIRTY ) gpt_attr |= GPT_DIRTY; |
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| 118 | if( tsar_attr & TSAR_MMU_LOCAL ) gpt_attr |= GPT_ACCESSED; |
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| 119 | if( tsar_attr & TSAR_MMU_REMOTE ) gpt_attr |= GPT_ACCESSED; |
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| 120 | if( tsar_attr & TSAR_MMU_GLOBAL ) gpt_attr |= GPT_GLOBAL; |
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| 121 | if( tsar_attr & TSAR_MMU_COW ) gpt_attr |= GPT_COW; |
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| 122 | if( tsar_attr & TSAR_MMU_SWAP ) gpt_attr |= GPT_SWAP; |
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| 123 | if( tsar_attr & TSAR_MMU_LOCKED ) gpt_attr |= GPT_LOCKED; |
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| 124 | |
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| 125 | return gpt_attr; |
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| 126 | } |
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| 127 | |
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[1] | 128 | ///////////////////////////////////// |
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| 129 | error_t hal_gpt_create( gpt_t * gpt ) |
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| 130 | { |
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| 131 | page_t * page; |
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[315] | 132 | xptr_t page_xp; |
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[1] | 133 | |
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[587] | 134 | thread_t * this = CURRENT_THREAD; |
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| 135 | |
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[443] | 136 | #if DEBUG_HAL_GPT_CREATE |
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[587] | 137 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
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[443] | 138 | if( DEBUG_HAL_GPT_CREATE < cycle ) |
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[611] | 139 | printk("\n[%s] : thread[%x,%x] enter / cycle %d\n", |
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[587] | 140 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
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[432] | 141 | #endif |
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[406] | 142 | |
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[623] | 143 | // check page size |
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| 144 | assert( (CONFIG_PPM_PAGE_SIZE == 4096) , "for TSAR, the page size must be 4 Kbytes\n" ); |
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[1] | 145 | |
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| 146 | // allocates 2 physical pages for PT1 |
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| 147 | kmem_req_t req; |
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| 148 | req.type = KMEM_PAGE; |
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| 149 | req.size = 1; // 2 small pages |
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| 150 | req.flags = AF_KERNEL | AF_ZERO; |
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| 151 | page = (page_t *)kmem_alloc( &req ); |
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| 152 | |
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[406] | 153 | if( page == NULL ) |
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[1] | 154 | { |
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[587] | 155 | printk("\n[PANIC] in %s : no memory for PT1 / process %x / cluster %x\n", |
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| 156 | __FUNCTION__, this->process->pid, local_cxy ); |
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[1] | 157 | return ENOMEM; |
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[406] | 158 | } |
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[1] | 159 | |
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| 160 | // initialize generic page table descriptor |
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[315] | 161 | page_xp = XPTR( local_cxy , page ); |
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| 162 | gpt->ptr = GET_PTR( ppm_page2base( page_xp ) ); |
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| 163 | gpt->ppn = ppm_page2ppn( page_xp ); |
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| 164 | |
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[443] | 165 | #if DEBUG_HAL_GPT_CREATE |
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[587] | 166 | cycle = (uint32_t)hal_get_cycles(); |
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[443] | 167 | if( DEBUG_HAL_GPT_CREATE < cycle ) |
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[611] | 168 | printk("\n[%s] : thread[%x,%x] exit / cycle %d\n", |
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[587] | 169 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
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[432] | 170 | #endif |
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[406] | 171 | |
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[1] | 172 | return 0; |
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[406] | 173 | |
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[1] | 174 | } // end hal_gpt_create() |
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| 175 | |
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| 176 | /////////////////////////////////// |
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| 177 | void hal_gpt_destroy( gpt_t * gpt ) |
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| 178 | { |
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| 179 | uint32_t ix1; |
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| 180 | uint32_t ix2; |
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| 181 | uint32_t * pt1; |
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| 182 | uint32_t pte1; |
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| 183 | ppn_t pt2_ppn; |
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| 184 | uint32_t * pt2; |
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| 185 | uint32_t attr; |
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| 186 | vpn_t vpn; |
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| 187 | kmem_req_t req; |
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| 188 | bool_t is_ref; |
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| 189 | |
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[443] | 190 | #if DEBUG_HAL_GPT_DESTROY |
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[587] | 191 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
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| 192 | thread_t * this = CURRENT_THREAD; |
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[443] | 193 | if( DEBUG_HAL_GPT_DESTROY < cycle ) |
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[611] | 194 | printk("\n[%s] : thread[%x,%x] enter / cycle %d\n", |
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[587] | 195 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
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[443] | 196 | #endif |
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| 197 | |
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[1] | 198 | // get pointer on calling process |
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| 199 | process_t * process = CURRENT_THREAD->process; |
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| 200 | |
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| 201 | // compute is_ref |
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[23] | 202 | is_ref = ( GET_CXY( process->ref_xp ) == local_cxy ); |
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[1] | 203 | |
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| 204 | // get pointer on PT1 |
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| 205 | pt1 = (uint32_t *)gpt->ptr; |
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| 206 | |
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| 207 | // scan the PT1 |
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| 208 | for( ix1 = 0 ; ix1 < 2048 ; ix1++ ) |
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| 209 | { |
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| 210 | pte1 = pt1[ix1]; |
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[401] | 211 | if( (pte1 & TSAR_MMU_MAPPED) != 0 ) // PTE1 valid |
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[1] | 212 | { |
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[401] | 213 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) // BIG page |
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[1] | 214 | { |
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[391] | 215 | if( (pte1 & TSAR_MMU_USER) != 0 ) |
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[1] | 216 | { |
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| 217 | // warning message |
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| 218 | printk("\n[WARNING] in %s : found an USER BIG page / ix1 = %d\n", |
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[391] | 219 | __FUNCTION__ , ix1 ); |
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[1] | 220 | |
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| 221 | // release the big physical page if reference cluster |
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| 222 | if( is_ref ) |
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| 223 | { |
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| 224 | vpn = (vpn_t)(ix1 << TSAR_MMU_IX2_WIDTH); |
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| 225 | hal_gpt_reset_pte( gpt , vpn ); |
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| 226 | } |
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| 227 | } |
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| 228 | } |
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[391] | 229 | else // SMALL page |
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[1] | 230 | { |
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[315] | 231 | // get local pointer on PT2 |
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[1] | 232 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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[315] | 233 | xptr_t base_xp = ppm_ppn2base( pt2_ppn ); |
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[587] | 234 | pt2 = GET_PTR( base_xp ); |
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[1] | 235 | |
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| 236 | // scan the PT2 to release all entries VALID and USER if reference cluster |
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| 237 | if( is_ref ) |
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| 238 | { |
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| 239 | for( ix2 = 0 ; ix2 < 512 ; ix2++ ) |
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| 240 | { |
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| 241 | attr = TSAR_MMU_ATTR_FROM_PTE2( pt2[2 * ix2] ); |
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[401] | 242 | if( ((attr & TSAR_MMU_MAPPED) != 0 ) && ((attr & TSAR_MMU_USER) != 0) ) |
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[1] | 243 | { |
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| 244 | // release the physical page |
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| 245 | vpn = (vpn_t)((ix1 << TSAR_MMU_IX2_WIDTH) | ix2); |
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| 246 | hal_gpt_reset_pte( gpt , vpn ); |
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| 247 | } |
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| 248 | } |
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| 249 | } |
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| 250 | |
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| 251 | // release the PT2 |
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| 252 | req.type = KMEM_PAGE; |
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[315] | 253 | req.ptr = GET_PTR( ppm_base2page( XPTR(local_cxy , pt2 ) ) ); |
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[1] | 254 | kmem_free( &req ); |
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| 255 | } |
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| 256 | } |
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| 257 | } |
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| 258 | |
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| 259 | // release the PT1 |
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| 260 | req.type = KMEM_PAGE; |
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[315] | 261 | req.ptr = GET_PTR( ppm_base2page( XPTR(local_cxy , pt1 ) ) ); |
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[1] | 262 | kmem_free( &req ); |
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| 263 | |
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[443] | 264 | #if DEBUG_HAL_GPT_DESTROY |
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[587] | 265 | cycle = (uint32_t)hal_get_cycles(); |
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[443] | 266 | if( DEBUG_HAL_GPT_DESTROY < cycle ) |
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[611] | 267 | printk("\n[%s] : thread[%x,%x] exit / cycle %d\n", |
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[587] | 268 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
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[443] | 269 | #endif |
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| 270 | |
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[1] | 271 | } // end hal_gpt_destroy() |
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| 272 | |
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[407] | 273 | /////////////////////////////////////////// |
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| 274 | void hal_gpt_display( process_t * process ) |
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[1] | 275 | { |
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[407] | 276 | gpt_t * gpt; |
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[1] | 277 | uint32_t ix1; |
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| 278 | uint32_t ix2; |
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| 279 | uint32_t * pt1; |
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| 280 | uint32_t pte1; |
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| 281 | ppn_t pt2_ppn; |
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| 282 | uint32_t * pt2; |
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| 283 | uint32_t pte2_attr; |
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| 284 | ppn_t pte2_ppn; |
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[406] | 285 | vpn_t vpn; |
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[1] | 286 | |
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[623] | 287 | // check argument |
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| 288 | assert( (process != NULL) , "NULL process pointer\n"); |
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[1] | 289 | |
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[407] | 290 | // get pointer on gpt |
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| 291 | gpt = &(process->vmm.gpt); |
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| 292 | |
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| 293 | // get pointer on PT1 |
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[1] | 294 | pt1 = (uint32_t *)gpt->ptr; |
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| 295 | |
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[623] | 296 | printk("\n***** Tsar Page Table for process %x : &gpt = %x / &pt1 = %x\n\n", |
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[407] | 297 | process->pid , gpt , pt1 ); |
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[406] | 298 | |
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[1] | 299 | // scan the PT1 |
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| 300 | for( ix1 = 0 ; ix1 < 2048 ; ix1++ ) |
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| 301 | { |
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| 302 | pte1 = pt1[ix1]; |
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[401] | 303 | if( (pte1 & TSAR_MMU_MAPPED) != 0 ) |
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[1] | 304 | { |
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[401] | 305 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) // BIG page |
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[1] | 306 | { |
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[406] | 307 | vpn = ix1 << 9; |
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| 308 | printk(" - BIG : vpn = %x / pt1[%d] = %X\n", vpn , ix1 , pte1 ); |
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[1] | 309 | } |
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| 310 | else // SMALL pages |
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| 311 | { |
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| 312 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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[315] | 313 | xptr_t base_xp = ppm_ppn2base ( pt2_ppn ); |
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[587] | 314 | pt2 = GET_PTR( base_xp ); |
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[1] | 315 | |
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| 316 | // scan the PT2 |
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| 317 | for( ix2 = 0 ; ix2 < 512 ; ix2++ ) |
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| 318 | { |
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| 319 | pte2_attr = TSAR_MMU_ATTR_FROM_PTE2( pt2[2 * ix2] ); |
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| 320 | pte2_ppn = TSAR_MMU_PPN_FROM_PTE2( pt2[2 * ix2 + 1] ); |
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[406] | 321 | |
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[401] | 322 | if( (pte2_attr & TSAR_MMU_MAPPED) != 0 ) |
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[1] | 323 | { |
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[406] | 324 | vpn = (ix1 << 9) | ix2; |
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[408] | 325 | printk(" - SMALL : vpn %X / ppn %X / attr %X\n", |
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| 326 | vpn , pte2_ppn , tsar2gpt(pte2_attr) ); |
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[1] | 327 | } |
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| 328 | } |
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| 329 | } |
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| 330 | } |
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| 331 | } |
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[407] | 332 | } // end hal_gpt_display() |
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[1] | 333 | |
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| 334 | |
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[587] | 335 | ////////////////////////////////////////// |
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| 336 | error_t hal_gpt_set_pte( xptr_t gpt_xp, |
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[1] | 337 | vpn_t vpn, |
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[587] | 338 | uint32_t attr, // GPT attributes |
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[408] | 339 | ppn_t ppn ) |
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[1] | 340 | { |
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[587] | 341 | cxy_t gpt_cxy; // target GPT cluster |
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| 342 | gpt_t * gpt_ptr; // target GPT local pointer |
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| 343 | uint32_t * pt1_ptr; // local pointer on PT1 |
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| 344 | xptr_t pte1_xp; // extended pointer on PT1 entry |
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| 345 | uint32_t pte1; // PT1 entry value if PTE1 |
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[1] | 346 | |
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[401] | 347 | ppn_t pt2_ppn; // PPN of PT2 |
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[587] | 348 | uint32_t * pt2_ptr; // PT2 base address |
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[1] | 349 | |
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[401] | 350 | uint32_t small; // requested PTE is for a small page |
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[315] | 351 | |
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[401] | 352 | page_t * page; // pointer on new physical page descriptor |
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| 353 | xptr_t page_xp; // extended pointer on new page descriptor |
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[1] | 354 | |
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[401] | 355 | uint32_t ix1; // index in PT1 |
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| 356 | uint32_t ix2; // index in PT2 |
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[1] | 357 | |
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[401] | 358 | uint32_t tsar_attr; // PTE attributes for TSAR MMU |
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| 359 | |
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[587] | 360 | thread_t * this = CURRENT_THREAD; |
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| 361 | |
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| 362 | // get cluster and local pointer on GPT |
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| 363 | gpt_cxy = GET_CXY( gpt_xp ); |
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| 364 | gpt_ptr = GET_PTR( gpt_xp ); |
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| 365 | |
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| 366 | #if DEBUG_HAL_GPT_SET_PTE |
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| 367 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
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| 368 | if( DEBUG_HAL_GPT_SET_PTE < cycle ) |
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[611] | 369 | printk("\n[%s] : thread[%x,%x] enter / vpn %x / attr %x / ppn %x / cluster %x / cycle %d\n", |
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[587] | 370 | __FUNCTION__, this->process->pid, this->trdid, vpn, attr, ppn, gpt_cxy, cycle ); |
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[432] | 371 | #endif |
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| 372 | |
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[1] | 373 | // compute indexes in PT1 and PT2 |
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| 374 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
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| 375 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
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| 376 | |
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[587] | 377 | pt1_ptr = hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
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| 378 | small = attr & GPT_SMALL; |
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[1] | 379 | |
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[432] | 380 | // compute tsar attributes from generic attributes |
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[401] | 381 | tsar_attr = gpt2tsar( attr ); |
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| 382 | |
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[587] | 383 | // build extended pointer on PTE1 = PT1[ix1] |
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| 384 | pte1_xp = XPTR( gpt_cxy , &pt1_ptr[ix1] ); |
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[406] | 385 | |
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[587] | 386 | // get current pte1 value |
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| 387 | pte1 = hal_remote_l32( pte1_xp ); |
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[1] | 388 | |
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[587] | 389 | if( small == 0 ) // map a big page in PT1 |
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[401] | 390 | { |
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[623] | 391 | |
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| 392 | // check PT1 entry not mapped |
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| 393 | assert( (pte1 == 0) , "try to set a big page in a mapped PT1 entry\n" ); |
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| 394 | |
---|
| 395 | // check VPN aligned |
---|
| 396 | assert( (ix2 == 0) , "illegal vpn for a big page\n" ); |
---|
| 397 | |
---|
| 398 | // check PPN aligned |
---|
| 399 | assert( ((ppn & 0x1FF) == 0) , "illegal ppn for a big page\n" ); |
---|
| 400 | |
---|
[587] | 401 | // set the PTE1 value in PT1 |
---|
| 402 | pte1 = (tsar_attr & TSAR_MMU_PTE1_ATTR_MASK) | ((ppn >> 9) & TSAR_MMU_PTE1_PPN_MASK); |
---|
| 403 | hal_remote_s32( pte1_xp , pte1 ); |
---|
[124] | 404 | hal_fence(); |
---|
[587] | 405 | |
---|
| 406 | #if DEBUG_HAL_GPT_SET_PTE |
---|
| 407 | if( DEBUG_HAL_GPT_SET_PTE < cycle ) |
---|
[611] | 408 | printk("\n[%s] : thread[%x,%x] map PTE1 / cxy %x / ix1 %x / pt1 %x / pte1 %x\n", |
---|
[587] | 409 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, ix1, pt1_ptr, pte1 ); |
---|
| 410 | #endif |
---|
| 411 | |
---|
[1] | 412 | return 0; |
---|
| 413 | } |
---|
[587] | 414 | else // map a small page in PT1 & PT2 |
---|
| 415 | { |
---|
| 416 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) // PT1 entry unmapped => map it |
---|
| 417 | { |
---|
| 418 | // allocate one physical page for PT2 |
---|
| 419 | if( gpt_cxy == local_cxy ) |
---|
| 420 | { |
---|
| 421 | kmem_req_t req; |
---|
| 422 | req.type = KMEM_PAGE; |
---|
| 423 | req.size = 0; // 1 small page |
---|
| 424 | req.flags = AF_KERNEL | AF_ZERO; |
---|
| 425 | page = (page_t *)kmem_alloc( &req ); |
---|
| 426 | } |
---|
| 427 | else |
---|
| 428 | { |
---|
| 429 | rpc_pmem_get_pages_client( gpt_cxy , 0 , &page ); |
---|
| 430 | } |
---|
[1] | 431 | |
---|
[406] | 432 | if( page == NULL ) |
---|
| 433 | { |
---|
[587] | 434 | printk("\n[PANIC] in %s : no memory for GPT PT2 / process %x / cluster %x\n", |
---|
| 435 | __FUNCTION__, this->process->pid, gpt_cxy ); |
---|
[406] | 436 | return ENOMEM; |
---|
| 437 | } |
---|
[1] | 438 | |
---|
[406] | 439 | // get the PT2 PPN |
---|
[587] | 440 | page_xp = XPTR( gpt_cxy , page ); |
---|
[406] | 441 | pt2_ppn = ppm_page2ppn( page_xp ); |
---|
[315] | 442 | |
---|
[587] | 443 | // build PTD1 value |
---|
[406] | 444 | pte1 = TSAR_MMU_MAPPED | TSAR_MMU_SMALL | pt2_ppn; |
---|
[1] | 445 | |
---|
[587] | 446 | // set the PTD1 value in PT1 |
---|
| 447 | hal_remote_s32( pte1_xp , pte1 ); |
---|
| 448 | |
---|
| 449 | #if DEBUG_HAL_GPT_SET_PTE |
---|
| 450 | if( DEBUG_HAL_GPT_SET_PTE < cycle ) |
---|
[611] | 451 | printk("\n[%s] : thread[%x,%x] map PTD1 / cxy %x / ix1 %d / pt1 %x / ptd1 %x\n", |
---|
[587] | 452 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, ix1, pt1_ptr, pte1 ); |
---|
| 453 | #endif |
---|
[406] | 454 | } |
---|
[587] | 455 | else // pt1 entry mapped => use it |
---|
[1] | 456 | { |
---|
| 457 | |
---|
[587] | 458 | #if DEBUG_HAL_GPT_SET_PTE |
---|
| 459 | if( DEBUG_HAL_GPT_SET_PTE < cycle ) |
---|
[611] | 460 | printk("\n[%s] : thread[%x,%x] get PTD1 / cxy %x / ix1 %d / pt1 %x / ptd1 %x\n", |
---|
[587] | 461 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, ix1, pt1_ptr, pte1 ); |
---|
| 462 | #endif |
---|
| 463 | |
---|
[1] | 464 | } |
---|
| 465 | |
---|
[406] | 466 | // get PT2 base from pte1 |
---|
| 467 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
[587] | 468 | pt2_ptr = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[1] | 469 | |
---|
[587] | 470 | // set PTE2 in PT2 (in this order) |
---|
| 471 | hal_remote_s32( XPTR( gpt_cxy , &pt2_ptr[2 * ix2 + 1] ) , ppn ); |
---|
| 472 | hal_fence(); |
---|
| 473 | hal_remote_s32( XPTR( gpt_cxy , &pt2_ptr[2 * ix2] ) , tsar_attr ); |
---|
| 474 | hal_fence(); |
---|
[1] | 475 | |
---|
[587] | 476 | #if DEBUG_HAL_GPT_SET_PTE |
---|
| 477 | if( DEBUG_HAL_GPT_SET_PTE < cycle ) |
---|
[611] | 478 | printk("\n[%s] : thread[%x,%x] map PTE2 / cxy %x / ix2 %x / pt2 %x / attr %x / ppn %x\n", |
---|
[587] | 479 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, ix2, pt2_ptr, tsar_attr, ppn ); |
---|
[432] | 480 | #endif |
---|
| 481 | |
---|
[587] | 482 | return 0; |
---|
| 483 | } |
---|
[1] | 484 | } // end of hal_gpt_set_pte() |
---|
| 485 | |
---|
[587] | 486 | //////////////////////////////////////// |
---|
| 487 | void hal_gpt_get_pte( xptr_t gpt_xp, |
---|
[1] | 488 | vpn_t vpn, |
---|
| 489 | uint32_t * attr, |
---|
| 490 | ppn_t * ppn ) |
---|
| 491 | { |
---|
| 492 | uint32_t * pt1; |
---|
| 493 | uint32_t pte1; |
---|
| 494 | |
---|
| 495 | uint32_t * pt2; |
---|
| 496 | ppn_t pt2_ppn; |
---|
| 497 | |
---|
[587] | 498 | // get cluster and local pointer on GPT |
---|
| 499 | cxy_t gpt_cxy = GET_CXY( gpt_xp ); |
---|
| 500 | gpt_t * gpt_ptr = GET_PTR( gpt_xp ); |
---|
| 501 | |
---|
| 502 | // compute indexes in PT1 and PT2 |
---|
[1] | 503 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 504 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
| 505 | |
---|
[587] | 506 | // get PT1 base |
---|
| 507 | pt1 = (uint32_t *)hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
| 508 | |
---|
| 509 | // get pte1 |
---|
| 510 | pte1 = hal_remote_l32( XPTR( gpt_cxy , &pt1[ix1] ) ); |
---|
[1] | 511 | |
---|
[587] | 512 | // check PTE1 mapped |
---|
[401] | 513 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) // PT1 entry not present |
---|
[1] | 514 | { |
---|
| 515 | *attr = 0; |
---|
| 516 | *ppn = 0; |
---|
[587] | 517 | return; |
---|
[1] | 518 | } |
---|
| 519 | |
---|
[587] | 520 | // access GPT |
---|
[401] | 521 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) // it's a PTE1 |
---|
[1] | 522 | { |
---|
[587] | 523 | // get PPN & ATTR from PT1 |
---|
[401] | 524 | *attr = tsar2gpt( TSAR_MMU_ATTR_FROM_PTE1( pte1 ) ); |
---|
[1] | 525 | *ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ) | (vpn & ((1<<TSAR_MMU_IX2_WIDTH)-1)); |
---|
| 526 | } |
---|
[587] | 527 | else // it's a PTD1 |
---|
[1] | 528 | { |
---|
| 529 | // compute PT2 base address |
---|
| 530 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
[587] | 531 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[1] | 532 | |
---|
[587] | 533 | // get PPN & ATTR from PT2 |
---|
| 534 | *ppn = hal_remote_l32( XPTR( gpt_cxy , &pt2[2*ix2+1] ) ) & ((1<<TSAR_MMU_PPN_WIDTH)-1); |
---|
| 535 | *attr = tsar2gpt( hal_remote_l32( XPTR( gpt_cxy , &pt2[2*ix2] ) ) ); |
---|
[1] | 536 | } |
---|
| 537 | } // end hal_gpt_get_pte() |
---|
| 538 | |
---|
| 539 | //////////////////////////////////// |
---|
| 540 | void hal_gpt_reset_pte( gpt_t * gpt, |
---|
| 541 | vpn_t vpn ) |
---|
| 542 | { |
---|
| 543 | uint32_t * pt1; // PT1 base address |
---|
| 544 | uint32_t pte1; // PT1 entry value |
---|
| 545 | |
---|
| 546 | ppn_t pt2_ppn; // PPN of PT2 |
---|
| 547 | uint32_t * pt2; // PT2 base address |
---|
| 548 | |
---|
[391] | 549 | // get ix1 & ix2 indexes |
---|
[1] | 550 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 551 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
| 552 | |
---|
| 553 | // get PTE1 value |
---|
| 554 | pt1 = gpt->ptr; |
---|
| 555 | pte1 = pt1[ix1]; |
---|
| 556 | |
---|
[401] | 557 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) // PT1 entry not present |
---|
[1] | 558 | { |
---|
| 559 | return; |
---|
| 560 | } |
---|
| 561 | |
---|
[401] | 562 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) // it's a PTE1 |
---|
[1] | 563 | { |
---|
| 564 | // unmap the big page |
---|
| 565 | pt1[ix1] = 0; |
---|
[124] | 566 | hal_fence(); |
---|
[1] | 567 | |
---|
| 568 | return; |
---|
| 569 | } |
---|
[391] | 570 | else // it's a PTD1 |
---|
[1] | 571 | { |
---|
| 572 | // compute PT2 base address |
---|
| 573 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
[587] | 574 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[1] | 575 | |
---|
| 576 | // unmap the small page |
---|
[587] | 577 | pt2[2*ix2] = 0; |
---|
[391] | 578 | hal_fence(); |
---|
[1] | 579 | |
---|
| 580 | return; |
---|
| 581 | } |
---|
| 582 | } // end hal_gpt_reset_pte() |
---|
| 583 | |
---|
[624] | 584 | |
---|
| 585 | /* unused until now (march 2019) [AG] |
---|
| 586 | |
---|
[1] | 587 | ////////////////////////////////////// |
---|
[624] | 588 | void hal_gpt_reset_range( gpt * gpt, |
---|
| 589 | vpn_t vpn_min, |
---|
| 590 | vpn_t vpn_max ) |
---|
| 591 | { |
---|
| 592 | vpn_t vpn; // current vpn |
---|
| 593 | |
---|
| 594 | uint32_t * pt1; // PT1 base address |
---|
| 595 | uint32_t pte1; // PT1 entry value |
---|
| 596 | |
---|
| 597 | ppn_t pt2_ppn; // PPN of PT2 |
---|
| 598 | uint32_t * pt2; // PT2 base address |
---|
| 599 | |
---|
| 600 | uint32_t ix1; // index in PT1 |
---|
| 601 | uint32_t ix2; // index in PT2 |
---|
| 602 | |
---|
| 603 | // get PT1 |
---|
| 604 | pt1 = gpt->ptr; |
---|
| 605 | |
---|
| 606 | // initialize current index |
---|
| 607 | vpn = vpn_min; |
---|
| 608 | |
---|
| 609 | // loop on pages |
---|
| 610 | while( vpn <= vpn_max ) |
---|
| 611 | { |
---|
| 612 | // get ix1 index from vpn |
---|
| 613 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 614 | |
---|
| 615 | // get PTE1 |
---|
| 616 | pte1 = pt1[ix1] |
---|
| 617 | |
---|
| 618 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) // PT1[ix1] unmapped |
---|
| 619 | { |
---|
| 620 | // update vpn (next big page) |
---|
| 621 | (vpn = ix1 + 1) << 9; |
---|
| 622 | } |
---|
| 623 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) // it's a PTE1 (big page) |
---|
| 624 | { |
---|
| 625 | // unmap the big page |
---|
| 626 | pt1[ix1] = 0; |
---|
| 627 | hal_fence(); |
---|
| 628 | |
---|
| 629 | // update vpn (next big page) |
---|
| 630 | (vpn = ix1 + 1) << 9; |
---|
| 631 | } |
---|
| 632 | else // it's a PTD1 (small page) |
---|
| 633 | { |
---|
| 634 | // compute PT2 base address |
---|
| 635 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
| 636 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
| 637 | |
---|
| 638 | // get ix2 index from vpn |
---|
| 639 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
| 640 | |
---|
| 641 | // unmap the small page |
---|
| 642 | pt2[2*ix2] = 0; |
---|
| 643 | hal_fence(); |
---|
| 644 | |
---|
| 645 | // update vpn (next small page) |
---|
| 646 | vpn++; |
---|
| 647 | } |
---|
| 648 | } |
---|
| 649 | } // hal_gpt_reset_range() |
---|
| 650 | */ |
---|
| 651 | |
---|
| 652 | ////////////////////////////////////// |
---|
[1] | 653 | error_t hal_gpt_lock_pte( gpt_t * gpt, |
---|
| 654 | vpn_t vpn ) |
---|
| 655 | { |
---|
| 656 | uint32_t * pt1; // PT1 base address |
---|
| 657 | volatile uint32_t * pte1_ptr; // address of PT1 entry |
---|
| 658 | uint32_t pte1; // value of PT1 entry |
---|
| 659 | |
---|
| 660 | uint32_t * pt2; // PT2 base address |
---|
| 661 | ppn_t pt2_ppn; // PPN of PT2 page if missing PT2 |
---|
| 662 | volatile uint32_t * pte2_ptr; // address of PT2 entry |
---|
| 663 | |
---|
| 664 | uint32_t attr; |
---|
| 665 | bool_t atomic; |
---|
| 666 | page_t * page; |
---|
[315] | 667 | xptr_t page_xp; |
---|
[1] | 668 | |
---|
| 669 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); // index in PT1 |
---|
| 670 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); // index in PT2 |
---|
| 671 | |
---|
| 672 | // get the PTE1 value |
---|
| 673 | pt1 = gpt->ptr; |
---|
| 674 | pte1_ptr = &pt1[ix1]; |
---|
| 675 | pte1 = *pte1_ptr; |
---|
| 676 | |
---|
| 677 | // If present, the page must be small |
---|
[401] | 678 | if( ((pte1 & TSAR_MMU_MAPPED) != 0) && ((pte1 & TSAR_MMU_SMALL) == 0) ) |
---|
[1] | 679 | { |
---|
| 680 | printk("\n[ERROR] in %s : try to lock a big page / PT1[%d] = %x\n", |
---|
| 681 | __FUNCTION__ , ix1 , pte1 ); |
---|
| 682 | return EINVAL; |
---|
| 683 | } |
---|
| 684 | |
---|
[401] | 685 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) // missing PT1 entry |
---|
[1] | 686 | { |
---|
| 687 | // allocate one physical page for PT2 |
---|
| 688 | kmem_req_t req; |
---|
| 689 | req.type = KMEM_PAGE; |
---|
| 690 | req.size = 0; // 1 small page |
---|
| 691 | req.flags = AF_KERNEL | AF_ZERO; |
---|
| 692 | page = (page_t *)kmem_alloc( &req ); |
---|
[23] | 693 | |
---|
[1] | 694 | if( page == NULL ) |
---|
| 695 | { |
---|
| 696 | printk("\n[ERROR] in %s : try to set a small page but cannot allocate PT2\n", |
---|
| 697 | __FUNCTION__ ); |
---|
| 698 | return ENOMEM; |
---|
| 699 | } |
---|
[23] | 700 | |
---|
[315] | 701 | page_xp = XPTR( local_cxy , page ); |
---|
| 702 | pt2_ppn = ppm_page2ppn( page_xp ); |
---|
[587] | 703 | pt2 = GET_PTR( ppm_page2base( page_xp ) ); |
---|
[1] | 704 | |
---|
| 705 | // try to set the PT1 entry |
---|
| 706 | do |
---|
| 707 | { |
---|
| 708 | atomic = hal_atomic_cas( (void*)pte1_ptr , 0 , |
---|
[401] | 709 | TSAR_MMU_MAPPED | TSAR_MMU_SMALL | pt2_ppn ); |
---|
[1] | 710 | } |
---|
| 711 | while( (atomic == false) && (*pte1_ptr == 0) ); |
---|
| 712 | |
---|
| 713 | if( atomic == false ) // missing PT2 has been allocate by another core |
---|
| 714 | { |
---|
| 715 | // release the allocated page |
---|
| 716 | ppm_free_pages( page ); |
---|
| 717 | |
---|
| 718 | // read again the PTE1 |
---|
| 719 | pte1 = *pte1_ptr; |
---|
| 720 | |
---|
| 721 | // get the PT2 base address |
---|
| 722 | pt2_ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ); |
---|
[587] | 723 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[1] | 724 | } |
---|
| 725 | } |
---|
| 726 | else |
---|
| 727 | { |
---|
| 728 | // This valid entry must be a PTD1 |
---|
[401] | 729 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) |
---|
[1] | 730 | { |
---|
| 731 | printk("\n[ERROR] in %s : set a small page in a big PT1 entry / PT1[%d] = %x\n", |
---|
| 732 | __FUNCTION__ , ix1 , pte1 ); |
---|
| 733 | return EINVAL; |
---|
| 734 | } |
---|
| 735 | |
---|
| 736 | // compute PPN of PT2 base |
---|
| 737 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
| 738 | |
---|
| 739 | // compute pointer on PT2 base |
---|
[587] | 740 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[1] | 741 | } |
---|
| 742 | |
---|
| 743 | // from here we have the PT2 pointer |
---|
| 744 | |
---|
| 745 | // compute pointer on PTE2 |
---|
| 746 | pte2_ptr = &pt2[2 * ix2]; |
---|
| 747 | |
---|
| 748 | // try to atomically lock the PTE2 until success |
---|
| 749 | do |
---|
| 750 | { |
---|
[401] | 751 | // busy waiting until TSAR_MMU_LOCK == 0 |
---|
[1] | 752 | do |
---|
| 753 | { |
---|
| 754 | attr = *pte2_ptr; |
---|
| 755 | hal_rdbar(); |
---|
| 756 | } |
---|
[401] | 757 | while( (attr & TSAR_MMU_LOCKED) != 0 ); |
---|
[1] | 758 | |
---|
[401] | 759 | atomic = hal_atomic_cas( (void*)pte2_ptr, attr , (attr | TSAR_MMU_LOCKED) ); |
---|
[1] | 760 | } |
---|
| 761 | while( atomic == 0 ); |
---|
| 762 | |
---|
| 763 | return 0; |
---|
[401] | 764 | |
---|
[1] | 765 | } // end hal_gpt_lock_pte() |
---|
| 766 | |
---|
| 767 | //////////////////////////////////////// |
---|
| 768 | error_t hal_gpt_unlock_pte( gpt_t * gpt, |
---|
| 769 | vpn_t vpn ) |
---|
| 770 | { |
---|
| 771 | uint32_t * pt1; // PT1 base address |
---|
| 772 | uint32_t pte1; // value of PT1 entry |
---|
| 773 | |
---|
| 774 | uint32_t * pt2; // PT2 base address |
---|
| 775 | ppn_t pt2_ppn; // PPN of PT2 page if missing PT2 |
---|
| 776 | uint32_t * pte2_ptr; // address of PT2 entry |
---|
| 777 | |
---|
| 778 | uint32_t attr; // PTE2 attribute |
---|
| 779 | |
---|
| 780 | // compute indexes in P1 and PT2 |
---|
| 781 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); // index in PT1 |
---|
| 782 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); // index in PT2 |
---|
| 783 | |
---|
| 784 | // get pointer on PT1 base |
---|
| 785 | pt1 = (uint32_t*)gpt->ptr; |
---|
| 786 | |
---|
| 787 | // get PTE1 |
---|
| 788 | pte1 = pt1[ix1]; |
---|
| 789 | |
---|
| 790 | // check PTE1 present and small page |
---|
[401] | 791 | if( ((pte1 & TSAR_MMU_MAPPED) == 0) || ((pte1 & TSAR_MMU_SMALL) == 0) ) |
---|
[1] | 792 | { |
---|
| 793 | printk("\n[ERROR] in %s : try to unlock a big or undefined page / PT1[%d] = %x\n", |
---|
| 794 | __FUNCTION__ , ix1 , pte1 ); |
---|
| 795 | return EINVAL; |
---|
| 796 | } |
---|
| 797 | |
---|
| 798 | // get pointer on PT2 base |
---|
| 799 | pt2_ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ); |
---|
[587] | 800 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[1] | 801 | |
---|
| 802 | // get pointer on PTE2 |
---|
| 803 | pte2_ptr = &pt2[2 * ix2]; |
---|
| 804 | |
---|
| 805 | // get PTE2_ATTR |
---|
| 806 | attr = *pte2_ptr; |
---|
| 807 | |
---|
| 808 | // check PTE2 present and locked |
---|
[420] | 809 | if( ((attr & TSAR_MMU_MAPPED) == 0) || ((attr & TSAR_MMU_LOCKED) == 0) ) |
---|
[1] | 810 | { |
---|
[401] | 811 | printk("\n[ERROR] in %s : unlock an unlocked/unmapped page / PT1[%d] = %x\n", |
---|
[1] | 812 | __FUNCTION__ , ix1 , pte1 ); |
---|
| 813 | return EINVAL; |
---|
| 814 | } |
---|
| 815 | |
---|
| 816 | // reset GPT_LOCK |
---|
[401] | 817 | *pte2_ptr = attr & ~TSAR_MMU_LOCKED; |
---|
[1] | 818 | |
---|
| 819 | return 0; |
---|
[401] | 820 | |
---|
[1] | 821 | } // end hal_gpt_unlock_pte() |
---|
| 822 | |
---|
[408] | 823 | /////////////////////////////////////////// |
---|
| 824 | error_t hal_gpt_pte_copy( gpt_t * dst_gpt, |
---|
[625] | 825 | vpn_t dst_vpn, |
---|
[408] | 826 | xptr_t src_gpt_xp, |
---|
[625] | 827 | vpn_t src_vpn, |
---|
[408] | 828 | bool_t cow, |
---|
| 829 | ppn_t * ppn, |
---|
| 830 | bool_t * mapped ) |
---|
[23] | 831 | { |
---|
[625] | 832 | uint32_t src_ix1; // index in SRC PT1 |
---|
| 833 | uint32_t src_ix2; // index in SRC PT2 |
---|
[1] | 834 | |
---|
[625] | 835 | uint32_t dst_ix1; // index in DST PT1 |
---|
| 836 | uint32_t dst_ix2; // index in DST PT2 |
---|
| 837 | |
---|
[408] | 838 | cxy_t src_cxy; // SRC GPT cluster |
---|
| 839 | gpt_t * src_gpt; // SRC GPT local pointer |
---|
[1] | 840 | |
---|
[408] | 841 | uint32_t * src_pt1; // local pointer on SRC PT1 |
---|
| 842 | uint32_t * dst_pt1; // local pointer on DST PT1 |
---|
| 843 | uint32_t * src_pt2; // local pointer on SRC PT2 |
---|
| 844 | uint32_t * dst_pt2; // local pointer on DST PT2 |
---|
| 845 | |
---|
[587] | 846 | kmem_req_t req; // for PT2 allocation |
---|
[407] | 847 | |
---|
| 848 | uint32_t src_pte1; |
---|
| 849 | uint32_t dst_pte1; |
---|
| 850 | |
---|
[408] | 851 | uint32_t src_pte2_attr; |
---|
| 852 | uint32_t src_pte2_ppn; |
---|
[1] | 853 | |
---|
[23] | 854 | page_t * page; |
---|
[315] | 855 | xptr_t page_xp; |
---|
[1] | 856 | |
---|
[23] | 857 | ppn_t src_pt2_ppn; |
---|
| 858 | ppn_t dst_pt2_ppn; |
---|
[1] | 859 | |
---|
[587] | 860 | // get remote src_gpt cluster and local pointer |
---|
| 861 | src_cxy = GET_CXY( src_gpt_xp ); |
---|
| 862 | src_gpt = GET_PTR( src_gpt_xp ); |
---|
| 863 | |
---|
| 864 | #if DEBUG_HAL_GPT_COPY |
---|
| 865 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
| 866 | thread_t * this = CURRENT_THREAD; |
---|
| 867 | if( DEBUG_HAL_GPT_COPY < cycle ) |
---|
[625] | 868 | printk("\n[%s] : thread[%x,%x] enter / src_cxy %x / dst_cxy %x / cycle %d\n", |
---|
| 869 | __FUNCTION__, this->process->pid, this->trdid, src_cxy, local_cxy, cycle ); |
---|
[432] | 870 | #endif |
---|
[407] | 871 | |
---|
[408] | 872 | // get remote src_gpt cluster and local pointer |
---|
| 873 | src_cxy = GET_CXY( src_gpt_xp ); |
---|
[587] | 874 | src_gpt = GET_PTR( src_gpt_xp ); |
---|
[407] | 875 | |
---|
[408] | 876 | // get remote src_pt1 and local dst_pt1 |
---|
| 877 | src_pt1 = (uint32_t *)hal_remote_lpt( XPTR( src_cxy , &src_gpt->ptr ) ); |
---|
[23] | 878 | dst_pt1 = (uint32_t *)dst_gpt->ptr; |
---|
[1] | 879 | |
---|
[408] | 880 | // check src_pt1 and dst_pt1 existence |
---|
[492] | 881 | assert( (src_pt1 != NULL) , "src_pt1 does not exist\n"); |
---|
| 882 | assert( (dst_pt1 != NULL) , "dst_pt1 does not exist\n"); |
---|
[407] | 883 | |
---|
[625] | 884 | // compute SRC indexes |
---|
| 885 | src_ix1 = TSAR_MMU_IX1_FROM_VPN( src_vpn ); |
---|
| 886 | src_ix2 = TSAR_MMU_IX2_FROM_VPN( src_vpn ); |
---|
[407] | 887 | |
---|
[625] | 888 | // compute DST indexes |
---|
| 889 | dst_ix1 = TSAR_MMU_IX1_FROM_VPN( dst_vpn ); |
---|
| 890 | dst_ix2 = TSAR_MMU_IX2_FROM_VPN( dst_vpn ); |
---|
| 891 | |
---|
[408] | 892 | // get src_pte1 |
---|
[625] | 893 | src_pte1 = hal_remote_l32( XPTR( src_cxy , &src_pt1[src_ix1] ) ); |
---|
[407] | 894 | |
---|
[408] | 895 | // do nothing if src_pte1 not MAPPED or not SMALL |
---|
| 896 | if( (src_pte1 & TSAR_MMU_MAPPED) && (src_pte1 & TSAR_MMU_SMALL) ) |
---|
| 897 | { |
---|
| 898 | // get dst_pt1 entry |
---|
[625] | 899 | dst_pte1 = dst_pt1[dst_ix1]; |
---|
[407] | 900 | |
---|
[408] | 901 | // map dst_pte1 if required |
---|
| 902 | if( (dst_pte1 & TSAR_MMU_MAPPED) == 0 ) |
---|
| 903 | { |
---|
| 904 | // allocate one physical page for a new PT2 |
---|
| 905 | req.type = KMEM_PAGE; |
---|
| 906 | req.size = 0; // 1 small page |
---|
| 907 | req.flags = AF_KERNEL | AF_ZERO; |
---|
| 908 | page = (page_t *)kmem_alloc( &req ); |
---|
[407] | 909 | |
---|
[408] | 910 | if( page == NULL ) |
---|
| 911 | { |
---|
| 912 | printk("\n[ERROR] in %s : cannot allocate PT2\n", __FUNCTION__ ); |
---|
| 913 | return -1; |
---|
| 914 | } |
---|
[407] | 915 | |
---|
[408] | 916 | // build extended pointer on page descriptor |
---|
| 917 | page_xp = XPTR( local_cxy , page ); |
---|
[407] | 918 | |
---|
[408] | 919 | // get PPN for this new PT2 |
---|
| 920 | dst_pt2_ppn = (ppn_t)ppm_page2ppn( page_xp ); |
---|
[407] | 921 | |
---|
[408] | 922 | // build the new dst_pte1 |
---|
| 923 | dst_pte1 = TSAR_MMU_MAPPED | TSAR_MMU_SMALL | dst_pt2_ppn; |
---|
[407] | 924 | |
---|
[408] | 925 | // register it in DST_GPT |
---|
[625] | 926 | dst_pt1[dst_ix1] = dst_pte1; |
---|
[408] | 927 | } |
---|
[407] | 928 | |
---|
[408] | 929 | // get pointer on src_pt2 |
---|
| 930 | src_pt2_ppn = (ppn_t)TSAR_MMU_PTBA_FROM_PTE1( src_pte1 ); |
---|
[587] | 931 | src_pt2 = GET_PTR( ppm_ppn2base( src_pt2_ppn ) ); |
---|
[407] | 932 | |
---|
[408] | 933 | // get pointer on dst_pt2 |
---|
| 934 | dst_pt2_ppn = (ppn_t)TSAR_MMU_PTBA_FROM_PTE1( dst_pte1 ); |
---|
[587] | 935 | dst_pt2 = GET_PTR( ppm_ppn2base( dst_pt2_ppn ) ); |
---|
[407] | 936 | |
---|
[408] | 937 | // get attr and ppn from SRC_PT2 |
---|
[625] | 938 | src_pte2_attr = hal_remote_l32( XPTR( src_cxy , &src_pt2[2 * src_ix2] ) ); |
---|
| 939 | src_pte2_ppn = hal_remote_l32( XPTR( src_cxy , &src_pt2[2 * src_ix2 + 1] ) ); |
---|
[407] | 940 | |
---|
[408] | 941 | // do nothing if src_pte2 not MAPPED |
---|
| 942 | if( (src_pte2_attr & TSAR_MMU_MAPPED) != 0 ) |
---|
| 943 | { |
---|
| 944 | // set PPN in DST PTE2 |
---|
[625] | 945 | dst_pt2[2 * dst_ix2 + 1] = src_pte2_ppn; |
---|
[408] | 946 | |
---|
| 947 | // set attributes in DST PTE2 |
---|
| 948 | if( cow && (src_pte2_attr & TSAR_MMU_WRITABLE) ) |
---|
[407] | 949 | { |
---|
[625] | 950 | dst_pt2[2 * dst_ix2] = (src_pte2_attr | TSAR_MMU_COW) & (~TSAR_MMU_WRITABLE); |
---|
[408] | 951 | } |
---|
| 952 | else |
---|
| 953 | { |
---|
[625] | 954 | dst_pt2[2 * dst_ix2] = src_pte2_attr; |
---|
[408] | 955 | } |
---|
[407] | 956 | |
---|
[408] | 957 | // return "successfully copied" |
---|
| 958 | *mapped = true; |
---|
| 959 | *ppn = src_pte2_ppn; |
---|
| 960 | |
---|
[587] | 961 | #if DEBUG_HAL_GPT_COPY |
---|
[432] | 962 | cycle = (uint32_t)hal_get_cycles; |
---|
[587] | 963 | if( DEBUG_HAL_GPT_COPY < cycle ) |
---|
[625] | 964 | printk("\n[%s] : thread[%x,%x] exit / copy done for src_vpn %x / dst_vpn %x / cycle %d\n", |
---|
| 965 | __FUNCTION__, this->process->pid, this->trdid, src_vpn, dst_vpn, cycle ); |
---|
[432] | 966 | #endif |
---|
[407] | 967 | |
---|
[408] | 968 | hal_fence(); |
---|
[407] | 969 | |
---|
[408] | 970 | return 0; |
---|
| 971 | } // end if PTE2 mapped |
---|
| 972 | } // end if PTE1 mapped |
---|
| 973 | |
---|
| 974 | // return "nothing done" |
---|
| 975 | *mapped = false; |
---|
| 976 | *ppn = 0; |
---|
[432] | 977 | |
---|
[587] | 978 | #if DEBUG_HAL_GPT_COPY |
---|
[432] | 979 | cycle = (uint32_t)hal_get_cycles; |
---|
[587] | 980 | if( DEBUG_HAL_GPT_COPY < cycle ) |
---|
[625] | 981 | printk("\n[%s] : thread[%x,%x] exit / nothing done / cycle %d\n", |
---|
| 982 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
---|
[432] | 983 | #endif |
---|
[408] | 984 | |
---|
[407] | 985 | hal_fence(); |
---|
| 986 | |
---|
| 987 | return 0; |
---|
| 988 | |
---|
[408] | 989 | } // end hal_gpt_pte_copy() |
---|
[407] | 990 | |
---|
[408] | 991 | ////////////////////////////////////////// |
---|
| 992 | bool_t hal_gpt_pte_is_mapped( gpt_t * gpt, |
---|
| 993 | vpn_t vpn ) |
---|
| 994 | { |
---|
| 995 | uint32_t * pt1; |
---|
| 996 | uint32_t pte1; |
---|
| 997 | uint32_t pte2_attr; |
---|
| 998 | |
---|
| 999 | uint32_t * pt2; |
---|
| 1000 | ppn_t pt2_ppn; |
---|
| 1001 | |
---|
| 1002 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 1003 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
| 1004 | |
---|
| 1005 | // get PTE1 value |
---|
| 1006 | pt1 = gpt->ptr; |
---|
| 1007 | pte1 = pt1[ix1]; |
---|
| 1008 | |
---|
| 1009 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) return false; |
---|
| 1010 | |
---|
| 1011 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) return false; |
---|
| 1012 | |
---|
| 1013 | // compute PT2 base address |
---|
| 1014 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
[587] | 1015 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[408] | 1016 | |
---|
| 1017 | // get pte2_attr |
---|
| 1018 | pte2_attr = pt2[2*ix2]; |
---|
| 1019 | |
---|
| 1020 | if( (pte2_attr & TSAR_MMU_MAPPED) == 0 ) return false; |
---|
| 1021 | else return true; |
---|
| 1022 | |
---|
| 1023 | } // end hal_gpt_pte_is_mapped() |
---|
| 1024 | |
---|
[407] | 1025 | /////////////////////////////////////// |
---|
| 1026 | bool_t hal_gpt_pte_is_cow( gpt_t * gpt, |
---|
| 1027 | vpn_t vpn ) |
---|
| 1028 | { |
---|
| 1029 | uint32_t * pt1; |
---|
| 1030 | uint32_t pte1; |
---|
[408] | 1031 | uint32_t pte2_attr; |
---|
[407] | 1032 | |
---|
| 1033 | uint32_t * pt2; |
---|
| 1034 | ppn_t pt2_ppn; |
---|
| 1035 | |
---|
| 1036 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 1037 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
| 1038 | |
---|
| 1039 | // get PTE1 value |
---|
| 1040 | pt1 = gpt->ptr; |
---|
| 1041 | pte1 = pt1[ix1]; |
---|
| 1042 | |
---|
[408] | 1043 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) return false; |
---|
[407] | 1044 | |
---|
[408] | 1045 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) return false; |
---|
[407] | 1046 | |
---|
[408] | 1047 | // compute PT2 base address |
---|
| 1048 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
[587] | 1049 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[408] | 1050 | |
---|
| 1051 | // get pte2_attr |
---|
| 1052 | pte2_attr = pt2[2*ix2]; |
---|
| 1053 | |
---|
| 1054 | if( (pte2_attr & TSAR_MMU_MAPPED) == 0 ) return false; |
---|
| 1055 | |
---|
| 1056 | if( (pte2_attr & TSAR_MMU_COW) == 0 ) return false; |
---|
| 1057 | else return true; |
---|
| 1058 | |
---|
[407] | 1059 | } // end hal_gpt_pte_is_cow() |
---|
| 1060 | |
---|
[408] | 1061 | ///////////////////////////////////////// |
---|
[432] | 1062 | void hal_gpt_set_cow( xptr_t gpt_xp, |
---|
| 1063 | vpn_t vpn_base, |
---|
| 1064 | vpn_t vpn_size ) |
---|
[408] | 1065 | { |
---|
| 1066 | cxy_t gpt_cxy; |
---|
| 1067 | gpt_t * gpt_ptr; |
---|
[407] | 1068 | |
---|
[408] | 1069 | vpn_t vpn; |
---|
[407] | 1070 | |
---|
[408] | 1071 | uint32_t ix1; |
---|
| 1072 | uint32_t ix2; |
---|
[407] | 1073 | |
---|
[408] | 1074 | uint32_t * pt1; |
---|
| 1075 | uint32_t pte1; |
---|
[407] | 1076 | |
---|
[408] | 1077 | uint32_t * pt2; |
---|
| 1078 | ppn_t pt2_ppn; |
---|
[432] | 1079 | uint32_t attr; |
---|
[407] | 1080 | |
---|
[408] | 1081 | // get GPT cluster and local pointer |
---|
| 1082 | gpt_cxy = GET_CXY( gpt_xp ); |
---|
[587] | 1083 | gpt_ptr = GET_PTR( gpt_xp ); |
---|
[407] | 1084 | |
---|
[408] | 1085 | // get local PT1 pointer |
---|
| 1086 | pt1 = (uint32_t *)hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
[407] | 1087 | |
---|
[408] | 1088 | // loop on pages |
---|
| 1089 | for( vpn = vpn_base ; vpn < (vpn_base + vpn_size) ; vpn++ ) |
---|
| 1090 | { |
---|
| 1091 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 1092 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
[407] | 1093 | |
---|
[408] | 1094 | // get PTE1 value |
---|
[570] | 1095 | pte1 = hal_remote_l32( XPTR( gpt_cxy , &pt1[ix1] ) ); |
---|
[407] | 1096 | |
---|
[408] | 1097 | // only MAPPED & SMALL PTEs are modified |
---|
| 1098 | if( (pte1 & TSAR_MMU_MAPPED) && (pte1 & TSAR_MMU_SMALL) ) |
---|
| 1099 | { |
---|
| 1100 | // compute PT2 base address |
---|
| 1101 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
[587] | 1102 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[407] | 1103 | |
---|
[492] | 1104 | assert( (GET_CXY( ppm_ppn2base( pt2_ppn ) ) == gpt_cxy ), |
---|
[408] | 1105 | "PT2 and PT1 must be in the same cluster\n"); |
---|
| 1106 | |
---|
| 1107 | // get current PTE2 attributes |
---|
[570] | 1108 | attr = hal_remote_l32( XPTR( gpt_cxy , &pt2[2*ix2] ) ); |
---|
[408] | 1109 | |
---|
| 1110 | // only MAPPED PTEs are modified |
---|
[432] | 1111 | if( attr & TSAR_MMU_MAPPED ) |
---|
[23] | 1112 | { |
---|
[432] | 1113 | attr = (attr | TSAR_MMU_COW) & (~TSAR_MMU_WRITABLE); |
---|
[570] | 1114 | hal_remote_s32( XPTR( gpt_cxy , &pt2[2*ix2] ) , attr ); |
---|
[432] | 1115 | } |
---|
| 1116 | } |
---|
[408] | 1117 | } // end loop on pages |
---|
[23] | 1118 | |
---|
[432] | 1119 | } // end hal_gpt_set_cow() |
---|
[315] | 1120 | |
---|
[408] | 1121 | ////////////////////////////////////////// |
---|
| 1122 | void hal_gpt_update_pte( xptr_t gpt_xp, |
---|
| 1123 | vpn_t vpn, |
---|
| 1124 | uint32_t attr, // generic GPT attributes |
---|
| 1125 | ppn_t ppn ) |
---|
| 1126 | { |
---|
| 1127 | uint32_t * pt1; // PT1 base addres |
---|
| 1128 | uint32_t pte1; // PT1 entry value |
---|
[23] | 1129 | |
---|
[408] | 1130 | ppn_t pt2_ppn; // PPN of PT2 |
---|
| 1131 | uint32_t * pt2; // PT2 base address |
---|
[23] | 1132 | |
---|
[408] | 1133 | uint32_t ix1; // index in PT1 |
---|
| 1134 | uint32_t ix2; // index in PT2 |
---|
[23] | 1135 | |
---|
[408] | 1136 | uint32_t tsar_attr; // PTE attributes for TSAR MMU |
---|
[23] | 1137 | |
---|
[408] | 1138 | // check attr argument MAPPED and SMALL |
---|
| 1139 | if( (attr & GPT_MAPPED) == 0 ) return; |
---|
| 1140 | if( (attr & GPT_SMALL ) == 0 ) return; |
---|
[23] | 1141 | |
---|
[408] | 1142 | // get cluster and local pointer on remote GPT |
---|
| 1143 | cxy_t gpt_cxy = GET_CXY( gpt_xp ); |
---|
[587] | 1144 | gpt_t * gpt_ptr = GET_PTR( gpt_xp ); |
---|
[23] | 1145 | |
---|
[408] | 1146 | // compute indexes in PT1 and PT2 |
---|
| 1147 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 1148 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
[23] | 1149 | |
---|
[408] | 1150 | // get PT1 base |
---|
| 1151 | pt1 = (uint32_t *)hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
[23] | 1152 | |
---|
[408] | 1153 | // compute tsar_attr from generic attributes |
---|
| 1154 | tsar_attr = gpt2tsar( attr ); |
---|
[23] | 1155 | |
---|
[408] | 1156 | // get PTE1 value |
---|
[570] | 1157 | pte1 = hal_remote_l32( XPTR( gpt_cxy , &pt1[ix1] ) ); |
---|
[23] | 1158 | |
---|
[408] | 1159 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) return; |
---|
| 1160 | if( (pte1 & TSAR_MMU_SMALL ) == 0 ) return; |
---|
| 1161 | |
---|
| 1162 | // get PT2 base from PTE1 |
---|
| 1163 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
[587] | 1164 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[408] | 1165 | |
---|
| 1166 | // set PTE2 in this order |
---|
[570] | 1167 | hal_remote_s32( XPTR( gpt_cxy, &pt2[2 * ix2 + 1] ) , ppn ); |
---|
[408] | 1168 | hal_fence(); |
---|
[570] | 1169 | hal_remote_s32( XPTR( gpt_cxy, &pt2[2 * ix2] ) , tsar_attr ); |
---|
[408] | 1170 | hal_fence(); |
---|
| 1171 | |
---|
| 1172 | } // end hal_gpt_update_pte() |
---|
| 1173 | |
---|