1 | /* |
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2 | * hal_gpt.c - implementation of the Generic Page Table API for TSAR-MIPS32 |
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3 | * |
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4 | * Author Alain Greiner (2016) |
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5 | * |
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6 | * Copyright (c) UPMC Sorbonne Universites |
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7 | * |
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8 | * This file is part of ALMOS-MKH. |
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9 | * |
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10 | * ALMOS-MKH.is free software; you can redistribute it and/or modify it |
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11 | * under the terms of the GNU General Public License as published by |
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12 | * the Free Software Foundation; version 2.0 of the License. |
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13 | * |
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14 | * ALMOS-MKH.is distributed in the hope that it will be useful, but |
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15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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17 | * General Public License for more details. |
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18 | * |
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19 | * You should have received a copy of the GNU General Public License |
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20 | * along with ALMOS-MKH.; if not, write to the Free Software Foundation, |
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21 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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22 | */ |
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23 | |
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24 | #include <hal_types.h> |
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25 | #include <hal_gpt.h> |
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26 | #include <hal_special.h> |
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27 | #include <printk.h> |
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28 | #include <bits.h> |
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29 | #include <process.h> |
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30 | #include <kmem.h> |
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31 | #include <thread.h> |
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32 | #include <cluster.h> |
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33 | #include <ppm.h> |
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34 | #include <page.h> |
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35 | |
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36 | //////////////////////////////////////////////////////////////////////////////////////// |
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37 | // This define the masks for the TSAR MMU PTE attributes (from TSAR MMU specification) |
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38 | //////////////////////////////////////////////////////////////////////////////////////// |
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39 | |
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40 | #define TSAR_MMU_MAPPED 0x80000000 |
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41 | #define TSAR_MMU_SMALL 0x40000000 |
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42 | #define TSAR_MMU_LOCAL 0x20000000 |
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43 | #define TSAR_MMU_REMOTE 0x10000000 |
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44 | #define TSAR_MMU_CACHABLE 0x08000000 |
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45 | #define TSAR_MMU_WRITABLE 0x04000000 |
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46 | #define TSAR_MMU_EXECUTABLE 0x02000000 |
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47 | #define TSAR_MMU_USER 0x01000000 |
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48 | #define TSAR_MMU_GLOBAL 0x00800000 |
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49 | #define TSAR_MMU_DIRTY 0x00400000 |
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50 | |
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51 | #define TSAR_MMU_COW 0x00000001 // only for small pages |
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52 | #define TSAR_MMU_SWAP 0x00000004 // only for small pages |
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53 | #define TSAR_MMU_LOCKED 0x00000008 // only for small pages |
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54 | |
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55 | //////////////////////////////////////////////////////////////////////////////////////// |
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56 | // TSAR MMU related macros (from the TSAR MMU specification) |
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57 | // - IX1 on 11 bits |
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58 | // - IX2 on 9 bits |
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59 | // - PPN on 28 bits |
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60 | //////////////////////////////////////////////////////////////////////////////////////// |
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61 | |
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62 | #define TSAR_MMU_IX1_WIDTH 11 |
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63 | #define TSAR_MMU_IX2_WIDTH 9 |
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64 | #define TSAR_MMU_PPN_WIDTH 28 |
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65 | |
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66 | #define TSAR_MMU_PTE1_ATTR_MASK 0xFFC00000 |
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67 | #define TSAR_MMU_PTE1_PPN_MASK 0x0007FFFF |
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68 | |
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69 | #define TSAR_MMU_IX1_FROM_VPN( vpn ) ((vpn >> 9) & 0x7FF) |
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70 | #define TSAR_MMU_IX2_FROM_VPN( vpn ) (vpn & 0x1FF) |
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71 | |
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72 | #define TSAR_MMU_PTBA_FROM_PTE1( pte1 ) (pte1 & 0x0FFFFFFF) |
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73 | #define TSAR_MMU_PPN_FROM_PTE1( pte1 ) ((pte1 & 0x0007FFFF)<<9) |
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74 | #define TSAR_MMU_ATTR_FROM_PTE1( pte1 ) (pte1 & 0xFFC00000) |
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75 | |
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76 | #define TSAR_MMU_PPN_FROM_PTE2( pte2 ) (pte2 & 0x0FFFFFFF) |
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77 | #define TSAR_MMU_ATTR_FROM_PTE2( pte2 ) (pte2 & 0xFFC000FF) |
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78 | |
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79 | |
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80 | /////////////////////////////////////////////////////////////////////////////////////// |
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81 | // This static function translates the GPT attributes to the TSAR attributes |
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82 | /////////////////////////////////////////////////////////////////////////////////////// |
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83 | static inline uint32_t gpt2tsar( uint32_t gpt_attr ) |
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84 | { |
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85 | uint32_t tsar_attr = 0; |
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86 | |
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87 | if( gpt_attr & GPT_MAPPED ) tsar_attr |= TSAR_MMU_MAPPED; |
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88 | if( gpt_attr & GPT_SMALL ) tsar_attr |= TSAR_MMU_SMALL; |
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89 | if( gpt_attr & GPT_WRITABLE ) tsar_attr |= TSAR_MMU_WRITABLE; |
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90 | if( gpt_attr & GPT_EXECUTABLE ) tsar_attr |= TSAR_MMU_EXECUTABLE; |
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91 | if( gpt_attr & GPT_CACHABLE ) tsar_attr |= TSAR_MMU_CACHABLE; |
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92 | if( gpt_attr & GPT_USER ) tsar_attr |= TSAR_MMU_USER; |
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93 | if( gpt_attr & GPT_DIRTY ) tsar_attr |= TSAR_MMU_DIRTY; |
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94 | if( gpt_attr & GPT_ACCESSED ) tsar_attr |= TSAR_MMU_LOCAL; |
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95 | if( gpt_attr & GPT_GLOBAL ) tsar_attr |= TSAR_MMU_GLOBAL; |
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96 | if( gpt_attr & GPT_COW ) tsar_attr |= TSAR_MMU_COW; |
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97 | if( gpt_attr & GPT_SWAP ) tsar_attr |= TSAR_MMU_SWAP; |
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98 | if( gpt_attr & GPT_LOCKED ) tsar_attr |= TSAR_MMU_LOCKED; |
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99 | |
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100 | return tsar_attr; |
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101 | } |
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102 | |
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103 | /////////////////////////////////////////////////////////////////////////////////////// |
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104 | // This static function translates the TSAR attributes to the GPT attributes |
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105 | /////////////////////////////////////////////////////////////////////////////////////// |
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106 | static inline uint32_t tsar2gpt( uint32_t tsar_attr ) |
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107 | { |
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108 | uint32_t gpt_attr = 0; |
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109 | |
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110 | if( tsar_attr & TSAR_MMU_MAPPED ) gpt_attr |= GPT_MAPPED; |
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111 | if( tsar_attr & TSAR_MMU_MAPPED ) gpt_attr |= GPT_READABLE; |
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112 | if( tsar_attr & TSAR_MMU_SMALL ) gpt_attr |= GPT_SMALL; |
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113 | if( tsar_attr & TSAR_MMU_WRITABLE ) gpt_attr |= GPT_WRITABLE; |
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114 | if( tsar_attr & TSAR_MMU_EXECUTABLE ) gpt_attr |= GPT_EXECUTABLE; |
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115 | if( tsar_attr & TSAR_MMU_CACHABLE ) gpt_attr |= GPT_CACHABLE; |
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116 | if( tsar_attr & TSAR_MMU_USER ) gpt_attr |= GPT_USER; |
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117 | if( tsar_attr & TSAR_MMU_DIRTY ) gpt_attr |= GPT_DIRTY; |
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118 | if( tsar_attr & TSAR_MMU_LOCAL ) gpt_attr |= GPT_ACCESSED; |
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119 | if( tsar_attr & TSAR_MMU_REMOTE ) gpt_attr |= GPT_ACCESSED; |
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120 | if( tsar_attr & TSAR_MMU_GLOBAL ) gpt_attr |= GPT_GLOBAL; |
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121 | if( tsar_attr & TSAR_MMU_COW ) gpt_attr |= GPT_COW; |
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122 | if( tsar_attr & TSAR_MMU_SWAP ) gpt_attr |= GPT_SWAP; |
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123 | if( tsar_attr & TSAR_MMU_LOCKED ) gpt_attr |= GPT_LOCKED; |
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124 | |
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125 | return gpt_attr; |
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126 | } |
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127 | |
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128 | ///////////////////////////////////// |
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129 | error_t hal_gpt_create( gpt_t * gpt ) |
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130 | { |
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131 | page_t * page; |
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132 | xptr_t page_xp; |
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133 | |
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134 | // check page size |
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135 | if( CONFIG_PPM_PAGE_SIZE != 4096 ) |
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136 | { |
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137 | printk("\n[PANIC] in %s : For TSAR, the page must be 4 Kbytes\n", __FUNCTION__ ); |
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138 | hal_core_sleep(); |
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139 | } |
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140 | |
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141 | // allocates 2 physical pages for PT1 |
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142 | kmem_req_t req; |
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143 | req.type = KMEM_PAGE; |
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144 | req.size = 1; // 2 small pages |
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145 | req.flags = AF_KERNEL | AF_ZERO; |
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146 | page = (page_t *)kmem_alloc( &req ); |
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147 | |
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148 | if( page == NULL ) |
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149 | { |
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150 | printk("\n[ERROR] in %s : cannot allocate physical memory for PT1\n", __FUNCTION__ ); |
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151 | return ENOMEM; |
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152 | } |
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153 | |
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154 | // initialize generic page table descriptor |
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155 | page_xp = XPTR( local_cxy , page ); |
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156 | |
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157 | gpt->ptr = GET_PTR( ppm_page2base( page_xp ) ); |
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158 | gpt->ppn = ppm_page2ppn( page_xp ); |
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159 | gpt->page = GET_PTR( page_xp ); |
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160 | |
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161 | return 0; |
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162 | } // end hal_gpt_create() |
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163 | |
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164 | |
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165 | /////////////////////////////////// |
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166 | void hal_gpt_destroy( gpt_t * gpt ) |
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167 | { |
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168 | uint32_t ix1; |
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169 | uint32_t ix2; |
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170 | uint32_t * pt1; |
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171 | uint32_t pte1; |
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172 | ppn_t pt2_ppn; |
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173 | uint32_t * pt2; |
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174 | uint32_t attr; |
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175 | vpn_t vpn; |
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176 | kmem_req_t req; |
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177 | bool_t is_ref; |
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178 | |
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179 | // get pointer on calling process |
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180 | process_t * process = CURRENT_THREAD->process; |
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181 | |
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182 | // compute is_ref |
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183 | is_ref = ( GET_CXY( process->ref_xp ) == local_cxy ); |
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184 | |
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185 | // get pointer on PT1 |
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186 | pt1 = (uint32_t *)gpt->ptr; |
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187 | |
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188 | // scan the PT1 |
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189 | for( ix1 = 0 ; ix1 < 2048 ; ix1++ ) |
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190 | { |
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191 | pte1 = pt1[ix1]; |
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192 | if( (pte1 & TSAR_MMU_MAPPED) != 0 ) // PTE1 valid |
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193 | { |
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194 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) // BIG page |
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195 | { |
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196 | if( (pte1 & TSAR_MMU_USER) != 0 ) |
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197 | { |
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198 | // warning message |
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199 | printk("\n[WARNING] in %s : found an USER BIG page / ix1 = %d\n", |
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200 | __FUNCTION__ , ix1 ); |
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201 | |
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202 | // release the big physical page if reference cluster |
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203 | if( is_ref ) |
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204 | { |
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205 | vpn = (vpn_t)(ix1 << TSAR_MMU_IX2_WIDTH); |
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206 | hal_gpt_reset_pte( gpt , vpn ); |
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207 | } |
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208 | } |
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209 | } |
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210 | else // SMALL page |
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211 | { |
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212 | // get local pointer on PT2 |
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213 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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214 | xptr_t base_xp = ppm_ppn2base( pt2_ppn ); |
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215 | pt2 = (uint32_t *)GET_PTR( base_xp ); |
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216 | |
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217 | // scan the PT2 to release all entries VALID and USER if reference cluster |
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218 | if( is_ref ) |
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219 | { |
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220 | for( ix2 = 0 ; ix2 < 512 ; ix2++ ) |
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221 | { |
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222 | attr = TSAR_MMU_ATTR_FROM_PTE2( pt2[2 * ix2] ); |
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223 | if( ((attr & TSAR_MMU_MAPPED) != 0 ) && ((attr & TSAR_MMU_USER) != 0) ) |
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224 | { |
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225 | // release the physical page |
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226 | vpn = (vpn_t)((ix1 << TSAR_MMU_IX2_WIDTH) | ix2); |
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227 | hal_gpt_reset_pte( gpt , vpn ); |
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228 | } |
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229 | } |
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230 | } |
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231 | |
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232 | // release the PT2 |
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233 | req.type = KMEM_PAGE; |
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234 | req.ptr = GET_PTR( ppm_base2page( XPTR(local_cxy , pt2 ) ) ); |
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235 | kmem_free( &req ); |
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236 | } |
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237 | } |
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238 | } |
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239 | |
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240 | // release the PT1 |
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241 | req.type = KMEM_PAGE; |
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242 | req.ptr = GET_PTR( ppm_base2page( XPTR(local_cxy , pt1 ) ) ); |
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243 | kmem_free( &req ); |
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244 | |
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245 | } // end hal_gpt_destroy() |
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246 | |
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247 | ///////////////////////////////// |
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248 | void hal_gpt_print( gpt_t * gpt ) |
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249 | { |
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250 | uint32_t ix1; |
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251 | uint32_t ix2; |
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252 | uint32_t * pt1; |
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253 | uint32_t pte1; |
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254 | ppn_t pt2_ppn; |
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255 | uint32_t * pt2; |
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256 | uint32_t pte2_attr; |
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257 | ppn_t pte2_ppn; |
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258 | |
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259 | printk("*** Page Table for process %x in cluster %x ***\n", |
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260 | CURRENT_THREAD->process->pid , local_cxy ); |
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261 | |
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262 | pt1 = (uint32_t *)gpt->ptr; |
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263 | |
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264 | // scan the PT1 |
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265 | for( ix1 = 0 ; ix1 < 2048 ; ix1++ ) |
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266 | { |
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267 | pte1 = pt1[ix1]; |
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268 | if( (pte1 & TSAR_MMU_MAPPED) != 0 ) |
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269 | { |
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270 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) // BIG page |
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271 | { |
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272 | printk(" - BIG : pt1[%d] = %x\n", ix1 , pte1 ); |
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273 | } |
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274 | else // SMALL pages |
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275 | { |
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276 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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277 | xptr_t base_xp = ppm_ppn2base ( pt2_ppn ); |
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278 | pt2 = (uint32_t *)GET_PTR( base_xp ); |
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279 | |
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280 | // scan the PT2 |
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281 | for( ix2 = 0 ; ix2 < 512 ; ix2++ ) |
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282 | { |
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283 | pte2_attr = TSAR_MMU_ATTR_FROM_PTE2( pt2[2 * ix2] ); |
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284 | pte2_ppn = TSAR_MMU_PPN_FROM_PTE2( pt2[2 * ix2 + 1] ); |
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285 | if( (pte2_attr & TSAR_MMU_MAPPED) != 0 ) |
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286 | { |
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287 | printk(" - SMALL : pt1[%d] = %x / pt2[%d] / pt2[%d]\n", |
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288 | ix1 , pt1[ix1] , 2*ix2 , pte2_attr , 2*ix2+1 , pte2_ppn ); |
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289 | } |
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290 | } |
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291 | } |
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292 | } |
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293 | } |
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294 | } // end hal_gpt_print() |
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295 | |
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296 | |
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297 | /////////////////////////////////////// |
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298 | error_t hal_gpt_set_pte( gpt_t * gpt, |
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299 | vpn_t vpn, |
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300 | ppn_t ppn, |
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301 | uint32_t attr ) // generic GPT attributes |
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302 | { |
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303 | uint32_t * pt1; // virtual base addres of PT1 |
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304 | volatile uint32_t * pte1_ptr; // pointer on PT1 entry |
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305 | uint32_t pte1; // PT1 entry value |
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306 | |
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307 | ppn_t pt2_ppn; // PPN of PT2 |
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308 | uint32_t * pt2; // virtual base address of PT2 |
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309 | |
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310 | uint32_t small; // requested PTE is for a small page |
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311 | bool_t atomic; |
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312 | |
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313 | page_t * page; // pointer on new physical page descriptor |
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314 | xptr_t page_xp; // extended pointer on new page descriptor |
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315 | |
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316 | uint32_t ix1; // index in PT1 |
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317 | uint32_t ix2; // index in PT2 |
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318 | |
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319 | uint32_t tsar_attr; // PTE attributes for TSAR MMU |
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320 | |
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321 | // compute indexes in PT1 and PT2 |
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322 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
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323 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
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324 | |
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325 | pt1 = gpt->ptr; |
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326 | small = attr & GPT_SMALL; |
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327 | |
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328 | // compute tsar_attr from generic attributes |
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329 | tsar_attr = gpt2tsar( attr ); |
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330 | |
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331 | // get PT1 entry value |
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332 | pte1_ptr = &pt1[ix1]; |
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333 | pte1 = *pte1_ptr; |
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334 | |
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335 | // Big pages (PTE1) are only set for the kernel vsegs, in the kernel init phase. |
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336 | // There is no risk of concurrent access. |
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337 | if( small == 0 ) |
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338 | { |
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339 | if( pte1 != 0 ) |
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340 | { |
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341 | panic("\n[PANIC] in %s : set a big page in a mapped PT1 entry / PT1[%d] = %x\n", |
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342 | __FUNCTION__ , ix1 , pte1 ); |
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343 | } |
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344 | |
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345 | // set the PTE1 |
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346 | *pte1_ptr = (tsar_attr & TSAR_MMU_PTE1_ATTR_MASK) | |
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347 | ((ppn >> 9) & TSAR_MMU_PTE1_PPN_MASK); |
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348 | hal_fence(); |
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349 | return 0; |
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350 | } |
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351 | |
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352 | // From this point, the requested PTE is a PTE2 (small page) |
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353 | |
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354 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) // the PT1 entry is not valid |
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355 | { |
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356 | // allocate one physical page for the PT2 |
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357 | kmem_req_t req; |
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358 | req.type = KMEM_PAGE; |
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359 | req.size = 0; // 1 small page |
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360 | req.flags = AF_KERNEL | AF_ZERO; |
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361 | page = (page_t *)kmem_alloc( &req ); |
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362 | if( page == NULL ) |
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363 | { |
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364 | printk("\n[ERROR] in %s : try to set a small page but cannot allocate PT2\n", |
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365 | __FUNCTION__ ); |
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366 | return ENOMEM; |
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367 | } |
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368 | |
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369 | page_xp = XPTR( local_cxy , page ); |
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370 | pt2_ppn = ppm_page2ppn( page_xp ); |
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371 | pt2 = (uint32_t *)GET_PTR( ppm_page2base( page_xp ) ); |
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372 | |
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373 | // try to atomicaly set a PTD1 in the PT1 entry |
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374 | do |
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375 | { |
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376 | atomic = hal_atomic_cas( (void*)pte1, 0 , |
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377 | TSAR_MMU_MAPPED | TSAR_MMU_SMALL | pt2_ppn ); |
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378 | } |
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379 | while( (atomic == false) && (*pte1_ptr == 0) ); |
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380 | |
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381 | if( atomic == false ) // the mapping has been done by another thread !!! |
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382 | { |
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383 | // release the allocated page |
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384 | ppm_free_pages( page ); |
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385 | |
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386 | // read PT1 entry again |
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387 | pte1 = *pte1_ptr; |
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388 | |
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389 | // compute PPN of PT2 base |
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390 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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391 | |
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392 | // compute pointer on PT2 base |
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393 | pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
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394 | } |
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395 | } |
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396 | else // The PT1 entry is valid |
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397 | { |
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398 | // This valid entry must be a PTD1 |
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399 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) |
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400 | { |
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401 | printk("\n[ERROR] in %s : set a small page in a big PT1 entry / PT1[%d] = %x\n", |
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402 | __FUNCTION__ , ix1 , pte1 ); |
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403 | return EINVAL; |
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404 | } |
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405 | |
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406 | // compute PPN of PT2 base |
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407 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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408 | |
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409 | // compute pointer on PT2 base |
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410 | pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
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411 | } |
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412 | |
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413 | // set PTE2 in this order |
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414 | pt2[2 * ix2 + 1] = ppn; |
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415 | hal_fence(); |
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416 | pt2[2 * ix2] = tsar_attr; |
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417 | hal_fence(); |
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418 | |
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419 | return 0; |
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420 | |
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421 | } // end of hal_gpt_set_pte() |
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422 | |
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423 | ///////////////////////////////////// |
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424 | void hal_gpt_get_pte( gpt_t * gpt, |
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425 | vpn_t vpn, |
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426 | uint32_t * attr, |
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427 | ppn_t * ppn ) |
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428 | { |
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429 | uint32_t * pt1; |
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430 | uint32_t pte1; |
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431 | |
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432 | uint32_t * pt2; |
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433 | ppn_t pt2_ppn; |
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434 | |
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435 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
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436 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
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437 | |
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438 | // get PTE1 value |
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439 | pt1 = gpt->ptr; |
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440 | pte1 = pt1[ix1]; |
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441 | |
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442 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) // PT1 entry not present |
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443 | { |
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444 | *attr = 0; |
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445 | *ppn = 0; |
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446 | } |
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447 | |
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448 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) // it's a PTE1 |
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449 | { |
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450 | *attr = tsar2gpt( TSAR_MMU_ATTR_FROM_PTE1( pte1 ) ); |
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451 | *ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ) | (vpn & ((1<<TSAR_MMU_IX2_WIDTH)-1)); |
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452 | } |
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453 | else // it's a PTD1 |
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454 | { |
---|
455 | // compute PT2 base address |
---|
456 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
457 | pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
458 | |
---|
459 | *ppn = pt2[2*ix2+1] & ((1<<TSAR_MMU_PPN_WIDTH)-1); |
---|
460 | *attr = tsar2gpt( pt2[2*ix2] ); |
---|
461 | } |
---|
462 | } // end hal_gpt_get_pte() |
---|
463 | |
---|
464 | //////////////////////////////////// |
---|
465 | void hal_gpt_reset_pte( gpt_t * gpt, |
---|
466 | vpn_t vpn ) |
---|
467 | { |
---|
468 | uint32_t * pt1; // PT1 base address |
---|
469 | uint32_t pte1; // PT1 entry value |
---|
470 | |
---|
471 | ppn_t pt2_ppn; // PPN of PT2 |
---|
472 | uint32_t * pt2; // PT2 base address |
---|
473 | |
---|
474 | ppn_t ppn; // PPN of page to be released |
---|
475 | |
---|
476 | // get ix1 & ix2 indexes |
---|
477 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
478 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
479 | |
---|
480 | // get PTE1 value |
---|
481 | pt1 = gpt->ptr; |
---|
482 | pte1 = pt1[ix1]; |
---|
483 | |
---|
484 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) // PT1 entry not present |
---|
485 | { |
---|
486 | return; |
---|
487 | } |
---|
488 | |
---|
489 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) // it's a PTE1 |
---|
490 | { |
---|
491 | // get PPN |
---|
492 | ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ); |
---|
493 | |
---|
494 | // unmap the big page |
---|
495 | pt1[ix1] = 0; |
---|
496 | hal_fence(); |
---|
497 | |
---|
498 | return; |
---|
499 | } |
---|
500 | else // it's a PTD1 |
---|
501 | { |
---|
502 | // compute PT2 base address |
---|
503 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
504 | pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
505 | |
---|
506 | // get PPN |
---|
507 | ppn = TSAR_MMU_PPN_FROM_PTE2( pt2[2*ix2+1] ); |
---|
508 | |
---|
509 | // unmap the small page |
---|
510 | pt2[2*ix2] = 0; // only attr is reset |
---|
511 | hal_fence(); |
---|
512 | |
---|
513 | return; |
---|
514 | } |
---|
515 | } // end hal_gpt_reset_pte() |
---|
516 | |
---|
517 | ////////////////////////////////////// |
---|
518 | error_t hal_gpt_lock_pte( gpt_t * gpt, |
---|
519 | vpn_t vpn ) |
---|
520 | { |
---|
521 | uint32_t * pt1; // PT1 base address |
---|
522 | volatile uint32_t * pte1_ptr; // address of PT1 entry |
---|
523 | uint32_t pte1; // value of PT1 entry |
---|
524 | |
---|
525 | uint32_t * pt2; // PT2 base address |
---|
526 | ppn_t pt2_ppn; // PPN of PT2 page if missing PT2 |
---|
527 | volatile uint32_t * pte2_ptr; // address of PT2 entry |
---|
528 | |
---|
529 | uint32_t attr; |
---|
530 | bool_t atomic; |
---|
531 | page_t * page; |
---|
532 | xptr_t page_xp; |
---|
533 | |
---|
534 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); // index in PT1 |
---|
535 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); // index in PT2 |
---|
536 | |
---|
537 | // get the PTE1 value |
---|
538 | pt1 = gpt->ptr; |
---|
539 | pte1_ptr = &pt1[ix1]; |
---|
540 | pte1 = *pte1_ptr; |
---|
541 | |
---|
542 | // If present, the page must be small |
---|
543 | if( ((pte1 & TSAR_MMU_MAPPED) != 0) && ((pte1 & TSAR_MMU_SMALL) == 0) ) |
---|
544 | { |
---|
545 | printk("\n[ERROR] in %s : try to lock a big page / PT1[%d] = %x\n", |
---|
546 | __FUNCTION__ , ix1 , pte1 ); |
---|
547 | return EINVAL; |
---|
548 | } |
---|
549 | |
---|
550 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) // missing PT1 entry |
---|
551 | { |
---|
552 | // allocate one physical page for PT2 |
---|
553 | kmem_req_t req; |
---|
554 | req.type = KMEM_PAGE; |
---|
555 | req.size = 0; // 1 small page |
---|
556 | req.flags = AF_KERNEL | AF_ZERO; |
---|
557 | page = (page_t *)kmem_alloc( &req ); |
---|
558 | |
---|
559 | if( page == NULL ) |
---|
560 | { |
---|
561 | printk("\n[ERROR] in %s : try to set a small page but cannot allocate PT2\n", |
---|
562 | __FUNCTION__ ); |
---|
563 | return ENOMEM; |
---|
564 | } |
---|
565 | |
---|
566 | page_xp = XPTR( local_cxy , page ); |
---|
567 | pt2_ppn = ppm_page2ppn( page_xp ); |
---|
568 | pt2 = (uint32_t *)GET_PTR( ppm_page2base( page_xp ) ); |
---|
569 | |
---|
570 | // try to set the PT1 entry |
---|
571 | do |
---|
572 | { |
---|
573 | atomic = hal_atomic_cas( (void*)pte1_ptr , 0 , |
---|
574 | TSAR_MMU_MAPPED | TSAR_MMU_SMALL | pt2_ppn ); |
---|
575 | } |
---|
576 | while( (atomic == false) && (*pte1_ptr == 0) ); |
---|
577 | |
---|
578 | if( atomic == false ) // missing PT2 has been allocate by another core |
---|
579 | { |
---|
580 | // release the allocated page |
---|
581 | ppm_free_pages( page ); |
---|
582 | |
---|
583 | // read again the PTE1 |
---|
584 | pte1 = *pte1_ptr; |
---|
585 | |
---|
586 | // get the PT2 base address |
---|
587 | pt2_ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ); |
---|
588 | pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
589 | } |
---|
590 | } |
---|
591 | else |
---|
592 | { |
---|
593 | // This valid entry must be a PTD1 |
---|
594 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) |
---|
595 | { |
---|
596 | printk("\n[ERROR] in %s : set a small page in a big PT1 entry / PT1[%d] = %x\n", |
---|
597 | __FUNCTION__ , ix1 , pte1 ); |
---|
598 | return EINVAL; |
---|
599 | } |
---|
600 | |
---|
601 | // compute PPN of PT2 base |
---|
602 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
603 | |
---|
604 | // compute pointer on PT2 base |
---|
605 | pt2 = (uint32_t *)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
606 | } |
---|
607 | |
---|
608 | // from here we have the PT2 pointer |
---|
609 | |
---|
610 | // compute pointer on PTE2 |
---|
611 | pte2_ptr = &pt2[2 * ix2]; |
---|
612 | |
---|
613 | // try to atomically lock the PTE2 until success |
---|
614 | do |
---|
615 | { |
---|
616 | // busy waiting until TSAR_MMU_LOCK == 0 |
---|
617 | do |
---|
618 | { |
---|
619 | attr = *pte2_ptr; |
---|
620 | hal_rdbar(); |
---|
621 | } |
---|
622 | while( (attr & TSAR_MMU_LOCKED) != 0 ); |
---|
623 | |
---|
624 | atomic = hal_atomic_cas( (void*)pte2_ptr, attr , (attr | TSAR_MMU_LOCKED) ); |
---|
625 | } |
---|
626 | while( atomic == 0 ); |
---|
627 | |
---|
628 | return 0; |
---|
629 | |
---|
630 | } // end hal_gpt_lock_pte() |
---|
631 | |
---|
632 | //////////////////////////////////////// |
---|
633 | error_t hal_gpt_unlock_pte( gpt_t * gpt, |
---|
634 | vpn_t vpn ) |
---|
635 | { |
---|
636 | uint32_t * pt1; // PT1 base address |
---|
637 | uint32_t pte1; // value of PT1 entry |
---|
638 | |
---|
639 | uint32_t * pt2; // PT2 base address |
---|
640 | ppn_t pt2_ppn; // PPN of PT2 page if missing PT2 |
---|
641 | uint32_t * pte2_ptr; // address of PT2 entry |
---|
642 | |
---|
643 | uint32_t attr; // PTE2 attribute |
---|
644 | |
---|
645 | // compute indexes in P1 and PT2 |
---|
646 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); // index in PT1 |
---|
647 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); // index in PT2 |
---|
648 | |
---|
649 | // get pointer on PT1 base |
---|
650 | pt1 = (uint32_t*)gpt->ptr; |
---|
651 | |
---|
652 | // get PTE1 |
---|
653 | pte1 = pt1[ix1]; |
---|
654 | |
---|
655 | // check PTE1 present and small page |
---|
656 | if( ((pte1 & TSAR_MMU_MAPPED) == 0) || ((pte1 & TSAR_MMU_SMALL) == 0) ) |
---|
657 | { |
---|
658 | printk("\n[ERROR] in %s : try to unlock a big or undefined page / PT1[%d] = %x\n", |
---|
659 | __FUNCTION__ , ix1 , pte1 ); |
---|
660 | return EINVAL; |
---|
661 | } |
---|
662 | |
---|
663 | // get pointer on PT2 base |
---|
664 | pt2_ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ); |
---|
665 | pt2 = (uint32_t *)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
666 | |
---|
667 | // get pointer on PTE2 |
---|
668 | pte2_ptr = &pt2[2 * ix2]; |
---|
669 | |
---|
670 | // get PTE2_ATTR |
---|
671 | attr = *pte2_ptr; |
---|
672 | |
---|
673 | // check PTE2 present and locked |
---|
674 | if( ((attr & TSAR_MMU_MAPPED) == 0) || ((attr & TSAR_MMU_LOCKED) == 0) ); |
---|
675 | { |
---|
676 | printk("\n[ERROR] in %s : unlock an unlocked/unmapped page / PT1[%d] = %x\n", |
---|
677 | __FUNCTION__ , ix1 , pte1 ); |
---|
678 | return EINVAL; |
---|
679 | } |
---|
680 | |
---|
681 | // reset GPT_LOCK |
---|
682 | *pte2_ptr = attr & ~TSAR_MMU_LOCKED; |
---|
683 | |
---|
684 | return 0; |
---|
685 | |
---|
686 | } // end hal_gpt_unlock_pte() |
---|
687 | |
---|
688 | /////////////////////////////////////// |
---|
689 | error_t hal_gpt_copy( gpt_t * dst_gpt, |
---|
690 | gpt_t * src_gpt, |
---|
691 | bool_t cow ) |
---|
692 | { |
---|
693 | uint32_t ix1; // index in PT1 |
---|
694 | uint32_t ix2; // index in PT2 |
---|
695 | |
---|
696 | uint32_t * src_pt1; // local pointer on PT1 for SRC_GPT |
---|
697 | uint32_t * dst_pt1; // local pointer on PT1 for DST_GPT |
---|
698 | uint32_t * dst_pt2; // local pointer on PT2 for DST_GPT |
---|
699 | uint32_t * src_pt2; // local pointer on PT2 for SRC_GPT |
---|
700 | |
---|
701 | uint32_t pte1; |
---|
702 | uint32_t pte2_attr; |
---|
703 | uint32_t pte2_ppn; |
---|
704 | uint32_t pte2_writable; |
---|
705 | |
---|
706 | page_t * page; |
---|
707 | xptr_t page_xp; |
---|
708 | |
---|
709 | ppn_t src_pt2_ppn; |
---|
710 | ppn_t dst_pt2_ppn; |
---|
711 | |
---|
712 | // get pointers on PT1 for src_gpt & dst_gpt |
---|
713 | src_pt1 = (uint32_t *)src_gpt->ptr; |
---|
714 | dst_pt1 = (uint32_t *)dst_gpt->ptr; |
---|
715 | |
---|
716 | // scan the SRC_PT1 |
---|
717 | for( ix1 = 0 ; ix1 < 2048 ; ix1++ ) |
---|
718 | { |
---|
719 | pte1 = src_pt1[ix1]; |
---|
720 | if( (pte1 & TSAR_MMU_MAPPED) != 0 ) |
---|
721 | { |
---|
722 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) // PTE1 => big kernel page |
---|
723 | { |
---|
724 | // big kernel pages are shared by all processes => copy it |
---|
725 | dst_pt1[ix1] = pte1; |
---|
726 | } |
---|
727 | else // PTD1 => smal pages |
---|
728 | { |
---|
729 | // allocate one physical page for a PT2 in DST_GPT |
---|
730 | kmem_req_t req; |
---|
731 | req.type = KMEM_PAGE; |
---|
732 | req.size = 0; // 1 small page |
---|
733 | req.flags = AF_KERNEL | AF_ZERO; |
---|
734 | page = (page_t *)kmem_alloc( &req ); |
---|
735 | |
---|
736 | if( page == NULL ) |
---|
737 | { |
---|
738 | // TODO release all memory allocated to DST_GPT |
---|
739 | printk("\n[ERROR] in %s : cannot allocate PT2\n", __FUNCTION__ ); |
---|
740 | return ENOMEM; |
---|
741 | } |
---|
742 | |
---|
743 | // get extended pointer on page descriptor |
---|
744 | page_xp = XPTR( local_cxy , page ); |
---|
745 | |
---|
746 | // get pointer on new PT2 in DST_GPT |
---|
747 | xptr_t base_xp = ppm_page2base( page_xp ); |
---|
748 | dst_pt2 = (uint32_t *)GET_PTR( base_xp ); |
---|
749 | |
---|
750 | // set a new PTD1 in DST_GPT |
---|
751 | dst_pt2_ppn = (ppn_t)ppm_page2ppn( page_xp ); |
---|
752 | dst_pt1[ix1] = TSAR_MMU_MAPPED | TSAR_MMU_SMALL | dst_pt2_ppn; |
---|
753 | |
---|
754 | // get pointer on PT2 in SRC_GPT |
---|
755 | src_pt2_ppn = (ppn_t)TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
756 | src_pt2 = (uint32_t *)GET_PTR( ppm_ppn2base( src_pt2_ppn ) ); |
---|
757 | |
---|
758 | // scan the SRC_PT2 |
---|
759 | for( ix2 = 0 ; ix2 < 512 ; ix2++ ) |
---|
760 | { |
---|
761 | // get attr & ppn from PTE2 |
---|
762 | pte2_attr = TSAR_MMU_ATTR_FROM_PTE2( src_pt2[2 * ix2] ); |
---|
763 | |
---|
764 | if( (pte2_attr & TSAR_MMU_MAPPED) != 0 ) // valid PTE2 in SRC_GPT |
---|
765 | { |
---|
766 | // get GPT_WRITABLE & PPN |
---|
767 | pte2_writable = pte2_attr & GPT_WRITABLE; |
---|
768 | pte2_ppn = TSAR_MMU_PPN_FROM_PTE2( src_pt2[2 * ix2 + 1] ); |
---|
769 | |
---|
770 | // set a new PTE2 in DST_GPT |
---|
771 | dst_pt2[2*ix2] = pte2_attr; |
---|
772 | dst_pt2[2*ix2 + 1] = pte2_ppn; |
---|
773 | |
---|
774 | // handle Copy-On-Write |
---|
775 | if( cow && pte2_writable ) |
---|
776 | { |
---|
777 | // reset GPT_WRITABLE in both SRC_GPT and DST_GPT |
---|
778 | hal_atomic_and( &dst_pt2[2*ix2] , ~GPT_WRITABLE ); |
---|
779 | hal_atomic_and( &src_pt2[2*ix2] , ~GPT_WRITABLE ); |
---|
780 | |
---|
781 | // register PG_COW in page descriptor |
---|
782 | page = (page_t *)GET_PTR( ppm_ppn2page( pte2_ppn ) ); |
---|
783 | hal_atomic_or( &page->flags , PG_COW ); |
---|
784 | hal_atomic_add( &page->fork_nr , 1 ); |
---|
785 | } |
---|
786 | } |
---|
787 | } // end loop on ix2 |
---|
788 | } |
---|
789 | } |
---|
790 | } // end loop ix1 |
---|
791 | |
---|
792 | hal_fence(); |
---|
793 | |
---|
794 | return 0; |
---|
795 | |
---|
796 | } // end hal_gpt_copy() |
---|
797 | |
---|