Context Navigation

source: trunk/hal/tsar_mips32/core/hal_gpt.c @ 632

Last change on this file since 632 was 632, checked in by alain, 5 years ago
This version replace the RPC by direct remote memory access for physical pages allacation/release. It is commited before being tested.
File size: 37.1 KB

Line
1	/*
2	* hal_gpt.c - implementation of the Generic Page Table API for TSAR-MIPS32
3	*
4	* Author Alain Greiner (2016,2017,2018)
5	*
6	* Copyright (c) UPMC Sorbonne Universites
7	*
8	* This file is part of ALMOS-MKH.
9	*
10	* ALMOS-MKH.is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU General Public License as published by
12	* the Free Software Foundation; version 2.0 of the License.
13	*
14	* ALMOS-MKH.is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* General Public License for more details.
18	*
19	* You should have received a copy of the GNU General Public License
20	* along with ALMOS-MKH.; if not, write to the Free Software Foundation,
21	* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22	*/
23
24	#include <hal_kernel_types.h>
25	#include <hal_gpt.h>
26	#include <hal_special.h>
27	#include <printk.h>
28	#include <bits.h>
29	#include <process.h>
30	#include <kmem.h>
31	#include <thread.h>
32	#include <cluster.h>
33	#include <ppm.h>
34	#include <page.h>
35
36	////////////////////////////////////////////////////////////////////////////////////////
37	// This define the masks for the TSAR MMU PTE attributes (from TSAR MMU specification)
38	////////////////////////////////////////////////////////////////////////////////////////
39
40	#define TSAR_PTE_MAPPED 0x80000000
41	#define TSAR_PTE_SMALL 0x40000000
42	#define TSAR_PTE_LOCAL 0x20000000
43	#define TSAR_PTE_REMOTE 0x10000000
44	#define TSAR_PTE_CACHABLE 0x08000000
45	#define TSAR_PTE_WRITABLE 0x04000000
46	#define TSAR_PTE_EXECUTABLE 0x02000000
47	#define TSAR_PTE_USER 0x01000000
48	#define TSAR_PTE_GLOBAL 0x00800000
49	#define TSAR_PTE_DIRTY 0x00400000
50
51	#define TSAR_PTE_COW 0x00000001 // only for small pages
52	#define TSAR_PTE_SWAP 0x00000004 // only for small pages
53	#define TSAR_PTE_LOCKED 0x00000008 // only for small pages
54
55	////////////////////////////////////////////////////////////////////////////////////////
56	// TSAR MMU related macros (from the TSAR MMU specification)
57	// - IX1 on 11 bits
58	// - IX2 on 9 bits
59	// - PPN on 28 bits
60	////////////////////////////////////////////////////////////////////////////////////////
61
62	#define TSAR_MMU_IX1_WIDTH 11
63	#define TSAR_MMU_IX2_WIDTH 9
64	#define TSAR_MMU_PPN_WIDTH 28
65
66	#define TSAR_MMU_PTE1_ATTR_MASK 0xFFC00000
67	#define TSAR_MMU_PTE1_PPN_MASK 0x0007FFFF
68
69	#define TSAR_MMU_IX1_FROM_VPN( vpn ) ((vpn >> 9) & 0x7FF)
70	#define TSAR_MMU_IX2_FROM_VPN( vpn ) (vpn & 0x1FF)
71
72	#define TSAR_MMU_PTBA_FROM_PTE1( pte1 ) (pte1 & 0x0FFFFFFF)
73	#define TSAR_MMU_PPN_FROM_PTE1( pte1 ) ((pte1 & 0x0007FFFF)<<9)
74	#define TSAR_MMU_ATTR_FROM_PTE1( pte1 ) (pte1 & 0xFFC00000)
75
76	#define TSAR_MMU_PPN_FROM_PTE2( pte2 ) (pte2 & 0x0FFFFFFF)
77	#define TSAR_MMU_ATTR_FROM_PTE2( pte2 ) (pte2 & 0xFFC000FF)
78
79	///////////////////////////////////////////////////////////////////////////////////////
80	// This static function translates the GPT attributes to the TSAR attributes
81	///////////////////////////////////////////////////////////////////////////////////////
82	static inline uint32_t gpt2tsar( uint32_t gpt_attr )
83	{
84	uint32_t tsar_attr = 0;
85
86	if( gpt_attr & GPT_MAPPED ) tsar_attr \|= TSAR_PTE_MAPPED;
87	if( gpt_attr & GPT_SMALL ) tsar_attr \|= TSAR_PTE_SMALL;
88	if( gpt_attr & GPT_WRITABLE ) tsar_attr \|= TSAR_PTE_WRITABLE;
89	if( gpt_attr & GPT_EXECUTABLE ) tsar_attr \|= TSAR_PTE_EXECUTABLE;
90	if( gpt_attr & GPT_CACHABLE ) tsar_attr \|= TSAR_PTE_CACHABLE;
91	if( gpt_attr & GPT_USER ) tsar_attr \|= TSAR_PTE_USER;
92	if( gpt_attr & GPT_DIRTY ) tsar_attr \|= TSAR_PTE_DIRTY;
93	if( gpt_attr & GPT_ACCESSED ) tsar_attr \|= TSAR_PTE_LOCAL;
94	if( gpt_attr & GPT_GLOBAL ) tsar_attr \|= TSAR_PTE_GLOBAL;
95	if( gpt_attr & GPT_COW ) tsar_attr \|= TSAR_PTE_COW;
96	if( gpt_attr & GPT_SWAP ) tsar_attr \|= TSAR_PTE_SWAP;
97	if( gpt_attr & GPT_LOCKED ) tsar_attr \|= TSAR_PTE_LOCKED;
98
99	return tsar_attr;
100	}
101
102	///////////////////////////////////////////////////////////////////////////////////////
103	// This static function translates the TSAR attributes to the GPT attributes
104	///////////////////////////////////////////////////////////////////////////////////////
105	static inline uint32_t tsar2gpt( uint32_t tsar_attr )
106	{
107	uint32_t gpt_attr = 0;
108
109	if( tsar_attr & TSAR_PTE_MAPPED ) gpt_attr \|= GPT_MAPPED;
110	if( tsar_attr & TSAR_PTE_MAPPED ) gpt_attr \|= GPT_READABLE;
111	if( tsar_attr & TSAR_PTE_SMALL ) gpt_attr \|= GPT_SMALL;
112	if( tsar_attr & TSAR_PTE_WRITABLE ) gpt_attr \|= GPT_WRITABLE;
113	if( tsar_attr & TSAR_PTE_EXECUTABLE ) gpt_attr \|= GPT_EXECUTABLE;
114	if( tsar_attr & TSAR_PTE_CACHABLE ) gpt_attr \|= GPT_CACHABLE;
115	if( tsar_attr & TSAR_PTE_USER ) gpt_attr \|= GPT_USER;
116	if( tsar_attr & TSAR_PTE_DIRTY ) gpt_attr \|= GPT_DIRTY;
117	if( tsar_attr & TSAR_PTE_LOCAL ) gpt_attr \|= GPT_ACCESSED;
118	if( tsar_attr & TSAR_PTE_REMOTE ) gpt_attr \|= GPT_ACCESSED;
119	if( tsar_attr & TSAR_PTE_GLOBAL ) gpt_attr \|= GPT_GLOBAL;
120	if( tsar_attr & TSAR_PTE_COW ) gpt_attr \|= GPT_COW;
121	if( tsar_attr & TSAR_PTE_SWAP ) gpt_attr \|= GPT_SWAP;
122	if( tsar_attr & TSAR_PTE_LOCKED ) gpt_attr \|= GPT_LOCKED;
123
124	return gpt_attr;
125	}
126
127	///////////////////////////////////////////////////////////////////////////////////////
128	// The blocking hal_gpt_lock_pte() function implements a busy-waiting policy to get
129	// exclusive access to a specific GPT entry.
130	// - when non zero, the following variable defines the max number of iterations
131	// in the busy waiting loop.
132	// - when zero, the watchdog mechanism is deactivated.
133	///////////////////////////////////////////////////////////////////////////////////////
134
135	#define GPT_LOCK_WATCHDOG 100000
136
137	/////////////////////////////////////
138	error_t hal_gpt_create( gpt_t * gpt )
139	{
140	page_t * page;
141	xptr_t page_xp;
142
143	thread_t * this = CURRENT_THREAD;
144
145	#if DEBUG_HAL_GPT_CREATE
146	uint32_t cycle = (uint32_t)hal_get_cycles();
147	if( DEBUG_HAL_GPT_CREATE < cycle )
148	printk("\n[%s] : thread[%x,%x] enter / cycle %d\n",
149	__FUNCTION__, this->process->pid, this->trdid, cycle );
150	#endif
151
152	// check page size
153	assert( (CONFIG_PPM_PAGE_SIZE == 4096) , "for TSAR, the page size must be 4 Kbytes\n" );
154
155	// allocates 2 physical pages for PT1
156	kmem_req_t req;
157	req.type = KMEM_PAGE;
158	req.size = 1; // 2 small pages
159	req.flags = AF_KERNEL \| AF_ZERO;
160	page = (page_t *)kmem_alloc( &req );
161
162	if( page == NULL )
163	{
164	printk("\n[PANIC] in %s : no memory for PT1 / process %x / cluster %x\n",
165	__FUNCTION__, this->process->pid, local_cxy );
166	return ENOMEM;
167	}
168
169	// initialize generic page table descriptor
170	page_xp = XPTR( local_cxy , page );
171	gpt->ptr = GET_PTR( ppm_page2base( page_xp ) );
172	gpt->ppn = ppm_page2ppn( page_xp );
173
174	#if DEBUG_HAL_GPT_CREATE
175	cycle = (uint32_t)hal_get_cycles();
176	if( DEBUG_HAL_GPT_CREATE < cycle )
177	printk("\n[%s] : thread[%x,%x] exit / cycle %d\n",
178	__FUNCTION__, this->process->pid, this->trdid, cycle );
179	#endif
180
181	return 0;
182
183	} // end hal_gpt_create()
184
185	///////////////////////////////////
186	void hal_gpt_destroy( gpt_t * gpt )
187	{
188	uint32_t ix1;
189	uint32_t ix2;
190	uint32_t * pt1;
191	uint32_t pte1;
192	ppn_t pt2_ppn;
193	uint32_t * pt2;
194	uint32_t attr;
195	kmem_req_t req;
196
197	#if DEBUG_HAL_GPT_DESTROY
198	uint32_t cycle = (uint32_t)hal_get_cycles();
199	thread_t * this = CURRENT_THREAD;
200	if( DEBUG_HAL_GPT_DESTROY < cycle )
201	printk("\n[%s] : thread[%x,%x] enter / cycle %d\n",
202	__FUNCTION__, this->process->pid, this->trdid, cycle );
203	#endif
204
205	// get pointer on PT1
206	pt1 = (uint32_t *)gpt->ptr;
207
208	// scan the PT1
209	for( ix1 = 0 ; ix1 < 2048 ; ix1++ )
210	{
211	pte1 = pt1[ix1];
212
213	if( (pte1 & TSAR_PTE_MAPPED) != 0 ) // PTE1 mapped
214	{
215	if( (pte1 & TSAR_PTE_SMALL) == 0 ) // BIG page
216	{
217	printk("\n[WARNING] in %s : mapped big page / ix1 %x\n",
218	__FUNCTION__ , ix1 );
219	}
220	else // PT2 exist
221	{
222	// get local pointer on PT2
223	pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 );
224	xptr_t base_xp = ppm_ppn2base( pt2_ppn );
225	pt2 = GET_PTR( base_xp );
226
227	// scan the PT2
228	for( ix2 = 0 ; ix2 < 512 ; ix2++ )
229	{
230	attr = TSAR_MMU_ATTR_FROM_PTE2( pt2[2 * ix2] );
231
232	if( (attr & TSAR_PTE_MAPPED) != 0 ) // PTE2 mapped
233	{
234	printk("\n[WARNING] in %s : mapped small page / ix1 %x / ix2 %x\n",
235	__FUNCTION__ , ix1, ix2 );
236	}
237	}
238
239	// release the page allocated for the PT2
240	req.type = KMEM_PAGE;
241	req.ptr = GET_PTR( ppm_base2page( XPTR(local_cxy , pt2 ) ) );
242	kmem_free( &req );
243	}
244	}
245	}
246
247	// release the PT1
248	req.type = KMEM_PAGE;
249	req.ptr = GET_PTR( ppm_base2page( XPTR(local_cxy , pt1 ) ) );
250	kmem_free( &req );
251
252	#if DEBUG_HAL_GPT_DESTROY
253	cycle = (uint32_t)hal_get_cycles();
254	if( DEBUG_HAL_GPT_DESTROY < cycle )
255	printk("\n[%s] : thread[%x,%x] exit / cycle %d\n",
256	__FUNCTION__, this->process->pid, this->trdid, cycle );
257	#endif
258
259	} // end hal_gpt_destroy()
260
261	/*
262
263	/////////////////////////////////////////////////////////////////////////////////////
264	// This static function can be used for debug.
265	/////////////////////////////////////////////////////////////////////////////////////
266	static void hal_gpt_display( process_t * process )
267	{
268	gpt_t * gpt;
269	uint32_t ix1;
270	uint32_t ix2;
271	uint32_t * pt1;
272	uint32_t pte1;
273	ppn_t pt2_ppn;
274	uint32_t * pt2;
275	uint32_t pte2_attr;
276	ppn_t pte2_ppn;
277	vpn_t vpn;
278
279	// check argument
280	assert( (process != NULL) , "NULL process pointer\n");
281
282	// get pointer on gpt
283	gpt = &(process->vmm.gpt);
284
285	// get pointer on PT1
286	pt1 = (uint32_t *)gpt->ptr;
287
288	printk("\n***** Tsar Page Table for process %x : &gpt = %x / &pt1 = %x\n\n",
289	process->pid , gpt , pt1 );
290
291	// scan the PT1
292	for( ix1 = 0 ; ix1 < 2048 ; ix1++ )
293	{
294	pte1 = pt1[ix1];
295	if( (pte1 & TSAR_PTE_MAPPED) != 0 )
296	{
297	if( (pte1 & TSAR_PTE_SMALL) == 0 ) // BIG page
298	{
299	vpn = ix1 << 9;
300	printk(" - BIG : vpn = %x / pt1[%d] = %X\n", vpn , ix1 , pte1 );
301	}
302	else // SMALL pages
303	{
304	pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 );
305	xptr_t base_xp = ppm_ppn2base ( pt2_ppn );
306	pt2 = GET_PTR( base_xp );
307
308	// scan the PT2
309	for( ix2 = 0 ; ix2 < 512 ; ix2++ )
310	{
311	pte2_attr = TSAR_MMU_ATTR_FROM_PTE2( pt2[2 * ix2] );
312	pte2_ppn = TSAR_MMU_PPN_FROM_PTE2( pt2[2 * ix2 + 1] );
313
314	if( (pte2_attr & TSAR_PTE_MAPPED) != 0 )
315	{
316	vpn = (ix1 << 9) \| ix2;
317	printk(" - SMALL : vpn %X / ppn %X / attr %X\n",
318	vpn , pte2_ppn , tsar2gpt(pte2_attr) );
319	}
320	}
321	}
322	}
323	}
324	} // end hal_gpt_display()
325
326	*/
327
328	////////////////////////////////////////////
329	error_t hal_gpt_lock_pte( xptr_t gpt_xp,
330	vpn_t vpn,
331	uint32_t * attr,
332	ppn_t * ppn )
333	{
334	uint32_t * pt1_ptr; // local pointer on PT1 base
335	xptr_t ptd1_xp; // extended pointer on PT1[x1] entry
336	uint32_t ptd1; // value of PT1[x1] entry
337
338	xptr_t page_xp;
339
340	ppn_t pt2_ppn; // PPN of page containing PT2
341	uint32_t * pt2_ptr; // local pointer on PT2 base
342	xptr_t pte2_xp; // extended pointer on PT2[ix2].attr
343	uint32_t pte2_attr; // PT2[ix2].attr current value
344	uint32_t pte2_ppn; // PT2[ix2].ppn current value
345	bool_t atomic;
346
347	#if GPT_LOCK_WATCHDOG
348	uint32_t count;
349	#endif
350
351	// get cluster and local pointer on GPT
352	cxy_t gpt_cxy = GET_CXY( gpt_xp );
353	gpt_t * gpt_ptr = GET_PTR( gpt_xp );
354
355	#if DEBUG_HAL_GPT_LOCK_PTE
356	thread_t * this = CURRENT_THREAD;
357	uint32_t cycle = (uint32_t)hal_get_cycles();
358	if( DEBUG_HAL_GPT_LOCK_PTE < cycle )
359	printk("\n[%s] : thread[%x,%x] enters / vpn %x in cluster %x / cycle %d\n",
360	__FUNCTION__, this->process->pid, this->trdid, vpn, gpt_cxy, cycle );
361	#endif
362
363	// get indexes in PTI & PT2 from vpn
364	uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); // index in PT1
365	uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); // index in PT2
366
367	// get local pointer on PT1
368	pt1_ptr = hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) );
369
370	// build extended pointer on PTD1 == PT1[ix1]
371	ptd1_xp = XPTR( gpt_cxy , &pt1_ptr[ix1] );
372
373	// get current PT1 entry value
374	ptd1 = hal_remote_l32( ptd1_xp );
375
376	// If PTD1 is unmapped and unlocked, try to atomically lock this PT1 entry.
377	// This PTD1 lock prevent multiple concurrent PT2 allocations
378	// - only the thread that successfully locked the PTD1 allocates a new PT2
379	// and updates the PTD1
380	// - all other threads simply wait until the missing PTD1 is mapped.
381
382	if( ptd1 == 0 )
383	{
384	// try to atomically lock the PTD1 to prevent concurrent PT2 allocations
385	atomic = hal_remote_atomic_cas( ptd1_xp,
386	ptd1,
387	ptd1 \| TSAR_PTE_LOCKED );
388	if( atomic )
389	{
390	// allocate one 4 Kbytes physical page for PT2
391	page_xp = ppm_remote_alloc_pages( gpt_cxy , 0 );
392
393	if( page_xp == NULL )
394	{
395	printk("\n[ERROR] in %s : cannot allocate memory for PT2\n", __FUNCTION__ );
396	return -1;
397	}
398
399	// get the PT2 PPN
400	pt2_ppn = ppm_page2ppn( page_xp );
401
402	// build PTD1
403	ptd1 = TSAR_PTE_MAPPED \| TSAR_PTE_SMALL \| pt2_ppn;
404
405	// set the PTD1 value in PT1
406	// this unlocks the PTD1
407	hal_remote_s32( ptd1_xp , ptd1 );
408	hal_fence();
409
410	#if (DEBUG_HAL_GPT_LOCK_PTE & 1)
411	if( DEBUG_HAL_GPT_LOCK_PTE < cycle )
412	printk("\n[%s] : thread[%x,%x] allocates a new PT2 for vpn %x in cluster %x\n",
413	__FUNCTION__, this->process->pid, this->trdid, vpn, gpt_cxy );
414	#endif
415
416	} // end if atomic
417	} // end if (ptd1 == 0)
418
419	// wait until PTD1 is mapped by another thread
420	while( (ptd1 & TSAR_PTE_MAPPED) == 0 )
421	{
422	ptd1 = hal_remote_l32( ptd1_xp );
423
424	#if GPT_LOCK_WATCHDOG
425	if( count > GPT_LOCK_WATCHDOG )
426	{
427	thread_t * thread = CURRENT_THREAD;
428	printk("\n[PANIC] in %s : thread[%x,%x] waiting PTD1 / vpn %x / cxy %x / %d iterations\n",
429	__FUNCTION__, thread->process->pid, thread->trdid, vpn, gpt_cxy, count );
430	hal_core_sleep();
431	}
432	count++;
433	#endif
434
435	}
436
437	// check ptd1 because only small page can be locked
438	assert( (ptd1 & TSAR_PTE_SMALL), "cannot lock a big page\n");
439
440	#if (DEBUG_HAL_GPT_LOCK_PTE & 1)
441	if( DEBUG_HAL_GPT_LOCK_PTE < cycle )
442	printk("\n[%s] : thread[%x,%x] get ptd1 %x for vpn %x in cluster %x\n",
443	__FUNCTION__, this->process->pid, this->trdid, ptd1, vpn, gpt_cxy );
444	#endif
445
446	// get pointer on PT2 base from PTD1
447	pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( ptd1 );
448	pt2_ptr = GET_PTR( ppm_ppn2base( pt2_ppn ) );
449
450	// build extended pointers on PT2[ix2].attr
451	pte2_xp = XPTR( gpt_cxy , &pt2_ptr[2 * ix2] );
452
453	// wait until PTE2 atomically set using a remote CAS
454	do
455	{
456
457	#if GPT_LOCK_WATCHDOG
458	count = 0;
459	#endif
460
461	// wait until PTE lock released by the current owner
462	do
463	{
464	pte2_attr = hal_remote_l32( pte2_xp );
465
466	#if GPT_LOCK_WATCHDOG
467	if( count > GPT_LOCK_WATCHDOG )
468	{
469	thread_t * thread = CURRENT_THREAD;
470	printk("\n[PANIC] in %s : thread[%x,%x] waiting PTE2 / vpn %x / cxy %x / %d iterations\n",
471	__FUNCTION__, thread->process->pid, thread->trdid, vpn, gpt_cxy, count );
472	hal_core_sleep();
473	}
474	count++;
475	#endif
476
477	}
478	while( (pte2_attr & TSAR_PTE_LOCKED) != 0 );
479
480	// try to atomically set the TSAR_PTE_LOCKED attribute
481	atomic = hal_remote_atomic_cas( pte2_xp,
482	pte2_attr,
483	(pte2_attr \| TSAR_PTE_LOCKED) );
484	}
485	while( atomic == 0 );
486
487	// get PTE2.ppn
488	pte2_ppn = hal_remote_l32( pte2_xp + 4 );
489
490	#if DEBUG_HAL_GPT_LOCK_PTE
491	cycle = (uint32_t)hal_get_cycles();
492	if( DEBUG_HAL_GPT_LOCK_PTE < cycle )
493	printk("\n[%s] : thread[%x,%x] exit / vpn %x in cluster %x / attr %x / ppn %x / cycle %d\n",
494	__FUNCTION__, this->process->pid, this->trdid, vpn, gpt_cxy, pte2_attr, pte2_ppn, cycle );
495	#endif
496
497	// return PPN and GPT attributes
498	*ppn = pte2_ppn & ((1<<TSAR_MMU_PPN_WIDTH)-1);
499	*attr = tsar2gpt( pte2_attr );
500	return 0;
501
502	} // end hal_gpt_lock_pte()
503
504	////////////////////////////////////////
505	void hal_gpt_unlock_pte( xptr_t gpt_xp,
506	vpn_t vpn )
507	{
508	uint32_t * pt1_ptr; // local pointer on PT1 base
509	xptr_t ptd1_xp; // extended pointer on PT1[ix1]
510	uint32_t ptd1; // value of PT1[ix1] entry
511
512	ppn_t pt2_ppn; // PPN of page containing PT2
513	uint32_t * pt2_ptr; // PT2 base address
514	xptr_t pte2_xp; // extended pointer on PT2[ix2].attr
515	uint32_t pte2_attr; // PTE2 attribute
516
517	// get cluster and local pointer on GPT
518	cxy_t gpt_cxy = GET_CXY( gpt_xp );
519	gpt_t * gpt_ptr = GET_PTR( gpt_xp );
520
521	#if DEBUG_HAL_GPT_LOCK_PTE
522	thread_t * this = CURRENT_THREAD;
523	uint32_t cycle = (uint32_t)hal_get_cycles();
524	if( DEBUG_HAL_GPT_LOCK_PTE < cycle )
525	printk("\n[%s] : thread[%x,%x] enters for vpn %x in cluster %x / cycle %d\n",
526	__FUNCTION__, this->process->pid, this->trdid, vpn, gpt_cxy, cycle );
527	#endif
528
529	// compute indexes in P1 and PT2
530	uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); // index in PT1
531	uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); // index in PT2
532
533	// get local pointer on PT1
534	pt1_ptr = hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) );
535
536	// build extended pointer on PTD1 == PT1[ix1]
537	ptd1_xp = XPTR( gpt_cxy , &pt1_ptr[ix1] );
538
539	// get current ptd1 value
540	ptd1 = hal_remote_l32( ptd1_xp );
541
542	// check PTD1 attributes
543	assert( ((ptd1 & TSAR_PTE_MAPPED) != 0), "unmapped PTE1\n");
544	assert( ((ptd1 & TSAR_PTE_SMALL ) != 0), "big page PTE1\n");
545
546	// get pointer on PT2 base from PTD1
547	pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( ptd1 );
548	pt2_ptr = GET_PTR( ppm_ppn2base( pt2_ppn ) );
549
550	// build extended pointers on PT2[ix2].attr
551	pte2_xp = XPTR( gpt_cxy , &pt2_ptr[2 * ix2] );
552
553	// get PT2[ix2].attr
554	pte2_attr = hal_remote_l32( pte2_xp );
555
556	// check PTE2 attributes
557	assert( ((pte2_attr & TSAR_PTE_MAPPED) != 0), "unmapped PTE2\n");
558	assert( ((pte2_attr & TSAR_PTE_LOCKED) != 0), "unlocked PTE2\n");
559
560	// reset TSAR_PTE_LOCKED attribute
561	hal_remote_s32( pte2_xp , pte2_attr & ~TSAR_PTE_LOCKED );
562
563	#if DEBUG_HAL_GPT_LOCK_PTE
564	cycle = (uint32_t)hal_get_cycles();
565	if( DEBUG_HAL_GPT_LOCK_PTE < cycle )
566	printk("\n[%s] : thread[%x,%x] unlocks vpn %x in cluster %x / cycle %d\n",
567	__FUNCTION__, this->process->pid, this->trdid, vpn, gpt_cxy, cycle );
568	#endif
569
570	} // end hal_gpt_unlock_pte()
571
572
573	///////////////////////////////////////
574	void hal_gpt_set_pte( xptr_t gpt_xp,
575	vpn_t vpn,
576	uint32_t attr,
577	ppn_t ppn )
578	{
579	cxy_t gpt_cxy; // target GPT cluster
580	gpt_t * gpt_ptr; // target GPT local pointer
581
582	uint32_t * pt1_ptr; // local pointer on PT1 base
583	xptr_t pte1_xp; // extended pointer on PT1 entry
584	uint32_t pte1; // PT1 entry value if PTE1
585
586	ppn_t pt2_ppn; // PPN of PT2
587	uint32_t * pt2_ptr; // local pointer on PT2 base
588	xptr_t pte2_attr_xp; // extended pointer on PT2[ix2].attr
589	xptr_t pte2_ppn_xp; // extended pointer on PT2[ix2].ppn
590	uint32_t pte2_attr; // current value of PT2[ix2].attr
591
592	uint32_t ix1; // index in PT1
593	uint32_t ix2; // index in PT2
594
595	uint32_t tsar_attr; // PTE attributes for TSAR MMU
596	uint32_t small; // requested PTE is for a small page
597
598	// get cluster and local pointer on GPT
599	gpt_cxy = GET_CXY( gpt_xp );
600	gpt_ptr = GET_PTR( gpt_xp );
601
602	// compute indexes in PT1 and PT2
603	ix1 = TSAR_MMU_IX1_FROM_VPN( vpn );
604	ix2 = TSAR_MMU_IX2_FROM_VPN( vpn );
605
606	pt1_ptr = hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) );
607	small = attr & GPT_SMALL;
608
609	// compute tsar attributes from generic attributes
610	tsar_attr = gpt2tsar( attr );
611
612	// build extended pointer on PTE1 = PT1[ix1]
613	pte1_xp = XPTR( gpt_cxy , &pt1_ptr[ix1] );
614
615	// get current pte1 value
616	pte1 = hal_remote_l32( pte1_xp );
617
618	if( small == 0 ) ///////////////// map a big page in PT1
619	{
620
621	// check PT1 entry not mapped
622	assert( (pte1 == 0) , "try to set a big page in an already mapped PTE1\n" );
623
624	// check VPN aligned
625	assert( (ix2 == 0) , "illegal vpn for a big page\n" );
626
627	// check PPN aligned
628	assert( ((ppn & 0x1FF) == 0) , "illegal ppn for a big page\n" );
629
630	// set the PTE1 value in PT1
631	pte1 = (tsar_attr & TSAR_MMU_PTE1_ATTR_MASK) \| ((ppn >> 9) & TSAR_MMU_PTE1_PPN_MASK);
632	hal_remote_s32( pte1_xp , pte1 );
633	hal_fence();
634
635	#if DEBUG_HAL_GPT_SET_PTE
636	thread_t * this = CURRENT_THREAD;
637	uint32_t cycle = (uint32_t)hal_get_cycles();
638	if( DEBUG_HAL_GPT_SET_PTE < cycle )
639	printk("\n[%s] : thread[%x,%x] map PTE1 / cxy %x / ix1 %x / pt1 %x / pte1 %x\n",
640	__FUNCTION__, this->process->pid, this->trdid, gpt_cxy, ix1, pt1_ptr, pte1 );
641	#endif
642
643	}
644	else ///////////////// map a small page in PT2
645	{
646
647	// PTE1 must be mapped because PTE2 must be locked
648	assert( (pte1 & TSAR_PTE_MAPPED), "PTE1 must be mapped\n" );
649
650	// get PT2 base from PTE1
651	pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 );
652	pt2_ptr = GET_PTR( ppm_ppn2base( pt2_ppn ) );
653
654	// build extended pointers on PT2[ix2].attr and PT2[ix2].ppn
655	pte2_attr_xp = XPTR( gpt_cxy , &pt2_ptr[2 * ix2] );
656	pte2_ppn_xp = XPTR( gpt_cxy , &pt2_ptr[2 * ix2 + 1] );
657
658	// get current value of PTE2.attr
659	pte2_attr = hal_remote_l32( pte2_attr_xp );
660
661	// PTE2 must be locked
662	assert( (pte2_attr & TSAR_PTE_LOCKED), "PTE2 must be locked\n" );
663
664	// set PTE2 in PT2 (in this order)
665	hal_remote_s32( pte2_ppn_xp , ppn );
666	hal_fence();
667	hal_remote_s32( pte2_attr_xp , tsar_attr );
668	hal_fence();
669
670	#if DEBUG_HAL_GPT_SET_PTE
671	thread_t * this = CURRENT_THREAD;
672	uint32_t cycle = (uint32_t)hal_get_cycles();
673	if( DEBUG_HAL_GPT_SET_PTE < cycle )
674	printk("\n[%s] : thread[%x,%x] map PTE2 / cxy %x / ix2 %x / pt2 %x / attr %x / ppn %x\n",
675	__FUNCTION__, this->process->pid, this->trdid, gpt_cxy, ix2, pt2_ptr, tsar_attr, ppn );
676	#endif
677
678	}
679	} // end of hal_gpt_set_pte()
680
681	///////////////////////////////////////
682	void hal_gpt_reset_pte( xptr_t gpt_xp,
683	vpn_t vpn )
684	{
685	cxy_t gpt_cxy; // target GPT cluster
686	gpt_t * gpt_ptr; // target GPT local pointer
687
688	uint32_t ix1; // index in PT1
689	uint32_t ix2; // index in PT2
690
691	uint32_t * pt1_ptr; // PT1 base address
692	xptr_t pte1_xp; // extended pointer on PT1[ix1]
693	uint32_t pte1; // PT1 entry value
694
695	ppn_t pt2_ppn; // PPN of PT2
696	uint32_t * pt2_ptr; // PT2 base address
697	xptr_t pte2_attr_xp; // extended pointer on PT2[ix2].attr
698	xptr_t pte2_ppn_xp; // extended pointer on PT2[ix2].ppn
699
700	// get cluster and local pointer on GPT
701	gpt_cxy = GET_CXY( gpt_xp );
702	gpt_ptr = GET_PTR( gpt_xp );
703
704	// get ix1 & ix2 indexes
705	ix1 = TSAR_MMU_IX1_FROM_VPN( vpn );
706	ix2 = TSAR_MMU_IX2_FROM_VPN( vpn );
707
708	// get local pointer on PT1 base
709	pt1_ptr = hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) );
710
711	// build extended pointer on PTE1 = PT1[ix1]
712	pte1_xp = XPTR( gpt_cxy , &pt1_ptr[ix1] );
713
714	// get current PTE1 value
715	pte1 = hal_remote_l32( pte1_xp );
716
717	if( (pte1 & TSAR_PTE_MAPPED) == 0 ) // PTE1 unmapped => do nothing
718	{
719	return;
720	}
721
722	if( (pte1 & TSAR_PTE_SMALL) == 0 ) // it's a PTE1 => unmap it from PT1
723	{
724	hal_remote_s32( pte1_xp , 0 );
725	hal_fence();
726
727	#if DEBUG_HAL_GPT_RESET_PTE
728	thread_t * this = CURRENT_THREAD;
729	uint32_t cycle = (uint32_t)hal_get_cycles();
730	if( DEBUG_HAL_GPT_RESET_PTE < cycle )
731	printk("\n[%s] : thread[%x,%x] unmap PTE1 / cxy %x / vpn %x / ix1 %x\n",
732	__FUNCTION__, this->process->pid, this->trdid, gpt_cxy, vpn, ix1 );
733	#endif
734
735	return;
736	}
737	else // it's a PTE2 => unmap it from PT2
738	{
739	// compute PT2 base address
740	pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 );
741	pt2_ptr = GET_PTR( ppm_ppn2base( pt2_ppn ) );
742
743	// build extended pointer on PT2[ix2].attr and PT2[ix2].ppn
744	pte2_attr_xp = XPTR( gpt_cxy , &pt2_ptr[2 * ix2] );
745	pte2_ppn_xp = XPTR( gpt_cxy , &pt2_ptr[2 * ix2 + 1] );
746
747	// unmap the PTE2
748	hal_remote_s32( pte2_attr_xp , 0 );
749	hal_fence();
750	hal_remote_s32( pte2_ppn_xp , 0 );
751	hal_fence();
752
753	#if DEBUG_HAL_GPT_RESET_PTE
754	thread_t * this = CURRENT_THREAD;
755	uint32_t cycle = (uint32_t)hal_get_cycles();
756	if( DEBUG_HAL_GPT_RESET_PTE < cycle )
757	printk("\n[%s] : thread[%x,%x] unmap PTE2 / cxy %x / vpn %x / ix2 %x\n",
758	__FUNCTION__, this->process->pid, this->trdid, gpt_cxy, vpn, ix2 );
759	#endif
760
761	return;
762	}
763	} // end hal_gpt_reset_pte()
764
765	////////////////////////////////////////
766	void hal_gpt_get_pte( xptr_t gpt_xp,
767	vpn_t vpn,
768	uint32_t * attr,
769	ppn_t * ppn )
770	{
771	uint32_t * pt1; // local pointer on PT1 base
772	uint32_t pte1; // PTE1 value
773
774	uint32_t * pt2; // local pointer on PT2 base
775	ppn_t pt2_ppn; // PPN of page containing the PT2
776	xptr_t pte2_attr_xp; // extended pointer on PT2[ix2].attr
777	xptr_t pte2_ppn_xp; // extended pointer on PT2[ix2].ppn
778	uint32_t pte2_attr; // current value of PT2[ix2].attr
779	ppn_t pte2_ppn; // current value of PT2[ix2].ppn
780
781	// get cluster and local pointer on GPT
782	cxy_t gpt_cxy = GET_CXY( gpt_xp );
783	gpt_t * gpt_ptr = GET_PTR( gpt_xp );
784
785	// compute indexes in PT1 and PT2
786	uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn );
787	uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn );
788
789	// get PT1 base
790	pt1 = hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) );
791
792	// get pte1
793	pte1 = hal_remote_l32( XPTR( gpt_cxy , &pt1[ix1] ) );
794
795	// check PTE1 mapped
796	if( (pte1 & TSAR_PTE_MAPPED) == 0 ) // PTE1 unmapped
797	{
798	*attr = 0;
799	*ppn = 0;
800	return;
801	}
802
803	// access GPT
804	if( (pte1 & TSAR_PTE_SMALL) == 0 ) // it's a PTE1
805	{
806	// get PPN & ATTR from PT1
807	*attr = tsar2gpt( TSAR_MMU_ATTR_FROM_PTE1( pte1 ) );
808	*ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ) \| (vpn & ((1<<TSAR_MMU_IX2_WIDTH)-1));
809	}
810	else // it's a PTE2
811	{
812	// compute PT2 base address
813	pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 );
814	pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) );
815
816	// build extended pointer on PT2[ix2].attr and PT2[ix2].ppn
817	pte2_attr_xp = XPTR( gpt_cxy , &pt2[2 * ix2] );
818	pte2_ppn_xp = XPTR( gpt_cxy , &pt2[2 * ix2 + 1] );
819
820	// get current value of PTE2.attr & PTE2.ppn
821	pte2_attr = hal_remote_l32( pte2_attr_xp );
822	pte2_ppn = hal_remote_l32( pte2_ppn_xp );
823
824	// return PPN & GPT attributes
825	*ppn = pte2_ppn & ((1<<TSAR_MMU_PPN_WIDTH)-1);
826	*attr = tsar2gpt( pte2_attr );
827	}
828	} // end hal_gpt_get_pte()
829
830
831	///////////////////////////////////////////
832	error_t hal_gpt_pte_copy( gpt_t * dst_gpt,
833	vpn_t dst_vpn,
834	xptr_t src_gpt_xp,
835	vpn_t src_vpn,
836	bool_t cow,
837	ppn_t * ppn,
838	bool_t * mapped )
839	{
840	uint32_t src_ix1; // index in SRC PT1
841	uint32_t src_ix2; // index in SRC PT2
842
843	uint32_t dst_ix1; // index in DST PT1
844	uint32_t dst_ix2; // index in DST PT2
845
846	cxy_t src_cxy; // SRC GPT cluster
847	gpt_t * src_gpt; // SRC GPT local pointer
848
849	uint32_t * src_pt1; // local pointer on SRC PT1
850	uint32_t * dst_pt1; // local pointer on DST PT1
851	uint32_t * src_pt2; // local pointer on SRC PT2
852	uint32_t * dst_pt2; // local pointer on DST PT2
853
854	kmem_req_t req; // for PT2 allocation
855
856	uint32_t src_pte1;
857	uint32_t dst_pte1;
858
859	uint32_t src_pte2_attr;
860	uint32_t src_pte2_ppn;
861
862	page_t * page;
863	xptr_t page_xp;
864
865	ppn_t src_pt2_ppn;
866	ppn_t dst_pt2_ppn;
867
868	// get remote src_gpt cluster and local pointer
869	src_cxy = GET_CXY( src_gpt_xp );
870	src_gpt = GET_PTR( src_gpt_xp );
871
872	#if DEBUG_HAL_GPT_COPY
873	uint32_t cycle = (uint32_t)hal_get_cycles();
874	thread_t * this = CURRENT_THREAD;
875	if( DEBUG_HAL_GPT_COPY < cycle )
876	printk("\n[%s] : thread[%x,%x] enter / src_cxy %x / dst_cxy %x / cycle %d\n",
877	__FUNCTION__, this->process->pid, this->trdid, src_cxy, local_cxy, cycle );
878	#endif
879
880	// get remote src_gpt cluster and local pointer
881	src_cxy = GET_CXY( src_gpt_xp );
882	src_gpt = GET_PTR( src_gpt_xp );
883
884	// get remote src_pt1 and local dst_pt1
885	src_pt1 = (uint32_t *)hal_remote_lpt( XPTR( src_cxy , &src_gpt->ptr ) );
886	dst_pt1 = (uint32_t *)dst_gpt->ptr;
887
888	// check src_pt1 and dst_pt1 existence
889	assert( (src_pt1 != NULL) , "src_pt1 does not exist\n");
890	assert( (dst_pt1 != NULL) , "dst_pt1 does not exist\n");
891
892	// compute SRC indexes
893	src_ix1 = TSAR_MMU_IX1_FROM_VPN( src_vpn );
894	src_ix2 = TSAR_MMU_IX2_FROM_VPN( src_vpn );
895
896	// compute DST indexes
897	dst_ix1 = TSAR_MMU_IX1_FROM_VPN( dst_vpn );
898	dst_ix2 = TSAR_MMU_IX2_FROM_VPN( dst_vpn );
899
900	// get src_pte1
901	src_pte1 = hal_remote_l32( XPTR( src_cxy , &src_pt1[src_ix1] ) );
902
903	// do nothing if src_pte1 not MAPPED or not SMALL
904	if( (src_pte1 & TSAR_PTE_MAPPED) && (src_pte1 & TSAR_PTE_SMALL) )
905	{
906	// get dst_pt1 entry
907	dst_pte1 = dst_pt1[dst_ix1];
908
909	// map dst_pte1 if required
910	if( (dst_pte1 & TSAR_PTE_MAPPED) == 0 )
911	{
912	// allocate one physical page for a new PT2
913	req.type = KMEM_PAGE;
914	req.size = 0; // 1 small page
915	req.flags = AF_KERNEL \| AF_ZERO;
916	page = (page_t *)kmem_alloc( &req );
917
918	if( page == NULL )
919	{
920	printk("\n[ERROR] in %s : cannot allocate PT2\n", __FUNCTION__ );
921	return -1;
922	}
923
924	// build extended pointer on page descriptor
925	page_xp = XPTR( local_cxy , page );
926
927	// get PPN for this new PT2
928	dst_pt2_ppn = (ppn_t)ppm_page2ppn( page_xp );
929
930	// build the new dst_pte1
931	dst_pte1 = TSAR_PTE_MAPPED \| TSAR_PTE_SMALL \| dst_pt2_ppn;
932
933	// register it in DST_GPT
934	dst_pt1[dst_ix1] = dst_pte1;
935	}
936
937	// get pointer on src_pt2
938	src_pt2_ppn = (ppn_t)TSAR_MMU_PTBA_FROM_PTE1( src_pte1 );
939	src_pt2 = GET_PTR( ppm_ppn2base( src_pt2_ppn ) );
940
941	// get pointer on dst_pt2
942	dst_pt2_ppn = (ppn_t)TSAR_MMU_PTBA_FROM_PTE1( dst_pte1 );
943	dst_pt2 = GET_PTR( ppm_ppn2base( dst_pt2_ppn ) );
944
945	// get attr and ppn from SRC_PT2
946	src_pte2_attr = hal_remote_l32( XPTR( src_cxy , &src_pt2[2 * src_ix2] ) );
947	src_pte2_ppn = hal_remote_l32( XPTR( src_cxy , &src_pt2[2 * src_ix2 + 1] ) );
948
949	// do nothing if src_pte2 not MAPPED
950	if( (src_pte2_attr & TSAR_PTE_MAPPED) != 0 )
951	{
952	// set PPN in DST PTE2
953	dst_pt2[2 * dst_ix2 + 1] = src_pte2_ppn;
954
955	// set attributes in DST PTE2
956	if( cow && (src_pte2_attr & TSAR_PTE_WRITABLE) )
957	{
958	dst_pt2[2 * dst_ix2] = (src_pte2_attr \| TSAR_PTE_COW) & (~TSAR_PTE_WRITABLE);
959	}
960	else
961	{
962	dst_pt2[2 * dst_ix2] = src_pte2_attr;
963	}
964
965	// return "successfully copied"
966	*mapped = true;
967	*ppn = src_pte2_ppn;
968
969	#if DEBUG_HAL_GPT_COPY
970	cycle = (uint32_t)hal_get_cycles;
971	if( DEBUG_HAL_GPT_COPY < cycle )
972	printk("\n[%s] : thread[%x,%x] exit / copy done for src_vpn %x / dst_vpn %x / cycle %d\n",
973	__FUNCTION__, this->process->pid, this->trdid, src_vpn, dst_vpn, cycle );
974	#endif
975
976	hal_fence();
977
978	return 0;
979	} // end if PTE2 mapped
980	} // end if PTE1 mapped
981
982	// return "nothing done"
983	*mapped = false;
984	*ppn = 0;
985
986	#if DEBUG_HAL_GPT_COPY
987	cycle = (uint32_t)hal_get_cycles;
988	if( DEBUG_HAL_GPT_COPY < cycle )
989	printk("\n[%s] : thread[%x,%x] exit / nothing done / cycle %d\n",
990	__FUNCTION__, this->process->pid, this->trdid, cycle );
991	#endif
992
993	hal_fence();
994
995	return 0;
996
997	} // end hal_gpt_pte_copy()
998
999	/////////////////////////////////////////
1000	void hal_gpt_set_cow( xptr_t gpt_xp,
1001	vpn_t vpn_base,
1002	vpn_t vpn_size )
1003	{
1004	cxy_t gpt_cxy;
1005	gpt_t * gpt_ptr;
1006
1007	vpn_t vpn;
1008
1009	uint32_t ix1;
1010	uint32_t ix2;
1011
1012	uint32_t * pt1;
1013	uint32_t pte1;
1014
1015	uint32_t * pt2;
1016	ppn_t pt2_ppn;
1017	uint32_t attr;
1018
1019	// get GPT cluster and local pointer
1020	gpt_cxy = GET_CXY( gpt_xp );
1021	gpt_ptr = GET_PTR( gpt_xp );
1022
1023	// get local PT1 pointer
1024	pt1 = (uint32_t *)hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) );
1025
1026	// loop on pages
1027	for( vpn = vpn_base ; vpn < (vpn_base + vpn_size) ; vpn++ )
1028	{
1029	ix1 = TSAR_MMU_IX1_FROM_VPN( vpn );
1030	ix2 = TSAR_MMU_IX2_FROM_VPN( vpn );
1031
1032	// get PTE1 value
1033	pte1 = hal_remote_l32( XPTR( gpt_cxy , &pt1[ix1] ) );
1034
1035	// only MAPPED & SMALL PTEs are modified
1036	if( (pte1 & TSAR_PTE_MAPPED) && (pte1 & TSAR_PTE_SMALL) )
1037	{
1038	// compute PT2 base address
1039	pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 );
1040	pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) );
1041
1042	assert( (GET_CXY( ppm_ppn2base( pt2_ppn ) ) == gpt_cxy ),
1043	"PT2 and PT1 must be in the same cluster\n");
1044
1045	// get current PTE2 attributes
1046	attr = hal_remote_l32( XPTR( gpt_cxy , &pt2[2*ix2] ) );
1047
1048	// only MAPPED PTEs are modified
1049	if( attr & TSAR_PTE_MAPPED )
1050	{
1051	attr = (attr \| TSAR_PTE_COW) & (~TSAR_PTE_WRITABLE);
1052	hal_remote_s32( XPTR( gpt_cxy , &pt2[2*ix2] ) , attr );
1053	}
1054	}
1055	} // end loop on pages
1056
1057	} // end hal_gpt_set_cow()
1058
1059	//////////////////////////////////////////
1060	void hal_gpt_update_pte( xptr_t gpt_xp,
1061	vpn_t vpn,
1062	uint32_t attr, // generic GPT attributes
1063	ppn_t ppn )
1064	{
1065	uint32_t * pt1; // PT1 base addres
1066	uint32_t pte1; // PT1 entry value
1067
1068	ppn_t pt2_ppn; // PPN of PT2
1069	uint32_t * pt2; // PT2 base address
1070	xptr_t pte2_xp; // exended pointer on PTE2
1071
1072	uint32_t ix1; // index in PT1
1073	uint32_t ix2; // index in PT2
1074
1075
1076	uint32_t tsar_attr; // PTE attributes for TSAR MMU
1077
1078	// check MAPPED, SMALL, and not LOCKED in attr argument
1079	assert( ((attr & GPT_MAPPED) != 0), "attribute MAPPED must be set in new attributes\n" );
1080	assert( ((attr & GPT_SMALL ) != 0), "attribute SMALL must be set in new attributes\n" );
1081	assert( ((attr & GPT_LOCKED) == 0), "attribute LOCKED must not be set in new attributes\n" );
1082
1083	// get cluster and local pointer on remote GPT
1084	cxy_t gpt_cxy = GET_CXY( gpt_xp );
1085	gpt_t * gpt_ptr = GET_PTR( gpt_xp );
1086
1087	// compute indexes in PT1 and PT2
1088	ix1 = TSAR_MMU_IX1_FROM_VPN( vpn );
1089	ix2 = TSAR_MMU_IX2_FROM_VPN( vpn );
1090
1091	// get PT1 base
1092	pt1 = (uint32_t *)hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) );
1093
1094	// compute tsar_attr from generic attributes
1095	tsar_attr = gpt2tsar( attr );
1096
1097	// get PTE1 value
1098	pte1 = hal_remote_l32( XPTR( gpt_cxy , &pt1[ix1] ) );
1099
1100	// check MAPPED and SMALL in target PTE1
1101	assert( ((pte1 & GPT_MAPPED) != 0), "attribute MAPPED must be set in target PTE1\n" );
1102	assert( ((pte1 & GPT_SMALL ) != 0), "attribute SMALL must be set in target PTE1\n" );
1103
1104	// get PT2 base from PTE1
1105	pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 );
1106	pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) );
1107
1108	// get extended pointer on PTE2
1109	pte2_xp = XPTR( gpt_cxy , &pt2[2*ix2] );
1110
1111	// check MAPPED in target PTE2
1112	assert( ((hal_remote_l32(pte2_xp) & GPT_MAPPED) != 0),
1113	"attribute MAPPED must be set in target PTE2\n" );
1114
1115	// set PTE2 in this order
1116	hal_remote_s32( pte2_xp , ppn );
1117	hal_fence();
1118	hal_remote_s32( pte2_xp + 4 , tsar_attr );
1119	hal_fence();
1120
1121	} // end hal_gpt_update_pte()
1122
1123
1124
1125
1126

Note: See TracBrowser for help on using the repository browser.

Download in other formats: