1 | /* |
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2 | * hal_gpt.c - implementation of the Generic Page Table API for TSAR-MIPS32 |
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3 | * |
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4 | * Author Alain Greiner (2016,2017,2018,2019) |
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5 | * |
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6 | * Copyright (c) UPMC Sorbonne Universites |
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7 | * |
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8 | * This file is part of ALMOS-MKH. |
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9 | * |
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10 | * ALMOS-MKH.is free software; you can redistribute it and/or modify it |
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11 | * under the terms of the GNU General Public License as published by |
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12 | * the Free Software Foundation; version 2.0 of the License. |
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13 | * |
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14 | * ALMOS-MKH.is distributed in the hope that it will be useful, but |
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15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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17 | * General Public License for more details. |
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18 | * |
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19 | * You should have received a copy of the GNU General Public License |
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20 | * along with ALMOS-MKH.; if not, write to the Free Software Foundation, |
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21 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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22 | */ |
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23 | |
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24 | #include <hal_kernel_types.h> |
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25 | #include <hal_gpt.h> |
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26 | #include <hal_special.h> |
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27 | #include <printk.h> |
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28 | #include <bits.h> |
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29 | #include <process.h> |
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30 | #include <kmem.h> |
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31 | #include <thread.h> |
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32 | #include <cluster.h> |
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33 | #include <ppm.h> |
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34 | #include <page.h> |
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35 | |
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36 | //////////////////////////////////////////////////////////////////////////////////////// |
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37 | // This define the masks for the TSAR MMU PTE attributes (from TSAR MMU specification) |
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38 | //////////////////////////////////////////////////////////////////////////////////////// |
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39 | |
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40 | #define TSAR_PTE_MAPPED 0x80000000 |
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41 | #define TSAR_PTE_SMALL 0x40000000 |
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42 | #define TSAR_PTE_LOCAL 0x20000000 |
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43 | #define TSAR_PTE_REMOTE 0x10000000 |
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44 | #define TSAR_PTE_CACHABLE 0x08000000 |
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45 | #define TSAR_PTE_WRITABLE 0x04000000 |
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46 | #define TSAR_PTE_EXECUTABLE 0x02000000 |
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47 | #define TSAR_PTE_USER 0x01000000 |
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48 | #define TSAR_PTE_GLOBAL 0x00800000 |
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49 | #define TSAR_PTE_DIRTY 0x00400000 |
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50 | |
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51 | #define TSAR_PTE_COW 0x00000001 // only for small pages |
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52 | #define TSAR_PTE_SWAP 0x00000004 // only for small pages |
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53 | #define TSAR_PTE_LOCKED 0x00000008 // only for small pages |
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54 | |
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55 | //////////////////////////////////////////////////////////////////////////////////////// |
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56 | // TSAR MMU related macros (from the TSAR MMU specification) |
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57 | // - IX1 on 11 bits |
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58 | // - IX2 on 9 bits |
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59 | // - PPN on 28 bits |
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60 | //////////////////////////////////////////////////////////////////////////////////////// |
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61 | |
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62 | #define TSAR_MMU_IX1_WIDTH 11 |
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63 | #define TSAR_MMU_IX2_WIDTH 9 |
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64 | #define TSAR_MMU_PPN_WIDTH 28 |
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65 | |
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66 | #define TSAR_MMU_PTE1_ATTR_MASK 0xFFC00000 |
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67 | #define TSAR_MMU_PTE1_PPN_MASK 0x0007FFFF |
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68 | |
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69 | #define TSAR_MMU_IX1_FROM_VPN( vpn ) ((vpn >> 9) & 0x7FF) |
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70 | #define TSAR_MMU_IX2_FROM_VPN( vpn ) (vpn & 0x1FF) |
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71 | |
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72 | #define TSAR_MMU_PPN2_FROM_PTE1( pte1 ) (pte1 & 0x0FFFFFFF) |
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73 | #define TSAR_MMU_PPN1_FROM_PTE1( pte1 ) ((pte1 & 0x0007FFFF)<<9) |
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74 | #define TSAR_MMU_ATTR_FROM_PTE1( pte1 ) (pte1 & 0xFFC00000) |
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75 | |
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76 | #define TSAR_MMU_PPN_FROM_PTE2( pte2 ) (pte2 & 0x0FFFFFFF) |
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77 | #define TSAR_MMU_ATTR_FROM_PTE2( pte2 ) (pte2 & 0xFFC000FF) |
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78 | |
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79 | /////////////////////////////////////////////////////////////////////////////////////// |
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80 | // This static function translates the GPT attributes to the TSAR attributes |
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81 | /////////////////////////////////////////////////////////////////////////////////////// |
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82 | static inline uint32_t gpt2tsar( uint32_t gpt_attr ) |
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83 | { |
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84 | uint32_t tsar_attr = 0; |
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85 | |
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86 | if( gpt_attr & GPT_MAPPED ) tsar_attr |= TSAR_PTE_MAPPED; |
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87 | if( gpt_attr & GPT_SMALL ) tsar_attr |= TSAR_PTE_SMALL; |
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88 | if( gpt_attr & GPT_WRITABLE ) tsar_attr |= TSAR_PTE_WRITABLE; |
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89 | if( gpt_attr & GPT_EXECUTABLE ) tsar_attr |= TSAR_PTE_EXECUTABLE; |
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90 | if( gpt_attr & GPT_CACHABLE ) tsar_attr |= TSAR_PTE_CACHABLE; |
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91 | if( gpt_attr & GPT_USER ) tsar_attr |= TSAR_PTE_USER; |
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92 | if( gpt_attr & GPT_DIRTY ) tsar_attr |= TSAR_PTE_DIRTY; |
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93 | if( gpt_attr & GPT_ACCESSED ) tsar_attr |= TSAR_PTE_LOCAL; |
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94 | if( gpt_attr & GPT_GLOBAL ) tsar_attr |= TSAR_PTE_GLOBAL; |
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95 | if( gpt_attr & GPT_COW ) tsar_attr |= TSAR_PTE_COW; |
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96 | if( gpt_attr & GPT_SWAP ) tsar_attr |= TSAR_PTE_SWAP; |
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97 | if( gpt_attr & GPT_LOCKED ) tsar_attr |= TSAR_PTE_LOCKED; |
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98 | |
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99 | return tsar_attr; |
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100 | } |
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101 | |
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102 | /////////////////////////////////////////////////////////////////////////////////////// |
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103 | // This static function translates the TSAR attributes to the GPT attributes |
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104 | /////////////////////////////////////////////////////////////////////////////////////// |
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105 | static inline uint32_t tsar2gpt( uint32_t tsar_attr ) |
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106 | { |
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107 | uint32_t gpt_attr = 0; |
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108 | |
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109 | if( tsar_attr & TSAR_PTE_MAPPED ) gpt_attr |= GPT_MAPPED; |
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110 | if( tsar_attr & TSAR_PTE_MAPPED ) gpt_attr |= GPT_READABLE; |
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111 | if( tsar_attr & TSAR_PTE_SMALL ) gpt_attr |= GPT_SMALL; |
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112 | if( tsar_attr & TSAR_PTE_WRITABLE ) gpt_attr |= GPT_WRITABLE; |
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113 | if( tsar_attr & TSAR_PTE_EXECUTABLE ) gpt_attr |= GPT_EXECUTABLE; |
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114 | if( tsar_attr & TSAR_PTE_CACHABLE ) gpt_attr |= GPT_CACHABLE; |
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115 | if( tsar_attr & TSAR_PTE_USER ) gpt_attr |= GPT_USER; |
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116 | if( tsar_attr & TSAR_PTE_DIRTY ) gpt_attr |= GPT_DIRTY; |
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117 | if( tsar_attr & TSAR_PTE_LOCAL ) gpt_attr |= GPT_ACCESSED; |
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118 | if( tsar_attr & TSAR_PTE_REMOTE ) gpt_attr |= GPT_ACCESSED; |
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119 | if( tsar_attr & TSAR_PTE_GLOBAL ) gpt_attr |= GPT_GLOBAL; |
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120 | if( tsar_attr & TSAR_PTE_COW ) gpt_attr |= GPT_COW; |
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121 | if( tsar_attr & TSAR_PTE_SWAP ) gpt_attr |= GPT_SWAP; |
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122 | if( tsar_attr & TSAR_PTE_LOCKED ) gpt_attr |= GPT_LOCKED; |
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123 | |
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124 | return gpt_attr; |
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125 | } |
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126 | |
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127 | /////////////////////////////////////////////////////////////////////////////////////// |
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128 | // The blocking hal_gpt_lock_pte() function implements a busy-waiting policy to get |
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129 | // exclusive access to a specific GPT entry. |
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130 | // - when non zero, the following variable defines the max number of iterations |
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131 | // in the busy waiting loop. |
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132 | // - when zero, the watchdog mechanism is deactivated. |
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133 | /////////////////////////////////////////////////////////////////////////////////////// |
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134 | |
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135 | #define GPT_LOCK_WATCHDOG 1000000 |
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136 | |
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137 | ///////////////////////////////////// |
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138 | error_t hal_gpt_create( gpt_t * gpt ) |
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139 | { |
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140 | void * base; |
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141 | |
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142 | thread_t * this = CURRENT_THREAD; |
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143 | |
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144 | #if DEBUG_HAL_GPT_CREATE |
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145 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
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146 | if( DEBUG_HAL_GPT_CREATE < cycle ) |
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147 | printk("\n[%s] thread[%x,%x] enter / cycle %d\n", |
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148 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
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149 | #endif |
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150 | |
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151 | // check page size |
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152 | assert( (CONFIG_PPM_PAGE_SIZE == 4096) , "the TSAR page size must be 4 Kbytes\n" ); |
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153 | |
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154 | // allocates 2 physical pages for PT1 |
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155 | kmem_req_t req; |
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156 | req.type = KMEM_PPM; |
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157 | req.order = 1; // 2 small pages |
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158 | req.flags = AF_KERNEL | AF_ZERO; |
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159 | base = kmem_alloc( &req ); |
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160 | |
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161 | if( base == NULL ) |
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162 | { |
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163 | printk("\n[PANIC] in %s : no memory for PT1 / process %x / cluster %x\n", |
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164 | __FUNCTION__, this->process->pid, local_cxy ); |
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165 | return ENOMEM; |
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166 | } |
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167 | |
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168 | gpt->ptr = base; |
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169 | gpt->ppn = ppm_base2ppn( XPTR( local_cxy , base ) ); |
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170 | |
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171 | #if DEBUG_HAL_GPT_CREATE |
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172 | cycle = (uint32_t)hal_get_cycles(); |
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173 | if( DEBUG_HAL_GPT_CREATE < cycle ) |
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174 | printk("\n[%s] thread[%x,%x] exit / pt1_base %x / pt1_ppn %x / cycle %d\n", |
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175 | __FUNCTION__, this->process->pid, this->trdid, gpt->ptr, gpt->ppn, cycle ); |
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176 | #endif |
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177 | |
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178 | return 0; |
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179 | |
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180 | } // end hal_gpt_create() |
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181 | |
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182 | /////////////////////////////////// |
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183 | void hal_gpt_destroy( gpt_t * gpt ) |
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184 | { |
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185 | uint32_t ix1; |
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186 | uint32_t ix2; |
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187 | uint32_t * pt1; |
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188 | uint32_t pte1; |
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189 | ppn_t pt2_ppn; |
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190 | uint32_t * pt2; |
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191 | uint32_t attr; |
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192 | kmem_req_t req; |
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193 | |
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194 | #if DEBUG_HAL_GPT_DESTROY |
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195 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
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196 | thread_t * this = CURRENT_THREAD; |
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197 | if( DEBUG_HAL_GPT_DESTROY < cycle ) |
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198 | printk("\n[%s] thread[%x,%x] enter / cycle %d\n", |
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199 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
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200 | #endif |
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201 | |
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202 | // get pointer on PT1 |
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203 | pt1 = (uint32_t *)gpt->ptr; |
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204 | |
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205 | // scan the PT1 |
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206 | for( ix1 = 0 ; ix1 < 2048 ; ix1++ ) |
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207 | { |
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208 | pte1 = pt1[ix1]; |
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209 | |
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210 | if( (pte1 & TSAR_PTE_MAPPED) != 0 ) // PTE1 mapped |
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211 | { |
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212 | if( (pte1 & TSAR_PTE_SMALL) == 0 ) // BIG page |
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213 | { |
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214 | printk("\n[WARNING] in %s : mapped big page / ix1 %x\n", |
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215 | __FUNCTION__ , ix1 ); |
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216 | } |
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217 | else // PT2 exist |
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218 | { |
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219 | // get local pointer on PT2 |
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220 | pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( pte1 ); |
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221 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
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222 | |
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223 | // scan the PT2 |
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224 | for( ix2 = 0 ; ix2 < 512 ; ix2++ ) |
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225 | { |
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226 | attr = TSAR_MMU_ATTR_FROM_PTE2( pt2[2 * ix2] ); |
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227 | |
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228 | if( (attr & TSAR_PTE_MAPPED) != 0 ) // PTE2 mapped |
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229 | { |
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230 | printk("\n[WARNING] in %s : mapped small page / ix1 %x / ix2 %x\n", |
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231 | __FUNCTION__ , ix1, ix2 ); |
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232 | } |
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233 | } |
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234 | |
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235 | // release the page allocated for the PT2 |
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236 | req.type = KMEM_PPM; |
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237 | req.ptr = pt2; |
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238 | kmem_free( &req ); |
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239 | } |
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240 | } |
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241 | } |
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242 | |
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243 | // release the PT1 |
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244 | req.type = KMEM_PPM; |
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245 | req.ptr = pt1; |
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246 | kmem_free( &req ); |
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247 | |
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248 | #if DEBUG_HAL_GPT_DESTROY |
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249 | cycle = (uint32_t)hal_get_cycles(); |
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250 | if( DEBUG_HAL_GPT_DESTROY < cycle ) |
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251 | printk("\n[%s] thread[%x,%x] exit / cycle %d\n", |
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252 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
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253 | #endif |
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254 | |
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255 | } // end hal_gpt_destroy() |
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256 | |
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257 | //////////////////////////////////////////// |
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258 | error_t hal_gpt_lock_pte( xptr_t gpt_xp, |
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259 | vpn_t vpn, |
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260 | uint32_t * attr, |
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261 | ppn_t * ppn ) |
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262 | { |
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263 | uint32_t * pt1; // local pointer on PT1 base |
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264 | xptr_t pte1_xp; // extended pointer on PT1[x1] entry |
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265 | uint32_t pte1; // value of PT1[x1] entry |
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266 | |
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267 | kmem_req_t req; // kmem request fro PT2 allocation |
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268 | |
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269 | uint32_t * pt2; // local pointer on PT2 base |
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270 | ppn_t pt2_ppn; // PPN of page containing PT2 |
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271 | xptr_t pte2_xp; // extended pointer on PT2[ix2].attr |
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272 | uint32_t pte2_attr; // PT2[ix2].attr current value |
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273 | uint32_t pte2_ppn; // PT2[ix2].ppn current value |
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274 | bool_t atomic; |
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275 | |
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276 | #if GPT_LOCK_WATCHDOG |
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277 | uint32_t count = 0; |
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278 | #endif |
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279 | |
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280 | // get cluster and local pointer on GPT |
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281 | cxy_t gpt_cxy = GET_CXY( gpt_xp ); |
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282 | gpt_t * gpt_ptr = GET_PTR( gpt_xp ); |
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283 | |
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284 | #if DEBUG_HAL_GPT_LOCK_PTE |
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285 | thread_t * this = CURRENT_THREAD; |
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286 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
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287 | if( DEBUG_HAL_GPT_LOCK_PTE < cycle ) |
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288 | printk("\n[%s] thread[%x,%x] enters / vpn %x in cluster %x / cycle %d\n", |
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289 | __FUNCTION__, this->process->pid, this->trdid, vpn, gpt_cxy, cycle ); |
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290 | #endif |
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291 | |
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292 | // get indexes in PTI & PT2 from vpn |
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293 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
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294 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
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295 | |
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296 | // get local pointer on PT1 |
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297 | pt1 = hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
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298 | |
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299 | // build extended pointer on PTE1 == PT1[ix1] |
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300 | pte1_xp = XPTR( gpt_cxy , &pt1[ix1] ); |
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301 | |
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302 | // get current PT1 entry value |
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303 | pte1 = hal_remote_l32( pte1_xp ); |
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304 | |
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305 | // If PTE1 is unmapped and unlocked, try to atomically lock this PT1 entry. |
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306 | // This PTE1 locking prevent multiple concurrent PT2 allocations |
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307 | // - only the thread that successfully locked the PTE1 allocates a new PT2 |
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308 | // and updates the PTE1 |
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309 | // - all other threads simply wait until the missing PTE1 is mapped. |
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310 | |
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311 | if( pte1 == 0 ) |
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312 | { |
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313 | // try to atomically lock the PTE1 to prevent concurrent PT2 allocations |
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314 | atomic = hal_remote_atomic_cas( pte1_xp, |
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315 | pte1, |
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316 | pte1 | TSAR_PTE_LOCKED ); |
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317 | if( atomic ) |
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318 | { |
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319 | // allocate one 4 Kbytes physical page for PT2 |
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320 | req.type = KMEM_PPM; |
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321 | req.order = 0; |
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322 | req.flags = AF_ZERO | AF_KERNEL; |
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323 | pt2 = kmem_remote_alloc( gpt_cxy , &req ); |
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324 | |
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325 | if( pt2 == NULL ) |
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326 | { |
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327 | printk("\n[ERROR] in %s : cannot allocate memory for PT2 in cluster %d\n", |
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328 | __FUNCTION__, gpt_cxy ); |
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329 | return -1; |
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330 | } |
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331 | |
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332 | // get the PT2 PPN |
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333 | pt2_ppn = ppm_base2ppn( XPTR( gpt_cxy , pt2 ) ); |
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334 | |
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335 | // build PTE1 |
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336 | pte1 = TSAR_PTE_MAPPED | TSAR_PTE_SMALL | pt2_ppn; |
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337 | |
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338 | // set the PTE1 value in PT1 |
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339 | // this unlocks the PTE1 |
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340 | hal_remote_s32( pte1_xp , pte1 ); |
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341 | hal_fence(); |
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342 | |
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343 | #if (DEBUG_HAL_GPT_LOCK_PTE & 1) |
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344 | if( DEBUG_HAL_GPT_LOCK_PTE < cycle ) |
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345 | printk("\n[%s] thread[%x,%x] allocates a new PT2 for vpn %x in cluster %x\n", |
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346 | __FUNCTION__, this->process->pid, this->trdid, vpn, gpt_cxy ); |
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347 | #endif |
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348 | |
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349 | } // end if atomic |
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350 | } // end if (pte1 == 0) |
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351 | |
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352 | // wait until PTE1 is mapped by another thread |
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353 | while( (pte1 & TSAR_PTE_MAPPED) == 0 ) |
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354 | { |
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355 | pte1 = hal_remote_l32( pte1_xp ); |
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356 | |
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357 | #if GPT_LOCK_WATCHDOG |
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358 | if( count > GPT_LOCK_WATCHDOG ) |
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359 | { |
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360 | thread_t * thread = CURRENT_THREAD; |
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361 | printk("\n[PANIC] in %s : thread[%x,%x] waiting PTE1 / vpn %x / cxy %x / %d iterations\n", |
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362 | __FUNCTION__, thread->process->pid, thread->trdid, vpn, gpt_cxy, count ); |
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363 | hal_core_sleep(); |
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364 | } |
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365 | count++; |
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366 | #endif |
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367 | |
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368 | } |
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369 | |
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370 | // check pte1 because only small page can be locked |
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371 | assert( (pte1 & TSAR_PTE_SMALL), "cannot lock a big page\n"); |
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372 | |
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373 | #if (DEBUG_HAL_GPT_LOCK_PTE & 1) |
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374 | if( DEBUG_HAL_GPT_LOCK_PTE < cycle ) |
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375 | printk("\n[%s] thread[%x,%x] get pte1 %x for vpn %x in cluster %x\n", |
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376 | __FUNCTION__, this->process->pid, this->trdid, pte1, vpn, gpt_cxy ); |
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377 | #endif |
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378 | |
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379 | // get pointer on PT2 base |
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380 | pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( pte1 ); |
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381 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
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382 | |
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383 | // build extended pointers on PT2[ix2].attr |
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384 | pte2_xp = XPTR( gpt_cxy , &pt2[2 * ix2] ); |
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385 | |
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386 | // wait until PTE2 atomically set using a remote CAS |
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387 | do |
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388 | { |
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389 | |
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390 | #if GPT_LOCK_WATCHDOG |
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391 | count = 0; |
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392 | #endif |
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393 | |
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394 | // wait until PTE lock released by the current owner |
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395 | do |
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396 | { |
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397 | pte2_attr = hal_remote_l32( pte2_xp ); |
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398 | |
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399 | #if GPT_LOCK_WATCHDOG |
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400 | if( count > GPT_LOCK_WATCHDOG ) |
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401 | { |
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402 | thread_t * thread = CURRENT_THREAD; |
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403 | printk("\n[PANIC] in %s : thread[%x,%x] waiting PTE2 / vpn %x / cxy %x / %d iterations\n", |
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404 | __FUNCTION__, thread->process->pid, thread->trdid, vpn, gpt_cxy, count ); |
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405 | hal_core_sleep(); |
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406 | } |
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407 | count++; |
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408 | #endif |
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409 | |
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410 | } |
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411 | while( (pte2_attr & TSAR_PTE_LOCKED) != 0 ); |
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412 | |
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413 | // try to atomically set the TSAR_PTE_LOCKED attribute |
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414 | atomic = hal_remote_atomic_cas( pte2_xp, |
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415 | pte2_attr, |
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416 | (pte2_attr | TSAR_PTE_LOCKED) ); |
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417 | } |
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418 | while( atomic == 0 ); |
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419 | |
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420 | // get PTE2.ppn |
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421 | pte2_ppn = hal_remote_l32( pte2_xp + 4 ); |
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422 | |
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423 | #if DEBUG_HAL_GPT_LOCK_PTE |
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424 | cycle = (uint32_t)hal_get_cycles(); |
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425 | if( DEBUG_HAL_GPT_LOCK_PTE < cycle ) |
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426 | printk("\n[%s] thread[%x,%x] exit / vpn %x in cluster %x / attr %x / ppn %x / cycle %d\n", |
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427 | __FUNCTION__, this->process->pid, this->trdid, vpn, gpt_cxy, pte2_attr, pte2_ppn, cycle ); |
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428 | #endif |
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429 | |
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430 | // return PPN and GPT attributes |
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431 | *ppn = pte2_ppn & ((1<<TSAR_MMU_PPN_WIDTH)-1); |
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432 | *attr = tsar2gpt( pte2_attr ); |
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433 | return 0; |
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434 | |
---|
435 | } // end hal_gpt_lock_pte() |
---|
436 | |
---|
437 | //////////////////////////////////////// |
---|
438 | void hal_gpt_unlock_pte( xptr_t gpt_xp, |
---|
439 | vpn_t vpn ) |
---|
440 | { |
---|
441 | uint32_t * pt1; // local pointer on PT1 base |
---|
442 | xptr_t pte1_xp; // extended pointer on PT1[ix1] |
---|
443 | uint32_t pte1; // value of PT1[ix1] entry |
---|
444 | |
---|
445 | uint32_t * pt2; // PT2 base address |
---|
446 | ppn_t pt2_ppn; // PPN of page containing PT2 |
---|
447 | xptr_t pte2_xp; // extended pointer on PT2[ix2].attr |
---|
448 | uint32_t pte2_attr; // PTE2 attribute |
---|
449 | |
---|
450 | // get cluster and local pointer on GPT |
---|
451 | cxy_t gpt_cxy = GET_CXY( gpt_xp ); |
---|
452 | gpt_t * gpt_ptr = GET_PTR( gpt_xp ); |
---|
453 | |
---|
454 | #if DEBUG_HAL_GPT_LOCK_PTE |
---|
455 | thread_t * this = CURRENT_THREAD; |
---|
456 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
457 | if( DEBUG_HAL_GPT_LOCK_PTE < cycle ) |
---|
458 | printk("\n[%s] thread[%x,%x] enters for vpn %x in cluster %x / cycle %d\n", |
---|
459 | __FUNCTION__, this->process->pid, this->trdid, vpn, gpt_cxy, cycle ); |
---|
460 | #endif |
---|
461 | |
---|
462 | // compute indexes in P1 and PT2 |
---|
463 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
464 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
465 | |
---|
466 | // get local pointer on PT1 |
---|
467 | pt1 = hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
468 | |
---|
469 | // build extended pointer on PTE1 == PT1[ix1] |
---|
470 | pte1_xp = XPTR( gpt_cxy , &pt1[ix1] ); |
---|
471 | |
---|
472 | // get current pte1 value |
---|
473 | pte1 = hal_remote_l32( pte1_xp ); |
---|
474 | |
---|
475 | // check PTE1 attributes |
---|
476 | assert( ((pte1 & TSAR_PTE_MAPPED) != 0), "unmapped PTE1\n"); |
---|
477 | assert( ((pte1 & TSAR_PTE_SMALL ) != 0), "big page PTE1\n"); |
---|
478 | |
---|
479 | // get pointer on PT2 base |
---|
480 | pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( pte1 ); |
---|
481 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
482 | |
---|
483 | // build extended pointers on PT2[ix2].attr |
---|
484 | pte2_xp = XPTR( gpt_cxy , &pt2[2 * ix2] ); |
---|
485 | |
---|
486 | // get PT2[ix2].attr |
---|
487 | pte2_attr = hal_remote_l32( pte2_xp ); |
---|
488 | |
---|
489 | // check PTE2 attributes |
---|
490 | assert( ((pte2_attr & TSAR_PTE_MAPPED) != 0), "unmapped PTE2\n"); |
---|
491 | assert( ((pte2_attr & TSAR_PTE_LOCKED) != 0), "unlocked PTE2\n"); |
---|
492 | |
---|
493 | // reset TSAR_PTE_LOCKED attribute |
---|
494 | hal_remote_s32( pte2_xp , pte2_attr & ~TSAR_PTE_LOCKED ); |
---|
495 | |
---|
496 | #if DEBUG_HAL_GPT_LOCK_PTE |
---|
497 | cycle = (uint32_t)hal_get_cycles(); |
---|
498 | if( DEBUG_HAL_GPT_LOCK_PTE < cycle ) |
---|
499 | printk("\n[%s] thread[%x,%x] unlocks vpn %x in cluster %x / cycle %d\n", |
---|
500 | __FUNCTION__, this->process->pid, this->trdid, vpn, gpt_cxy, cycle ); |
---|
501 | #endif |
---|
502 | |
---|
503 | } // end hal_gpt_unlock_pte() |
---|
504 | |
---|
505 | |
---|
506 | /////////////////////////////////////// |
---|
507 | void hal_gpt_set_pte( xptr_t gpt_xp, |
---|
508 | vpn_t vpn, |
---|
509 | uint32_t attr, |
---|
510 | ppn_t ppn ) |
---|
511 | { |
---|
512 | cxy_t gpt_cxy; // target GPT cluster |
---|
513 | gpt_t * gpt_ptr; // target GPT local pointer |
---|
514 | |
---|
515 | uint32_t * pt1; // local pointer on PT1 base |
---|
516 | xptr_t pte1_xp; // extended pointer on PT1 entry |
---|
517 | uint32_t pte1; // PT1 entry value if PTE1 |
---|
518 | |
---|
519 | uint32_t * pt2; // local pointer on PT2 base |
---|
520 | ppn_t pt2_ppn; // PPN of PT2 |
---|
521 | xptr_t pte2_attr_xp; // extended pointer on PT2[ix2].attr |
---|
522 | xptr_t pte2_ppn_xp; // extended pointer on PT2[ix2].ppn |
---|
523 | uint32_t pte2_attr; // current value of PT2[ix2].attr |
---|
524 | |
---|
525 | uint32_t ix1; // index in PT1 |
---|
526 | uint32_t ix2; // index in PT2 |
---|
527 | |
---|
528 | uint32_t tsar_attr; // PTE attributes for TSAR MMU |
---|
529 | uint32_t small; // requested PTE is for a small page |
---|
530 | |
---|
531 | // get cluster and local pointer on GPT |
---|
532 | gpt_cxy = GET_CXY( gpt_xp ); |
---|
533 | gpt_ptr = GET_PTR( gpt_xp ); |
---|
534 | |
---|
535 | // compute indexes in PT1 and PT2 |
---|
536 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
537 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
538 | |
---|
539 | #if DEBUG_HAL_GPT_SET_PTE |
---|
540 | thread_t * this = CURRENT_THREAD; |
---|
541 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
542 | if( DEBUG_HAL_GPT_SET_PTE < cycle ) |
---|
543 | printk("\n[%s] thread[%x,%x] enter gpt (%x,%x) / vpn %x / attr %x / ppn %x\n", |
---|
544 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, &gpt_ptr->ptr, vpn, attr, ppn ); |
---|
545 | #endif |
---|
546 | |
---|
547 | small = attr & GPT_SMALL; |
---|
548 | |
---|
549 | // get local pointer on PT1 |
---|
550 | pt1 = hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
551 | |
---|
552 | // compute tsar attributes from generic attributes |
---|
553 | tsar_attr = gpt2tsar( attr ); |
---|
554 | |
---|
555 | // build extended pointer on PTE1 = PT1[ix1] |
---|
556 | pte1_xp = XPTR( gpt_cxy , &pt1[ix1] ); |
---|
557 | |
---|
558 | // get current pte1 value |
---|
559 | pte1 = hal_remote_l32( pte1_xp ); |
---|
560 | |
---|
561 | if( small == 0 ) ///////////////// map a big page in PT1 |
---|
562 | { |
---|
563 | |
---|
564 | // check PT1 entry not mapped |
---|
565 | assert( (pte1 == 0) , "try to set a big page in an already mapped PTE1\n" ); |
---|
566 | |
---|
567 | // check VPN aligned |
---|
568 | assert( (ix2 == 0) , "illegal vpn for a big page\n" ); |
---|
569 | |
---|
570 | // check PPN aligned |
---|
571 | assert( ((ppn & 0x1FF) == 0) , "illegal ppn for a big page\n" ); |
---|
572 | |
---|
573 | // set the PTE1 value in PT1 |
---|
574 | pte1 = (tsar_attr & TSAR_MMU_PTE1_ATTR_MASK) | ((ppn >> 9) & TSAR_MMU_PTE1_PPN_MASK); |
---|
575 | hal_remote_s32( pte1_xp , pte1 ); |
---|
576 | hal_fence(); |
---|
577 | |
---|
578 | #if DEBUG_HAL_GPT_SET_PTE |
---|
579 | if( DEBUG_HAL_GPT_SET_PTE < cycle ) |
---|
580 | printk("\n[%s] thread[%x,%x] map PTE1 / cxy %x / ix1 %x / pt1 %x / pte1 %x\n", |
---|
581 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, ix1, pt1, pte1 ); |
---|
582 | #endif |
---|
583 | |
---|
584 | } |
---|
585 | else ///////////////// map a small page in PT2 |
---|
586 | { |
---|
587 | |
---|
588 | // PTE1 must be mapped because PTE2 must be locked |
---|
589 | assert( (pte1 & TSAR_PTE_MAPPED), "PTE1 must be mapped\n" ); |
---|
590 | |
---|
591 | // get PT2 base |
---|
592 | pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( pte1 ); |
---|
593 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
594 | |
---|
595 | // build extended pointers on PT2[ix2].attr and PT2[ix2].ppn |
---|
596 | pte2_attr_xp = XPTR( gpt_cxy , &pt2[2 * ix2] ); |
---|
597 | pte2_ppn_xp = XPTR( gpt_cxy , &pt2[2 * ix2 + 1] ); |
---|
598 | |
---|
599 | // get current value of PTE2.attr |
---|
600 | pte2_attr = hal_remote_l32( pte2_attr_xp ); |
---|
601 | |
---|
602 | // PTE2 must be locked |
---|
603 | assert( (pte2_attr & TSAR_PTE_LOCKED), "PTE2 must be locked\n" ); |
---|
604 | |
---|
605 | // set PTE2 in PT2 (in this order) |
---|
606 | hal_remote_s32( pte2_ppn_xp , ppn ); |
---|
607 | hal_fence(); |
---|
608 | hal_remote_s32( pte2_attr_xp , tsar_attr ); |
---|
609 | hal_fence(); |
---|
610 | |
---|
611 | #if DEBUG_HAL_GPT_SET_PTE |
---|
612 | thread_t * this = CURRENT_THREAD; |
---|
613 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
614 | if( DEBUG_HAL_GPT_SET_PTE < cycle ) |
---|
615 | printk("\n[%s] thread[%x,%x] map PTE2 / cxy %x / ix2 %x / pt2 %x / attr %x / ppn %x\n", |
---|
616 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, ix2, pt2, tsar_attr, ppn ); |
---|
617 | #endif |
---|
618 | |
---|
619 | } |
---|
620 | } // end of hal_gpt_set_pte() |
---|
621 | |
---|
622 | /////////////////////////////////////// |
---|
623 | void hal_gpt_reset_pte( xptr_t gpt_xp, |
---|
624 | vpn_t vpn ) |
---|
625 | { |
---|
626 | cxy_t gpt_cxy; // target GPT cluster |
---|
627 | gpt_t * gpt_ptr; // target GPT local pointer |
---|
628 | |
---|
629 | uint32_t ix1; // index in PT1 |
---|
630 | uint32_t ix2; // index in PT2 |
---|
631 | |
---|
632 | uint32_t * pt1; // PT1 base address |
---|
633 | xptr_t pte1_xp; // extended pointer on PT1[ix1] |
---|
634 | uint32_t pte1; // PT1 entry value |
---|
635 | |
---|
636 | uint32_t * pt2; // PT2 base address |
---|
637 | ppn_t pt2_ppn; // PPN of PT2 |
---|
638 | xptr_t pte2_attr_xp; // extended pointer on PT2[ix2].attr |
---|
639 | xptr_t pte2_ppn_xp; // extended pointer on PT2[ix2].ppn |
---|
640 | |
---|
641 | // get cluster and local pointer on GPT |
---|
642 | gpt_cxy = GET_CXY( gpt_xp ); |
---|
643 | gpt_ptr = GET_PTR( gpt_xp ); |
---|
644 | |
---|
645 | // get ix1 & ix2 indexes |
---|
646 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
647 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
648 | |
---|
649 | // get local pointer on PT1 base |
---|
650 | pt1 = hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
651 | |
---|
652 | // build extended pointer on PTE1 = PT1[ix1] |
---|
653 | pte1_xp = XPTR( gpt_cxy , &pt1[ix1] ); |
---|
654 | |
---|
655 | // get current PTE1 value |
---|
656 | pte1 = hal_remote_l32( pte1_xp ); |
---|
657 | |
---|
658 | if( (pte1 & TSAR_PTE_MAPPED) == 0 ) // PTE1 unmapped => do nothing |
---|
659 | { |
---|
660 | return; |
---|
661 | } |
---|
662 | |
---|
663 | if( (pte1 & TSAR_PTE_SMALL) == 0 ) // it's a PTE1 => unmap it from PT1 |
---|
664 | { |
---|
665 | hal_remote_s32( pte1_xp , 0 ); |
---|
666 | hal_fence(); |
---|
667 | |
---|
668 | #if DEBUG_HAL_GPT_RESET_PTE |
---|
669 | thread_t * this = CURRENT_THREAD; |
---|
670 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
671 | if( DEBUG_HAL_GPT_RESET_PTE < cycle ) |
---|
672 | printk("\n[%s] thread[%x,%x] unmap PTE1 / cxy %x / vpn %x / ix1 %x\n", |
---|
673 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, vpn, ix1 ); |
---|
674 | #endif |
---|
675 | |
---|
676 | return; |
---|
677 | } |
---|
678 | else // it's a PTE2 => unmap it from PT2 |
---|
679 | { |
---|
680 | // get PT2 base |
---|
681 | pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( pte1 ); |
---|
682 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
683 | |
---|
684 | // build extended pointer on PT2[ix2].attr and PT2[ix2].ppn |
---|
685 | pte2_attr_xp = XPTR( gpt_cxy , &pt2[2 * ix2] ); |
---|
686 | pte2_ppn_xp = XPTR( gpt_cxy , &pt2[2 * ix2 + 1] ); |
---|
687 | |
---|
688 | // unmap the PTE2 |
---|
689 | hal_remote_s32( pte2_attr_xp , 0 ); |
---|
690 | hal_fence(); |
---|
691 | hal_remote_s32( pte2_ppn_xp , 0 ); |
---|
692 | hal_fence(); |
---|
693 | |
---|
694 | #if DEBUG_HAL_GPT_RESET_PTE |
---|
695 | thread_t * this = CURRENT_THREAD; |
---|
696 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
697 | if( DEBUG_HAL_GPT_RESET_PTE < cycle ) |
---|
698 | printk("\n[%s] thread[%x,%x] unmap PTE2 / cxy %x / vpn %x / ix2 %x\n", |
---|
699 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, vpn, ix2 ); |
---|
700 | #endif |
---|
701 | |
---|
702 | return; |
---|
703 | } |
---|
704 | } // end hal_gpt_reset_pte() |
---|
705 | |
---|
706 | //////////////////////////////////////// |
---|
707 | void hal_gpt_get_pte( xptr_t gpt_xp, |
---|
708 | vpn_t vpn, |
---|
709 | uint32_t * attr, |
---|
710 | ppn_t * ppn ) |
---|
711 | { |
---|
712 | uint32_t * pt1; // local pointer on PT1 base |
---|
713 | uint32_t pte1; // PTE1 value |
---|
714 | |
---|
715 | uint32_t * pt2; // local pointer on PT2 base |
---|
716 | ppn_t pt2_ppn; // PPN of page containing the PT2 |
---|
717 | xptr_t pte2_attr_xp; // extended pointer on PT2[ix2].attr |
---|
718 | xptr_t pte2_ppn_xp; // extended pointer on PT2[ix2].ppn |
---|
719 | uint32_t pte2_attr; // current value of PT2[ix2].attr |
---|
720 | ppn_t pte2_ppn; // current value of PT2[ix2].ppn |
---|
721 | |
---|
722 | // get cluster and local pointer on GPT |
---|
723 | cxy_t gpt_cxy = GET_CXY( gpt_xp ); |
---|
724 | gpt_t * gpt_ptr = GET_PTR( gpt_xp ); |
---|
725 | |
---|
726 | // compute indexes in PT1 and PT2 |
---|
727 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
728 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
729 | |
---|
730 | // get PT1 base |
---|
731 | pt1 = hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
732 | |
---|
733 | // get pte1 |
---|
734 | pte1 = hal_remote_l32( XPTR( gpt_cxy , &pt1[ix1] ) ); |
---|
735 | |
---|
736 | // check PTE1 mapped |
---|
737 | if( (pte1 & TSAR_PTE_MAPPED) == 0 ) // PTE1 unmapped |
---|
738 | { |
---|
739 | *attr = 0; |
---|
740 | *ppn = 0; |
---|
741 | return; |
---|
742 | } |
---|
743 | |
---|
744 | // access GPT |
---|
745 | if( (pte1 & TSAR_PTE_SMALL) == 0 ) // it's a PTE1 |
---|
746 | { |
---|
747 | // get PPN & ATTR |
---|
748 | *attr = tsar2gpt( TSAR_MMU_ATTR_FROM_PTE1( pte1 ) ); |
---|
749 | *ppn = TSAR_MMU_PPN1_FROM_PTE1( pte1 ) | (vpn & ((1<<TSAR_MMU_IX2_WIDTH)-1)); |
---|
750 | } |
---|
751 | else // it's a PTE2 |
---|
752 | { |
---|
753 | // compute PT2 base address |
---|
754 | pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( pte1 ); |
---|
755 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
756 | |
---|
757 | // build extended pointer on PT2[ix2].attr and PT2[ix2].ppn |
---|
758 | pte2_attr_xp = XPTR( gpt_cxy , &pt2[2 * ix2] ); |
---|
759 | pte2_ppn_xp = XPTR( gpt_cxy , &pt2[2 * ix2 + 1] ); |
---|
760 | |
---|
761 | // get current value of PTE2.attr & PTE2.ppn |
---|
762 | pte2_attr = hal_remote_l32( pte2_attr_xp ); |
---|
763 | pte2_ppn = hal_remote_l32( pte2_ppn_xp ); |
---|
764 | |
---|
765 | // return PPN & GPT attributes |
---|
766 | *ppn = pte2_ppn & ((1<<TSAR_MMU_PPN_WIDTH)-1); |
---|
767 | *attr = tsar2gpt( pte2_attr ); |
---|
768 | } |
---|
769 | } // end hal_gpt_get_pte() |
---|
770 | |
---|
771 | |
---|
772 | /////////////////////////////////////////// |
---|
773 | error_t hal_gpt_pte_copy( gpt_t * dst_gpt, |
---|
774 | vpn_t dst_vpn, |
---|
775 | xptr_t src_gpt_xp, |
---|
776 | vpn_t src_vpn, |
---|
777 | bool_t cow, |
---|
778 | ppn_t * ppn, |
---|
779 | bool_t * mapped ) |
---|
780 | { |
---|
781 | uint32_t src_ix1; // index in SRC PT1 |
---|
782 | uint32_t src_ix2; // index in SRC PT2 |
---|
783 | |
---|
784 | uint32_t dst_ix1; // index in DST PT1 |
---|
785 | uint32_t dst_ix2; // index in DST PT2 |
---|
786 | |
---|
787 | cxy_t src_cxy; // SRC GPT cluster |
---|
788 | gpt_t * src_gpt; // SRC GPT local pointer |
---|
789 | |
---|
790 | uint32_t * src_pt1; // local pointer on SRC PT1 |
---|
791 | uint32_t * dst_pt1; // local pointer on DST PT1 |
---|
792 | |
---|
793 | uint32_t * src_pt2; // local pointer on SRC PT2 |
---|
794 | uint32_t * dst_pt2; // local pointer on DST PT2 |
---|
795 | |
---|
796 | kmem_req_t req; // for PT2 allocation |
---|
797 | |
---|
798 | uint32_t src_pte1; |
---|
799 | uint32_t dst_pte1; |
---|
800 | |
---|
801 | uint32_t src_pte2_attr; |
---|
802 | uint32_t src_pte2_ppn; |
---|
803 | |
---|
804 | page_t * page; |
---|
805 | xptr_t page_xp; |
---|
806 | |
---|
807 | ppn_t src_pt2_ppn; |
---|
808 | ppn_t dst_pt2_ppn; |
---|
809 | |
---|
810 | // get remote src_gpt cluster and local pointer |
---|
811 | src_cxy = GET_CXY( src_gpt_xp ); |
---|
812 | src_gpt = GET_PTR( src_gpt_xp ); |
---|
813 | |
---|
814 | #if DEBUG_HAL_GPT_COPY |
---|
815 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
816 | thread_t * this = CURRENT_THREAD; |
---|
817 | if( DEBUG_HAL_GPT_COPY < cycle ) |
---|
818 | printk("\n[%s] thread[%x,%x] enter / src_cxy %x / dst_cxy %x / cycle %d\n", |
---|
819 | __FUNCTION__, this->process->pid, this->trdid, src_cxy, local_cxy, cycle ); |
---|
820 | #endif |
---|
821 | |
---|
822 | // get remote src_pt1 and local dst_pt1 |
---|
823 | src_pt1 = (uint32_t *)hal_remote_lpt( XPTR( src_cxy , &src_gpt->ptr ) ); |
---|
824 | dst_pt1 = (uint32_t *)dst_gpt->ptr; |
---|
825 | |
---|
826 | // check src_pt1 and dst_pt1 existence |
---|
827 | assert( (src_pt1 != NULL) , "src_pt1 does not exist\n"); |
---|
828 | assert( (dst_pt1 != NULL) , "dst_pt1 does not exist\n"); |
---|
829 | |
---|
830 | // compute SRC indexes |
---|
831 | src_ix1 = TSAR_MMU_IX1_FROM_VPN( src_vpn ); |
---|
832 | src_ix2 = TSAR_MMU_IX2_FROM_VPN( src_vpn ); |
---|
833 | |
---|
834 | // compute DST indexes |
---|
835 | dst_ix1 = TSAR_MMU_IX1_FROM_VPN( dst_vpn ); |
---|
836 | dst_ix2 = TSAR_MMU_IX2_FROM_VPN( dst_vpn ); |
---|
837 | |
---|
838 | // get src_pte1 |
---|
839 | src_pte1 = hal_remote_l32( XPTR( src_cxy , &src_pt1[src_ix1] ) ); |
---|
840 | |
---|
841 | // do nothing if src_pte1 not MAPPED or not SMALL |
---|
842 | if( (src_pte1 & TSAR_PTE_MAPPED) && (src_pte1 & TSAR_PTE_SMALL) ) |
---|
843 | { |
---|
844 | // get dst_pt1 entry |
---|
845 | dst_pte1 = dst_pt1[dst_ix1]; |
---|
846 | |
---|
847 | // map dst_pte1 when this entry is not mapped |
---|
848 | if( (dst_pte1 & TSAR_PTE_MAPPED) == 0 ) |
---|
849 | { |
---|
850 | // allocate one physical page for a new PT2 |
---|
851 | req.type = KMEM_PPM; |
---|
852 | req.order = 0; // 1 small page |
---|
853 | req.flags = AF_KERNEL | AF_ZERO; |
---|
854 | dst_pt2 = kmem_alloc( &req ); |
---|
855 | |
---|
856 | if( dst_pt2 == NULL ) |
---|
857 | { |
---|
858 | printk("\n[ERROR] in %s : cannot allocate PT2\n", __FUNCTION__ ); |
---|
859 | return -1; |
---|
860 | } |
---|
861 | |
---|
862 | // build extended pointer on page descriptor |
---|
863 | page_xp = XPTR( local_cxy , page ); |
---|
864 | |
---|
865 | // get PPN for this new PT2 |
---|
866 | dst_pt2_ppn = ppm_base2ppn( XPTR( local_cxy , dst_pt2 ) ); |
---|
867 | |
---|
868 | // build new dst_pte1 |
---|
869 | dst_pte1 = TSAR_PTE_MAPPED | TSAR_PTE_SMALL | dst_pt2_ppn; |
---|
870 | |
---|
871 | // register it in DST_GPT |
---|
872 | dst_pt1[dst_ix1] = dst_pte1; |
---|
873 | } |
---|
874 | |
---|
875 | // get pointer on src_pt2 |
---|
876 | src_pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( src_pte1 ); |
---|
877 | src_pt2 = GET_PTR( ppm_ppn2base( src_pt2_ppn ) ); |
---|
878 | |
---|
879 | // get pointer on dst_pt2 |
---|
880 | dst_pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( dst_pte1 ); |
---|
881 | dst_pt2 = GET_PTR( ppm_ppn2base( dst_pt2_ppn ) ); |
---|
882 | |
---|
883 | // get attr and ppn from SRC_PT2 |
---|
884 | src_pte2_attr = hal_remote_l32( XPTR( src_cxy , &src_pt2[2 * src_ix2] ) ); |
---|
885 | src_pte2_ppn = hal_remote_l32( XPTR( src_cxy , &src_pt2[2 * src_ix2 + 1] ) ); |
---|
886 | |
---|
887 | // do nothing if src_pte2 not MAPPED |
---|
888 | if( (src_pte2_attr & TSAR_PTE_MAPPED) != 0 ) |
---|
889 | { |
---|
890 | // set PPN in DST PTE2 |
---|
891 | dst_pt2[2 * dst_ix2 + 1] = src_pte2_ppn; |
---|
892 | |
---|
893 | // set attributes in DST PTE2 |
---|
894 | if( cow && (src_pte2_attr & TSAR_PTE_WRITABLE) ) |
---|
895 | { |
---|
896 | dst_pt2[2 * dst_ix2] = (src_pte2_attr | TSAR_PTE_COW) & (~TSAR_PTE_WRITABLE); |
---|
897 | } |
---|
898 | else |
---|
899 | { |
---|
900 | dst_pt2[2 * dst_ix2] = src_pte2_attr; |
---|
901 | } |
---|
902 | |
---|
903 | // return "successfully copied" |
---|
904 | *mapped = true; |
---|
905 | *ppn = src_pte2_ppn; |
---|
906 | |
---|
907 | #if DEBUG_HAL_GPT_COPY |
---|
908 | cycle = (uint32_t)hal_get_cycles; |
---|
909 | if( DEBUG_HAL_GPT_COPY < cycle ) |
---|
910 | printk("\n[%s] thread[%x,%x] exit / copy done for src_vpn %x / dst_vpn %x / cycle %d\n", |
---|
911 | __FUNCTION__, this->process->pid, this->trdid, src_vpn, dst_vpn, cycle ); |
---|
912 | #endif |
---|
913 | |
---|
914 | hal_fence(); |
---|
915 | |
---|
916 | return 0; |
---|
917 | } // end if PTE2 mapped |
---|
918 | } // end if PTE1 mapped |
---|
919 | |
---|
920 | // return "nothing done" |
---|
921 | *mapped = false; |
---|
922 | *ppn = 0; |
---|
923 | |
---|
924 | #if DEBUG_HAL_GPT_COPY |
---|
925 | cycle = (uint32_t)hal_get_cycles; |
---|
926 | if( DEBUG_HAL_GPT_COPY < cycle ) |
---|
927 | printk("\n[%s] thread[%x,%x] exit / nothing done / cycle %d\n", |
---|
928 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
---|
929 | #endif |
---|
930 | |
---|
931 | hal_fence(); |
---|
932 | |
---|
933 | return 0; |
---|
934 | |
---|
935 | } // end hal_gpt_pte_copy() |
---|
936 | |
---|
937 | ///////////////////////////////////////// |
---|
938 | void hal_gpt_set_cow( xptr_t gpt_xp, |
---|
939 | vpn_t vpn_base, |
---|
940 | vpn_t vpn_size ) |
---|
941 | { |
---|
942 | cxy_t gpt_cxy; |
---|
943 | gpt_t * gpt_ptr; |
---|
944 | |
---|
945 | uint32_t ix1; // current |
---|
946 | uint32_t ix2; // current |
---|
947 | |
---|
948 | vpn_t vpn_min; |
---|
949 | vpn_t vpn_max; // included |
---|
950 | |
---|
951 | uint32_t ix1_min; |
---|
952 | uint32_t ix1_max; // included |
---|
953 | |
---|
954 | uint32_t ix2_min; |
---|
955 | uint32_t ix2_max; // included |
---|
956 | |
---|
957 | uint32_t * pt1; |
---|
958 | uint32_t pte1; |
---|
959 | |
---|
960 | uint32_t * pt2; |
---|
961 | ppn_t pt2_ppn; |
---|
962 | uint32_t attr; |
---|
963 | |
---|
964 | // get GPT cluster and local pointer |
---|
965 | gpt_cxy = GET_CXY( gpt_xp ); |
---|
966 | gpt_ptr = GET_PTR( gpt_xp ); |
---|
967 | |
---|
968 | #if DEBUG_HAL_GPT_SET_COW |
---|
969 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
970 | thread_t * this = CURRENT_THREAD; |
---|
971 | if(DEBUG_HAL_GPT_SET_COW < cycle ) |
---|
972 | printk("\n[%s] thread[%x,%x] enter / gpt[%x,%x] / vpn_base %x / vpn_size %x / cycle %d\n", |
---|
973 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, gpt_ptr, vpn_base, vpn_size, cycle ); |
---|
974 | #endif |
---|
975 | |
---|
976 | // get PT1 pointer |
---|
977 | pt1 = (uint32_t *)hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
978 | |
---|
979 | #if (DEBUG_HAL_GPT_SET_COW & 1) |
---|
980 | if(DEBUG_HAL_GPT_SET_COW < cycle ) |
---|
981 | printk("\n[%s] thread[%x,%x] get pt1 = %x\n", |
---|
982 | __FUNCTION__, this->process->pid, this->trdid, pt1 ); |
---|
983 | #endif |
---|
984 | |
---|
985 | vpn_min = vpn_base; |
---|
986 | vpn_max = vpn_base + vpn_size - 1; |
---|
987 | |
---|
988 | ix1_min = TSAR_MMU_IX1_FROM_VPN( vpn_base ); |
---|
989 | ix1_max = TSAR_MMU_IX1_FROM_VPN( vpn_max ); |
---|
990 | |
---|
991 | for( ix1 = ix1_min ; ix1 <= ix1_max ; ix1++ ) |
---|
992 | { |
---|
993 | |
---|
994 | #if (DEBUG_HAL_GPT_SET_COW & 1) |
---|
995 | if(DEBUG_HAL_GPT_SET_COW < cycle ) |
---|
996 | printk("\n[%s] thread[%x,%x] : &pt1[%x] = %x\n", |
---|
997 | __FUNCTION__, this->process->pid, this->trdid, ix1, &pt1[ix1] ); |
---|
998 | #endif |
---|
999 | // get PTE1 value |
---|
1000 | pte1 = hal_remote_l32( XPTR( gpt_cxy , &pt1[ix1] ) ); |
---|
1001 | |
---|
1002 | #if (DEBUG_HAL_GPT_SET_COW & 1) |
---|
1003 | if(DEBUG_HAL_GPT_SET_COW < cycle ) |
---|
1004 | printk("\n[%s] thread[%x,%x] : pt1[%x] = %x\n", |
---|
1005 | __FUNCTION__, this->process->pid, this->trdid, ix1, pte1 ); |
---|
1006 | #endif |
---|
1007 | |
---|
1008 | // only MAPPED & SMALL PTEs are modified |
---|
1009 | if( (pte1 & TSAR_PTE_MAPPED) && (pte1 & TSAR_PTE_SMALL) ) |
---|
1010 | { |
---|
1011 | // get PT2 pointer |
---|
1012 | pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( pte1 ); |
---|
1013 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
1014 | |
---|
1015 | #if (DEBUG_HAL_GPT_SET_COW & 1) |
---|
1016 | if(DEBUG_HAL_GPT_SET_COW < cycle ) |
---|
1017 | printk("\n[%s] thread[%x,%x] : get pt2 = %x\n", |
---|
1018 | __FUNCTION__, this->process->pid, this->trdid, pt2 ); |
---|
1019 | #endif |
---|
1020 | ix2_min = (ix1 == ix1_min) ? TSAR_MMU_IX2_FROM_VPN(vpn_min) : 0; |
---|
1021 | ix2_max = (ix1 == ix1_max) ? TSAR_MMU_IX2_FROM_VPN(vpn_max) : 511; |
---|
1022 | |
---|
1023 | for( ix2 = ix2_min ; ix2 <= ix2_max ; ix2++ ) |
---|
1024 | { |
---|
1025 | |
---|
1026 | #if (DEBUG_HAL_GPT_SET_COW & 1) |
---|
1027 | if(DEBUG_HAL_GPT_SET_COW < cycle ) |
---|
1028 | printk("\n[%s] thread[%x,%x] : &pte2[%x] = %x\n", |
---|
1029 | __FUNCTION__, this->process->pid, this->trdid, 2*ix2, &pt2[2*ix2] ); |
---|
1030 | #endif |
---|
1031 | // get current PTE2 attributes |
---|
1032 | attr = hal_remote_l32( XPTR( gpt_cxy , &pt2[2*ix2] ) ); |
---|
1033 | |
---|
1034 | #if (DEBUG_HAL_GPT_SET_COW & 1) |
---|
1035 | if(DEBUG_HAL_GPT_SET_COW < cycle ) |
---|
1036 | printk("\n[%s] thread[%x,%x] : pte2[%x] (attr) = %x\n", |
---|
1037 | __FUNCTION__, this->process->pid, this->trdid, 2*ix2, attr ); |
---|
1038 | #endif |
---|
1039 | // only MAPPED PTEs are modified |
---|
1040 | if( attr & TSAR_PTE_MAPPED ) |
---|
1041 | { |
---|
1042 | attr = (attr | TSAR_PTE_COW) & (~TSAR_PTE_WRITABLE); |
---|
1043 | hal_remote_s32( XPTR( gpt_cxy , &pt2[2*ix2] ) , attr ); |
---|
1044 | } |
---|
1045 | } // end loop on ix2 |
---|
1046 | } |
---|
1047 | } // end loop on ix1 |
---|
1048 | |
---|
1049 | #if DEBUG_HAL_GPT_SET_COW |
---|
1050 | cycle = (uint32_t)hal_get_cycles(); |
---|
1051 | if(DEBUG_HAL_GPT_SET_COW < cycle ) |
---|
1052 | printk("\n[%s] thread[%x,%x] exit / cycle %d\n", |
---|
1053 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
---|
1054 | #endif |
---|
1055 | |
---|
1056 | } // end hal_gpt_set_cow() |
---|
1057 | |
---|
1058 | ////////////////////////////////////////// |
---|
1059 | void hal_gpt_update_pte( xptr_t gpt_xp, |
---|
1060 | vpn_t vpn, |
---|
1061 | uint32_t attr, // generic GPT attributes |
---|
1062 | ppn_t ppn ) |
---|
1063 | { |
---|
1064 | uint32_t * pt1; // PT1 base addres |
---|
1065 | uint32_t pte1; // PT1 entry value |
---|
1066 | |
---|
1067 | ppn_t pt2_ppn; // PPN of PT2 |
---|
1068 | uint32_t * pt2; // PT2 base address |
---|
1069 | xptr_t pte2_attr_xp; // exended pointer on pte2.attr |
---|
1070 | xptr_t pte2_ppn_xp; // exended pointer on pte2.ppn |
---|
1071 | |
---|
1072 | uint32_t ix1; // index in PT1 |
---|
1073 | uint32_t ix2; // index in PT2 |
---|
1074 | |
---|
1075 | // check MAPPED, SMALL, and not LOCKED in attr argument |
---|
1076 | assert( ((attr & GPT_MAPPED) != 0), "attribute MAPPED must be set in new attributes\n" ); |
---|
1077 | assert( ((attr & GPT_SMALL ) != 0), "attribute SMALL must be set in new attributes\n" ); |
---|
1078 | assert( ((attr & GPT_LOCKED) == 0), "attribute LOCKED must not be set in new attributes\n" ); |
---|
1079 | |
---|
1080 | // get cluster and local pointer on remote GPT |
---|
1081 | cxy_t gpt_cxy = GET_CXY( gpt_xp ); |
---|
1082 | gpt_t * gpt_ptr = GET_PTR( gpt_xp ); |
---|
1083 | |
---|
1084 | // compute indexes in PT1 and PT2 |
---|
1085 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
1086 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
1087 | |
---|
1088 | // get PT1 base |
---|
1089 | pt1 = (uint32_t *)hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
1090 | |
---|
1091 | // get PTE1 value |
---|
1092 | pte1 = hal_remote_l32( XPTR( gpt_cxy , &pt1[ix1] ) ); |
---|
1093 | |
---|
1094 | // check MAPPED and SMALL in target PTE1 |
---|
1095 | assert( ((pte1 & TSAR_PTE_MAPPED) != 0), "attribute MAPPED must be set in target PTE1\n" ); |
---|
1096 | assert( ((pte1 & TSAR_PTE_SMALL ) != 0), "attribute SMALL must be set in target PTE1\n" ); |
---|
1097 | |
---|
1098 | // get PT2 base |
---|
1099 | pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( pte1 ); |
---|
1100 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
1101 | |
---|
1102 | // build extended pointers on PT2[ix2].attr and PT2[ix2].ppn |
---|
1103 | pte2_attr_xp = XPTR( gpt_cxy , &pt2[2 * ix2] ); |
---|
1104 | pte2_ppn_xp = XPTR( gpt_cxy , &pt2[2 * ix2 + 1] ); |
---|
1105 | |
---|
1106 | |
---|
1107 | // check MAPPED in target PTE2 |
---|
1108 | assert( ((hal_remote_l32(pte2_attr_xp) & TSAR_PTE_MAPPED) != 0), |
---|
1109 | "attribute MAPPED must be set in target PTE2\n" ); |
---|
1110 | |
---|
1111 | // set PTE2 in this order |
---|
1112 | hal_remote_s32( pte2_ppn_xp , ppn ); |
---|
1113 | hal_fence(); |
---|
1114 | hal_remote_s32( pte2_attr_xp , gpt2tsar( attr ) ); |
---|
1115 | hal_fence(); |
---|
1116 | |
---|
1117 | } // end hal_gpt_update_pte() |
---|
1118 | |
---|
1119 | |
---|
1120 | |
---|
1121 | |
---|
1122 | |
---|