source: trunk/hal/tsar_mips32/core/hal_kentry.h @ 481

Last change on this file since 481 was 481, checked in by viala@…, 3 years ago

[hal/mips32] Add void type to function prototypes with no parameter

File size: 4.9 KB
RevLine 
[16]1/*
[121]2 * hal_kentry.h - MIPS32 registers mnemonics
[16]3 *
4 * Copyright (c) 2008,2009,2010,2011,2012 Ghassan Almaless
5 * Copyright (c) 2011,2012 UPMC Sorbonne Universites
6 *
7 * This file is part of ALMOS-kernel.
8 *
9 * ALMOS-kernel is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2.0 of the License.
12 *
13 * ALMOS-kernel is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with ALMOS-kernel; if not, write to the Free Software Foundation,
20 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 */
22
23#ifndef _HAL_KENTRY_H_
24#define _HAL_KENTRY_H_
25
[406]26//////////////////////////////////////////////////////////////////////////////////////////
27// This file defines the MIPS32 specific mnemonics to access the "uzone", that is
28// a fixed size array of 32 bits integers, used by the kentry function to save/restore
29// the MIPS32 CPU registers, at each exception / interruption / syscall.
30// It also defines several initial values for the SR register.
31//
32// This file is included in the hal_kentry.S, hal_syscall.c, hal_exception.c,
33// and hal_context.c files.
34//////////////////////////////////////////////////////////////////////////////////////////
[121]35
[16]36
[406]37/****************************************************************************************
[408]38 * This structure defines the cpu_uzone dynamically allocated in the kernel stack
39 * by the hal_kentry assembly code for the TSAR_MIPS32 architecture.
40 * WARNING : It is replicated in hal_kentry.S file.
[406]41 ***************************************************************************************/
42
43#define      UZ_MODE         0    /* c2_mode */             
[407]44#define      UZ_AT           1    /* at_01   */
45#define      UZ_V0           2    /* v0_02   */
46#define      UZ_V1           3    /* v1_03   */
47#define      UZ_A0           4    /* a0_04   */
48#define      UZ_A1           5    /* a1_05   */
49#define      UZ_A2           6    /* a2_06   */
50#define      UZ_A3           7    /* a3_07   */
51#define      UZ_T0           8    /* t0_08   */
52#define      UZ_T1           9    /* t1_09   */
53#define      UZ_T2           10   /* t2_10   */
54#define      UZ_T3           11   /* t3_11   */
55#define      UZ_T4           12   /* t4_12   */
56#define      UZ_T5           13   /* t5_13   */
57#define      UZ_T6           14   /* t6_14   */
58#define      UZ_T7           15   /* t7_15   */
[408]59#define      UZ_S0           16   /* s0_16   */
60#define      UZ_S1           17   /* s1_17   */
61#define      UZ_S2           18   /* s2_18   */
62#define      UZ_S3           19   /* s3_19   */
63#define      UZ_S4           20   /* s4_20   */
64#define      UZ_S5           21   /* s5_21   */
65#define      UZ_S6           22   /* s6_22   */
66#define      UZ_S7           23   /* s7_23   */
67#define      UZ_T8           24   /* t8_24   */
68#define      UZ_T9           25   /* t9_25   */
[406]69
[408]70#define      UZ_LO           26
71#define      UZ_HI           27
[406]72
[408]73#define      UZ_GP           28   /* gp_28   */
74#define      UZ_SP           29   /* sp_29   */
75#define      UZ_S8           30   /* s8_30   */
76#define      UZ_RA           31   /* ra_31   */
77
78#define      UZ_PTPR         32   /* c2_ptpr */
79#define      UZ_EPC          33   /* c0_epc  */
80#define      UZ_SR           34   /* c0_sr   */
81#define      UZ_TH           35   /* c0_th   */
82#define      UZ_CR           36   /* c0_cr   */
83
84#define      UZ_REGS         37
85
[406]86/*************************************************************************************
87 * The hal_kentry_enter() function is the unique kernel entry point in case of
88 * exception, interrupt, or syscall for the TSAR_MIPS32 architecture. 
[408]89 * It can be executed by a core in user mode (in case of exception or syscall),
90 * or by a core already in kernel mode (in case of interrupt).
[406]91 *
[408]92 * In both cases it allocates an "uzone" space in the kernel stack to save the
93 * CPU registers values, desactivates the MMU, and calls the relevant handler
94 * (exception/interrupt/syscall)
[406]95 *
[408]96 * After handler execution, it restores the CPU context from the uzone and jumps
97 * to address contained in EPC calling hal_kentry_eret()
[406]98 ************************************************************************************/
[481]99void hal_kentry_enter( void );
[406]100
101/*************************************************************************************
102 * The hal_kentry_eret() function contains only the assembly "eret" instruction,
[408]103 * that reset the EXL bit in the c0_sr register, and jump to the address
[406]104 * contained in the c0_epc register.
105 * ************************************************************************************/
[481]106void hal_kentry_eret( void );
[406]107
[121]108#endif  /* _HAL_KENTRY_H_ */
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