source: trunk/hal/tsar_mips32/core/hal_kentry.h @ 407

Last change on this file since 407 was 407, checked in by alain, 5 years ago

First implementation of fork/exec.

File size: 4.8 KB
Line 
1/*
2 * hal_kentry.h - MIPS32 registers mnemonics
3 *
4 * Copyright (c) 2008,2009,2010,2011,2012 Ghassan Almaless
5 * Copyright (c) 2011,2012 UPMC Sorbonne Universites
6 *
7 * This file is part of ALMOS-kernel.
8 *
9 * ALMOS-kernel is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2.0 of the License.
12 *
13 * ALMOS-kernel is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with ALMOS-kernel; if not, write to the Free Software Foundation,
20 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 */
22
23#ifndef _HAL_KENTRY_H_
24#define _HAL_KENTRY_H_
25
26//////////////////////////////////////////////////////////////////////////////////////////
27// This file defines the MIPS32 specific mnemonics to access the "uzone", that is
28// a fixed size array of 32 bits integers, used by the kentry function to save/restore
29// the MIPS32 CPU registers, at each exception / interruption / syscall.
30// It also defines several initial values for the SR register.
31//
32// This file is included in the hal_kentry.S, hal_syscall.c, hal_exception.c,
33// and hal_context.c files.
34//////////////////////////////////////////////////////////////////////////////////////////
35
36
37/****************************************************************************************
38 * This structure defines the cpu_uzone for TSAR MIPS32, as well as the
39 *  mnemonics used by the hal_kentry assembly code.
40 ***************************************************************************************/
41
42#define      UZ_MODE         0    /* c2_mode */             
43#define      UZ_AT           1    /* at_01   */
44#define      UZ_V0           2    /* v0_02   */
45#define      UZ_V1           3    /* v1_03   */
46#define      UZ_A0           4    /* a0_04   */
47#define      UZ_A1           5    /* a1_05   */
48#define      UZ_A2           6    /* a2_06   */
49#define      UZ_A3           7    /* a3_07   */
50#define      UZ_T0           8    /* t0_08   */
51#define      UZ_T1           9    /* t1_09   */
52#define      UZ_T2           10   /* t2_10   */
53#define      UZ_T3           11   /* t3_11   */
54#define      UZ_T4           12   /* t4_12   */
55#define      UZ_T5           13   /* t5_13   */
56#define      UZ_T6           14   /* t6_14   */
57#define      UZ_T7           15   /* t7_15   */
58#define      UZ_T8           16   /* t8_24   */
59#define      UZ_T9           17   /* t9_25   */
60#define      UZ_S0           18   /* s0_16   */
61#define      UZ_S1           19   /* s1_17   */
62#define      UZ_S2           20   /* s2_18   */
63#define      UZ_S3           21   /* s3_19   */
64#define      UZ_S4           22   /* s4_20   */
65#define      UZ_S5           23   /* s5_21   */
66#define      UZ_S6           24   /* s6_22   */
67#define      UZ_S7           25   /* s7_23   */
68#define      UZ_S8           26   /* s8_30   */
69#define      UZ_GP           27   /* gp_28   */
70#define      UZ_RA           28   /* ra_31   */
71#define      UZ_EPC          29   /* c0_epc  */
72#define      UZ_CR           30   /* c0_cr   */
73#define      UZ_SP           31   /* sp_29   */
74#define      UZ_SR           32   /* c0_sr   */
75#define      UZ_LO           33
76#define      UZ_HI           34
77
78#define      UZ_REGS         35
79
80/*************************************************************************************
81 * The hal_kentry_enter() function is the unique kernel entry point in case of
82 * exception, interrupt, or syscall for the TSAR_MIPS32 architecture. 
83 *
84 * When we enter the kernel, we test the status register:
85 * - If the core is in user mode, we desactivate the MMU, and we save
86 *   the core context in the uzone of the calling thread descriptor.
87 * - If the core is already in kernel mode (in case of interrupt),
88 *   we save the context in the kernel stack.
89 * - In both cases, we increment the cores_in_kernel variable,
90 *   and we call the relevant exception/interrupt/syscall handler
91 *
92 * When we exit the kernel after handler execution:
93 * - we restore the core context from the uzone and return to user space,
94 *   calling the hal_kentry_eret()
95 ************************************************************************************/
96void hal_kentry_enter();
97
98/*************************************************************************************
99 * The hal_kentry_eret() function contains only the assembly "eret" instruction,
100 * that and the EXL bit in the c0_sr register, and jump to the address
101 * contained in the c0_epc register.
102 * ************************************************************************************/
103void hal_kentry_eret();
104
105#endif  /* _HAL_KENTRY_H_ */
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