source: trunk/hal/tsar_mips32/core/mips32_context.h @ 254

Last change on this file since 254 was 62, checked in by max@…, 5 years ago

create the core/ sub-directory for tsar

File size: 3.0 KB
Line 
1/*
2 * mips32_context.h - structures used to save MIPS32 CPU & FPU registers
3 *
4 * Author  Alain Greiner    (2016)
5 *
6 * Copyright (c) UPMC Sorbonne Universites
7 *
8 * This file is part of ALMOS-MKH.
9 *
10 * ALMOS-MKH is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2.0 of the License.
13 *
14 * ALMOS-MKH is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with ALMOS-MKH; if not, write to the Free Software Foundation,
21 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24#ifndef  _MIPS32_CONTEXT_H_
25#define  _MIPS32_CONTEXT_H_
26
27//////////////////////////////////////////////////////////////////////////////////////////
28// This file defines the MIPPS32specific structures, that are used to save /restore
29// MIPS32 CPU and FPU registers at context swich.
30//////////////////////////////////////////////////////////////////////////////////////////
31
32/****************************************************************************************
33 * This defines the "mips32_cpu_context_t" structure, containing general registers,
34 * as well as CP0 or CP2 registers.
35 * These registers are saved/restored at each context switch.
36 * It can be accessed through a void* pointer contained in the thread descriptor.
37 *
38 * WARNING : update the hal_cpu_context_save() and hal_cpu_context_restore()
39 *           functions when modifying this structure.
40 ***************************************************************************************/
41
42typedef struct mips_32_cpu_context_s
43{
44        uint32_t s0_16;      // slot 0
45        uint32_t s1_17;      // slot 1
46        uint32_t s2_18;      // slot 2
47        uint32_t s3_19;      // slot 3
48        uint32_t s4_20;      // slot 4
49        uint32_t s5_21;      // slot 5
50        uint32_t s6_22;      // slot 6
51        uint32_t s7_23;      // slot 7
52        uint32_t sp_29;      // slot 8
53        uint32_t fp_30;      // slot 9
54        uint32_t ra_31;      // slot 10
55        uint32_t c0_sr;      // slot 11
56        uint32_t c0_th;      // slot 12
57        uint32_t c2_ptpr;    // slot 13
58        uint32_t c2_mode;    // slot 14
59} 
60mips32_cpu_context_t;
61
62/****************************************************************************************
63 * This defines the "mips32_fpu_context_t" structure, containing all FPU registers
64 * (i.e. CP1 coprocessor registers).
65 * These registers are saved/restored each time the FPU is allocated to a thread.
66 * It can be accessed through a void* pointer contained in the thread descriptor.
67 *
68 * WARNING : update the hal_fpu_context_save() and hal_fpu_context_restore()
69 *           functions when modifying this structure.
70 ***************************************************************************************/
71
72typedef struct mips32_fpu_context_s
73{
74        uint32_t   fpu_regs[32];     
75}
76mips32_fpu_context_t;
77
78
79#endif  /* _MIPS32_CONTEXT_H_ */
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