source: trunk/hal/tsar_mips32/core/mips32_uzone.h @ 280

Last change on this file since 280 was 62, checked in by max@…, 5 years ago

create the core/ sub-directory for tsar

File size: 3.4 KB
Line 
1/*
2 * mips32_uzone.h - structures used to save MIPS32 core registers
3 *
4 * Author  Alain Greiner    (2016)
5 *
6 * Copyright (c) UPMC Sorbonne Universites
7 *
8 * This file is part of ALMOS-MKH.
9 *
10 * ALMOS-MKH is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2.0 of the License.
13 *
14 * ALMOS-MKH is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with ALMOS-MKH; if not, write to the Free Software Foundation,
21 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24#ifndef  _MIPS32_UZONE_REGS_H_
25#define  _MIPS32_UZONE_REGS_H_
26
27//////////////////////////////////////////////////////////////////////////////////////////
28// This file defines the MIPS32 specific mnemonics to access the "uzone", that is
29// a fixed size array of 32 bits integers, used by the kentry function to save/restore
30// the MIPS32 CPU registers, at each exception / interruption / syscall.
31// It also defines several initial values for the SR register.
32//
33// This file is included in the TSAR_MIPS32 specific hal_kentry.S, hal_syscall.c,
34// hal_exception.c, and hal_interrupt.c files.
35//////////////////////////////////////////////////////////////////////////////////////////
36
37/****************************************************************************************
38 * This defines  SR values for TSAR-MIPS32
39 ***************************************************************************************/
40
41#define SR_USR_MODE       0xFC11
42#define SR_USR_MODE_FPU   0x2000FC11
43#define SR_SYS_MODE       0xFC00
44
45/****************************************************************************************
46 * This defines the "uzone" mnemonics and size.
47 ***************************************************************************************/
48
49#define      UZ_KSP          0    // kernel stack pointer
50#define      UZ_AT           1
51#define      UZ_V0           2
52#define      UZ_V1           3
53#define      UZ_A0           4
54#define      UZ_A1           5
55#define      UZ_A2           6
56#define      UZ_A3           7
57#define      UZ_T0           8
58#define      UZ_T1           9
59#define      UZ_T2           10
60#define      UZ_T3           11
61#define      UZ_T4           12
62#define      UZ_T5           13
63#define      UZ_T6           14
64#define      UZ_T7           15
65#define      UZ_T8           16
66#define      UZ_T9           17
67#define      UZ_S0           18
68#define      UZ_S1           19
69#define      UZ_S2           20
70#define      UZ_S3           21
71#define      UZ_S4           22
72#define      UZ_S5           23
73#define      UZ_S6           24
74#define      UZ_S7           25
75#define      UZ_S8           26
76#define      UZ_GP           27
77#define      UZ_RA           28
78#define      UZ_EPC          29   // CP0 Exception Program Counter
79#define      UZ_CR           30   // CP0 Cause register
80#define      UZ_SP           31   // user stack pointer
81#define      UZ_SR           32   // CP0 Status Register
82#define      UZ_LO           33
83#define      UZ_HI           34
84#define      UZ_DEXT         35   // CP2 data paddr extension
85#define      UZ_MODE         36   // CP2 MMU mode
86
87#define      CPU_REGS_NR     37
88
89
90#endif  /* _MIPS32_UZONE_REGS_H_ */
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