source: trunk/hal/tsar_mips32/drivers/soclib_dma.h @ 438

Last change on this file since 438 was 75, checked in by max@…, 5 years ago

Create the drivers/ sub-directory in each hal, and move soclib
into it. Note that soclib is not valid for x86_64, but more
changes will come.

File size: 4.6 KB
Line 
1/*
2 * soclib_dma.h - soclib Multi Channels DMA driver definition.
3 *
4 * Author     Alain Greiner (2017)
5 *
6 * Copyright (c) UPMC Sorbonne Universites
7 *
8 * This file is part of ALMOS-MKH.
9 *
10 * ALMOS-MKH is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2.0 of the License.
13 *
14 * ALMOS-MKH is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with ALMOS-MKH; if not, write to the Free Software Foundation,
21 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24#ifndef _SOCLIB_DMA_H_
25#define _SOCLIB_DMA_H_
26
27/********************************************************************************************
28 * This driver supports the SocLib VciBlockDevice component, that is a simgle channel,
29 * block oriented, external storage controler, supporting only one I/O transaction,
30 * at a given time.
31 *******************************************************************************************/
32
33/********************************************************************************************
34 *       SOCLIB_DMA registers offset
35 *******************************************************************************************/
36
37enum SoclibDmaRegisters
38{
39    DMA_SRC                  = 0,    /*! source buffer 32 LSB address bits                         */
40    DMA_DST                  = 1,    /*! source buffer 32 LSB address bits                         */
41    DMA_LEN                  = 2,    /*! number of bytes (on write) / transfer status (on read)    */
42    DMA_RESET            = 3,    /*! desactivate channel (can be usde to acknowledge IRQ)      */
43    DMA_IRQ_DISABLED = 4,    /*! no IRQ generated if non zero                              */
44    DMA_SRC_EXT      = 5,    /*! source buffer 32 MSB address bits                         */
45    DMA_DST_EXT      = 6,    /*! source buffer 32 MSB address bits                         */
46
47    DMA_SPAN             = 8,    /*! number of registers per channel                           */
48};
49
50/********************************************************************************************
51 *       SOCLIB_DMA status values
52 *******************************************************************************************/
53
54#define DMA_SUCCESS       0
55#define DMA_IDLE          2
56#define DMA_ERROR_READ    1
57#define DMA_ERROR_WRITE   3
58#define DMA_BUSY          4    // or any value larger than 3
59
60
61/********************************************************************************************
62 * This function access the SOCLIB_DMA hardware register to enable interrupts.
63 ********************************************************************************************
64 * @ chdev     : pointer on DMA chdev descriptor.
65 *******************************************************************************************/
66extern void soclib_dma_init( chdev_t * chdev );
67
68/********************************************************************************************
69 * This function is called by the server thread associated to the DMA device.
70 * It access the command embedded in the calling thread descriptor, (format defined in the
71 * dev_dma.h file) and access the SOCLIB_DMA hardware registers to start command execution.
72 * Then it blocks on the THREAD_BLOCKED_DEV_ISR and deschedules, because each DMA channel
73 * can only execute one command at a given time.
74 * It is re-activated by the ISR signaling the transfer completion.
75 ********************************************************************************************
76 * @ thread_xp  : extended pointer on the client thread.
77 *******************************************************************************************/
78extern void soclib_dma_cmd( xptr_t thread_xp );
79
80/********************************************************************************************
81 * This Interrupt Service Routine is executed when the IRQ signaling the completion of
82 * a DMA command is received by a core. It acknowledge the IRQ by accessing the proper
83 * SOCLIB_DMA register, unblock the client thread, and unblock the server thread that
84 * can starts execution of a new command if the waiting queue is not emppty.
85 ********************************************************************************************
86 * @ chdev     : pointer on DMA chdev descriptor.
87 *******************************************************************************************/
88extern void soclib_dma_isr( chdev_t * chdev );
89
90
91#endif  /* _SOCLIB_DMA_H_ */
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