source: trunk/hal/tsar_mips32/drivers/soclib_pic.c @ 424

Last change on this file since 424 was 424, checked in by alain, 6 years ago

cosmetic.

File size: 19.7 KB
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[75]1/*
2 * soclib_pic.c - soclib PIC driver implementation.
3 *
[188]4 * Author  Alain Greiner (2016,2017)
[141]5 *
[75]6 * Copyright (c) UPMC Sorbonne Universites
7 *
8 * This file is part of ALMOS-MKH.
9 *
[141]10 * ALMOS-MKH is free software; you can redistribute it and/or modify it
[75]11 * under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2.0 of the License.
13 *
[141]14 * ALMOS-MKH is distributed in the hope that it will be useful, but
[75]15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
[141]20 * along with ALMOS-MKH; if not, write to the Free Software Foundation,
[75]21 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24#include <hal_types.h>
25#include <chdev.h>
26#include <soclib_pic.h>
27#include <errno.h>
28#include <string.h>
29#include <vfs.h>
[296]30#include <rpc.h>
[188]31#include <cluster.h>
32#include <printk.h>
33#include <core.h>
34#include <thread.h>
[75]35
[188]36//////////////////////////////////////////////////////////////////////////////////////
37//         Extern variables
38//////////////////////////////////////////////////////////////////////////////////////
39
40extern  chdev_directory_t chdev_dir;    // defined in chdev.h / allocated in kerneL-init.c
41
42extern  iopic_input_t  iopic_input;  // defined in dev_pic.h / allocated in kernel_init.c
43extern  lapic_input_t  lapic_input;  // defined in dev_pic.h / allocated in kernel_init.c
44 
[407]45
46
[188]47//////////////////////////////////////////////////////////////////////////////////////
48//        SOCLIB PIC private functions
49//////////////////////////////////////////////////////////////////////////////////////
50
51///////////////////////////////
52uint32_t soclib_pic_wti_alloc()
53{
54    uint32_t index;
55
56    // get pointer on cluster extension for SOCLIB PIC (XCU descriptor)
57    soclib_pic_cluster_t * ext_ptr = LOCAL_CLUSTER->pic_extend;
58
59    assert( (ext_ptr->first_free_wti < ext_ptr->wti_nr) , __FUNCTION__ ,
60            "no free WTI found : too much external IRQs\n");
61
62    // update WTI allocator
63    index = ext_ptr->first_free_wti;
64    ext_ptr->first_free_wti++;
65
66    return index;
67
68}  // end soclib_pic_wti_alloc()
69
70///////////////////////////////////////
71inline uint32_t * soclib_pic_xcu_base()
72{
[205]73    return ((soclib_pic_cluster_t *)(LOCAL_CLUSTER->pic_extend))->xcu_base;
74}
[188]75
[205]76/////////////////////////////////////////////////////////
77inline uint32_t * soclib_pic_remote_xcu_base( cxy_t cxy )
78{
79    soclib_pic_cluster_t * extend;
[188]80
[205]81    // get extended pointer on PIC extension in remote cluster
82    extend = hal_remote_lpt( XPTR( cxy , &cluster_manager.pic_extend ) );
[188]83
[205]84        return (uint32_t *)hal_remote_lpt( XPTR( cxy , &extend->xcu_base ) );
85                 
86}
87
[188]88///////////////////////////////////////////
89void soclib_pic_xcu_status( lid_t      lid,
90                            uint32_t * hwi_status,
91                            uint32_t * wti_status,
92                            uint32_t * pti_status )
93{
94    // get local XCU segment base
95        uint32_t * base = soclib_pic_xcu_base();
96
97    // read PRIO register
98        uint32_t prio = base[(XCU_PRIO << 5) | lid];
99
100    *wti_status = (prio & 0x4) ? (((prio >> 24) & 0x1F) + 1) : 0;
101    *hwi_status = (prio & 0x2) ? (((prio >> 16) & 0x1F) + 1) : 0;
102    *pti_status = (prio & 0x1) ? (((prio >>  8) & 0x1F) + 1) : 0;
103
104}
105
[279]106////////////////////////////////////////////////////
107inline uint32_t soclib_pic_xcu_ack( uint32_t * reg )
108{
109    return *reg;
110}
111
[188]112/////////////////////////////
113void soclib_pic_irq_handler()
114{
115    uint32_t   hwi_status;   // HWI index + 1  / no pending HWI if 0
116    uint32_t   wti_status;   // WTI index + 1  / no pending WTI if 0
117    uint32_t   pti_status;   // PTI index + 1  / no pending PTI if 0
118    chdev_t  * src_chdev;    // pointer on source chdev descriptor
[279]119    uint32_t   index;        // WTI / HWI / PTI index
[188]120
[406]121    uint32_t * xcu_base = soclib_pic_xcu_base();
[188]122
[406]123    core_t   * core = CURRENT_THREAD->core;
124
[188]125    // get XCU status
126    soclib_pic_xcu_status( core->lid,
127                           &hwi_status,
128                           &wti_status,
129                           &pti_status );
130
[407]131    irq_dmsg("\n[DBG] %s : core[%x,%d] enter / WTI = %x / HWI = %x / WTI = %x\n",
[296]132             __FUNCTION__ , local_cxy , core->lid , wti_status , hwi_status , pti_status );
[279]133
[188]134    // analyse status and handle up to 3 pending IRQ (one WTI, one HWI, one PTI)
135
136    if( wti_status )          // pending WTI
137        {
138        index = wti_status - 1;
139
140        if( index < LOCAL_CLUSTER->cores_nr )   // it is an IPI
141        {
142            assert( (index == core->lid) , __FUNCTION__ , "illegal IPI index" );
143
[407]144            irq_dmsg("\n[DBG] %s : core[%x,%d] received an IPI / cycle %d\n",
[406]145             __FUNCTION__ , local_cxy , core->lid , hal_time_stamp() );
146
147            // acknowledge WTI (this require an XCU read)
148            uint32_t   ack  = xcu_base[(XCU_WTI_REG << 5) | core->lid];
[337]149           
[296]150            // check RPC FIFO,  and activate or create a RPC thread
[337]151            // condition is always true, but we must use the ack value
152            if( ack + 1 ) rpc_check();
[188]153        }
154        else                                    // it is an external device
155        {
156            // get pointer on source chdev
157            src_chdev = ((soclib_pic_core_t *)core->pic_extend)->wti_vector[index];
158
159                    if( src_chdev == NULL )        // strange, but not fatal
160                    {
161                printk("\n[WARNING] in %s : no handler for WTI %d on core %d in cluster %x\n",
162                       __FUNCTION__ , index , core->lid , local_cxy );
163
164                    core->spurious_irqs ++;
165
[279]166                // disable WTI in local XCU controller
167                uint32_t * base = soclib_pic_xcu_base();
168                base[(XCU_MSK_WTI_DISABLE << 5) | core->lid] = 1 << core->lid;
[188]169            }
170            else                                 // call relevant ISR
171            {
[407]172                irq_dmsg("\n[DBG] %s : core[%x,%d] received external WTI %d / cycle %d\n",
[406]173                __FUNCTION__ , local_cxy , core->lid , index , hal_time_stamp() );
[188]174
175                // call ISR
176                    src_chdev->isr( src_chdev );
177            }
178        }
179        }
180
181        if( hwi_status )      // pending HWI
182        {
183        index = hwi_status - 1;
184
185        // get pointer on source chdev
186        src_chdev = ((soclib_pic_core_t *)core->pic_extend)->hwi_vector[index];
187
188                if( src_chdev == NULL )        // strange, but not fatal
189                {
190            printk("\n[WARNING] in %s : no handler for HWI %d on core %d in cluster %x\n",
191                   __FUNCTION__ , index , core->lid , local_cxy );
192
193                core->spurious_irqs ++;
194
[279]195            // disable HWI in local XCU controller
[406]196            xcu_base[(XCU_MSK_HWI_DISABLE << 5) | core->lid] = 1 << core->lid;
[188]197                }
198        else                    // call relevant ISR
199        {
[407]200            irq_dmsg("\n[DBG] %s : core[%x,%d] received HWI %d / cycle %d\n",
[406]201            __FUNCTION__ , local_cxy , core->lid , index , hal_time_stamp() );
[188]202
203            // call ISR
204                    src_chdev->isr( src_chdev );
205        }
206        }
207
208    if( pti_status )      // pending PTI
209        {
210        index = pti_status - 1;
211
[407]212        irq_dmsg("\n[DBG] %s : core[%x,%d] received PTI %d / cycle %d\n",
[406]213        __FUNCTION__ , core->lid , local_cxy , index , hal_time_stamp() );
[188]214
215        assert( (index == core->lid) , __FUNCTION__ , "unconsistent PTI index\n");
216
[406]217        // acknowledge PTI (this require a read access to XCU)
218        uint32_t   ack  = xcu_base[(XCU_PTI_ACK << 5) | core->lid];
[188]219
[279]220        // execute all actions related to TICK event
[406]221        // condition is always true, but we must use the ack value
222        if( ack + 1 ) core_clock( core );
[188]223        }
224}  // end soclib_pic_irq_handler()
225
226
227
228
229//////////////////////////////////////////////////////////////////////////////////////
230//         SOCLIC PIC device  generic API
231//////////////////////////////////////////////////////////////////////////////////////
232
233/////////////////////////////////////
234void soclib_pic_init( chdev_t * pic )
235{
236    uint32_t    i;      // for loop on IOPIC inputs
237    uint32_t    x;      // for loop on clusters in a row
238    uint32_t    y;      // for loop on clusters in a column inputs
239    uint32_t    lid;    // for loop on cores in a cluster
240
241    // get target architecture parameters
242    cluster_t * cluster = LOCAL_CLUSTER;
243    uint32_t    x_size  = cluster->x_size;
244    uint32_t    y_size  = cluster->y_size;
245    uint32_t    y_width = cluster->y_width;
246    uint32_t    ncores  = cluster->cores_nr;
247
248    // get IOPIC controller cluster and segment base pointer
249    cxy_t      iopic_seg_cxy = (cxy_t)GET_CXY( pic->base );
250    uint32_t * iopic_seg_ptr = (uint32_t *)GET_PTR( pic->base );
251
[407]252    // reset the IOPIC component registers : disable all input IRQs
[188]253    for( i = 0 ; i < CONFIG_MAX_EXTERNAL_IRQS ; i++ )
254    {
255        xptr_t iopic_seg_xp = XPTR( iopic_seg_cxy,
256                                    iopic_seg_ptr + i*IOPIC_SPAN + IOPIC_MASK ); 
257        hal_remote_sw( iopic_seg_xp , 0 ); 
258    }
259   
260    // GET XCU controller segment base
261    uint32_t * base = soclib_pic_xcu_base();
262
263    // reset the XCU component registers in all clusters:
264    // mask all HWIs, all WTIs, and all PTIs, for all cores   
265    for( x = 0 ; x < x_size ; x++ )
266    {
267        for( y = 0 ; y < y_size ; y++ )
268        {
269            for( lid = 0 ; lid < ncores ; lid++ )
270            {
271                cxy_t cxy = (x<<y_width) + y;
272                xptr_t hwi_mask_xp = XPTR( cxy , base + (XCU_MSK_HWI_DISABLE << 5 | lid) );
273                xptr_t wti_mask_xp = XPTR( cxy , base + (XCU_MSK_WTI_DISABLE << 5 | lid) );
274                xptr_t pti_mask_xp = XPTR( cxy , base + (XCU_MSK_PTI_DISABLE << 5 | lid) );
275                hal_remote_sw( hwi_mask_xp , 0xFFFFFFFF );
276                hal_remote_sw( wti_mask_xp , 0xFFFFFFFF );
277                hal_remote_sw( pti_mask_xp , 0xFFFFFFFF );
278            }
279        }
280    }
281}  // end soclib_pic_init()
282
283//////////////////////////////////////////////////
284void soclib_pic_extend_init( uint32_t * xcu_base )
285{
286    soclib_pic_cluster_t * cluster_ext_ptr;   
287    soclib_pic_core_t    * core_ext_ptr;
288    kmem_req_t             req;
289    uint32_t               lid;
290    uint32_t               idx;
291
292    cluster_t            * cluster = LOCAL_CLUSTER;
293
294    // create core extension for all cores in cluster
295    for( lid = 0 ; lid < cluster->cores_nr ; lid++ )
296    {
297        // allocate memory for core extension
298        req.type     = KMEM_GENERIC;
299        req.size     = sizeof(soclib_pic_core_t);
300        req.flags    = AF_KERNEL;
301        core_ext_ptr = kmem_alloc( &req );
302
303        assert( (core_ext_ptr != NULL) , __FUNCTION__ ,
304                "cannot allocate memory for core extension\n");
305   
306        // reset the HWI / WTI  interrupt vectors
307        for( idx = 0 ; idx < SOCLIB_MAX_HWI ; idx++ ) core_ext_ptr->hwi_vector[idx] = NULL;
308        for( idx = 0 ; idx < SOCLIB_MAX_WTI ; idx++ ) core_ext_ptr->wti_vector[idx] = NULL;
309
310        // register PIC extension in core descriptor
311        cluster->core_tbl[lid].pic_extend = core_ext_ptr;
312    }
313
314    // allocate memory for cluster extension
315    req.type        = KMEM_GENERIC;
316    req.size        = sizeof(soclib_pic_cluster_t);
317    req.flags       = AF_KERNEL;
318    cluster_ext_ptr = kmem_alloc( &req );
319
320    assert( (cluster_ext_ptr != NULL) , __FUNCTION__ ,
321            "cannot allocate memory for cluster extension\n");
322
323    // get XCU characteristics from the XCU config register
324    uint32_t  config = xcu_base[XCU_CONFIG<<5];
325    uint32_t  wti_nr = (config >> 16) & 0xFF; 
326    uint32_t  hwi_nr = (config >> 8 ) & 0xFF; 
327    uint32_t  pti_nr = (config      ) & 0xFF; 
328
329    // initialize the cluster extension
330    // The first WTI slots are for IPIs (one slot per core)
331    cluster_ext_ptr->xcu_base       = xcu_base;
332    cluster_ext_ptr->hwi_nr         = hwi_nr;
333    cluster_ext_ptr->wti_nr         = wti_nr;
334    cluster_ext_ptr->pti_nr         = pti_nr;
335    cluster_ext_ptr->first_free_wti = cluster->cores_nr;
336
337    // register PIC extension in cluster manager
338    cluster->pic_extend = cluster_ext_ptr;
339
340}  // end soclib_pic_extend_init()
341
[75]342////////////////////////////////////////
[188]343void soclib_pic_bind_irq( lid_t     lid,
344                          chdev_t * src_chdev )
[75]345{
[188]346    // get extended & local pointers on PIC chdev descriptor
347    xptr_t     pic_xp  = chdev_dir.pic;
348    cxy_t      pic_cxy = GET_CXY( pic_xp );
349    chdev_t *  pic_ptr = (chdev_t *)GET_PTR( pic_xp );
[75]350
[188]351    // get extended and local pointers on IOPIC  segment base
352    xptr_t     seg_pic_xp  = hal_remote_lwd( XPTR( pic_cxy , &pic_ptr->base ) );
353    cxy_t      seg_pic_cxy = GET_CXY( seg_pic_xp );
354    uint32_t * seg_pic_ptr = (uint32_t *)GET_PTR( seg_pic_xp );
355
356    // get local pointer on XCU segment base
357    uint32_t * seg_xcu_ptr = soclib_pic_xcu_base();
358
359    // get the source chdev functionnal type, channel, and direction
360    uint32_t func    = src_chdev->func;
361    uint32_t channel = src_chdev->channel;
362    bool_t   is_rx   = src_chdev->is_rx;
363
364    if( (func == DEV_FUNC_IOC) || (func == DEV_FUNC_NIC) ||
365        (func == DEV_FUNC_TXT) || (func == DEV_FUNC_IOB) )          // external IRQ => WTI
[75]366    {
[188]367        // get external IRQ index
[407]368        uint32_t  hwi_id;   
369        if     (  func == DEV_FUNC_IOC            ) hwi_id = iopic_input.ioc[channel];
370        else if(  func == DEV_FUNC_TXT  &&  is_rx ) hwi_id = iopic_input.txt_rx[channel];
371        else if(  func == DEV_FUNC_TXT  && !is_rx ) hwi_id = iopic_input.txt_tx[channel];
372        else if( (func == DEV_FUNC_NIC) &&  is_rx ) hwi_id = iopic_input.nic_rx[channel];
373        else if( (func == DEV_FUNC_NIC) && !is_rx ) hwi_id = iopic_input.nic_tx[channel];
374        else if(  func == DEV_FUNC_IOB            ) hwi_id = iopic_input.iob;
[188]375        else      assert( false , __FUNCTION__ , "illegal device functionnal type\n");
376
377        // get a WTI mailbox from local XCU descriptor 
378        uint32_t wti_id = soclib_pic_wti_alloc();
379
380        // register IRQ type and index in chdev
381        src_chdev->irq_type = SOCLIB_TYPE_WTI;
382        src_chdev->irq_id   = wti_id;
383
384        // compute extended pointer on WTI mailbox in local XCU
385        xptr_t wti_xp = XPTR( local_cxy , &seg_xcu_ptr[(XCU_WTI_REG << 5) | wti_id] );
386
387            // set the IOPIC_ADDRESS and IOPIC_EXTEND registers in IOPIC
388        uint32_t lsb_wdata = (uint32_t)wti_xp;
389        uint32_t msb_wdata = (uint32_t)(wti_xp >> 32);
[407]390        xptr_t   lsb_xp = XPTR( seg_pic_cxy , seg_pic_ptr+hwi_id*IOPIC_SPAN+IOPIC_ADDRESS );
391        xptr_t   msb_xp = XPTR( seg_pic_cxy , seg_pic_ptr+hwi_id*IOPIC_SPAN+IOPIC_EXTEND );
[188]392        hal_remote_sw( lsb_xp , lsb_wdata );
393        hal_remote_sw( msb_xp , msb_wdata );
394
[407]395        // enable IRQ in IOPIC
396        hal_remote_sw( XPTR( seg_pic_cxy , seg_pic_ptr+hwi_id*IOPIC_SPAN+IOPIC_MASK ), 1 );
[188]397
398        // update the WTI interrupt vector for core[lid]
399        core_t * core = &LOCAL_CLUSTER->core_tbl[lid];
400        ((soclib_pic_core_t *)core->pic_extend)->wti_vector[wti_id] = src_chdev;
[407]401
402pic_dmsg("\n[DBG] %s : %s / channel = %d / rx = %d / hwi_id = %d / wti_id = %d / cluster = %x\n",
403__FUNCTION__ , chdev_func_str( func ) , channel , is_rx , hwi_id , wti_id , local_cxy );
404
[75]405    }
[188]406    else if( (func == DEV_FUNC_DMA) || (func == DEV_FUNC_MMC) )   // internal IRQ => HWI
407    {
408        // get internal IRQ index
409        uint32_t hwi_id;
410        if( func == DEV_FUNC_DMA ) hwi_id = lapic_input.dma[channel];
411        else                       hwi_id = lapic_input.mmc;
[75]412
[188]413        // register IRQ type and index in chdev
414        src_chdev->irq_type = SOCLIB_TYPE_HWI;
415        src_chdev->irq_id   = hwi_id;
416
417        // update the HWI interrupt vector for core[lid]
418        core_t * core = &LOCAL_CLUSTER->core_tbl[lid];
419        ((soclib_pic_core_t *)core->pic_extend)->wti_vector[hwi_id] = src_chdev;
[407]420
421pic_dmsg("\n[DBG] %s : %s / channel = %d / hwi_id = %d / cluster = %x\n",
422__FUNCTION__ , chdev_func_str( func ) , channel , hwi_id , local_cxy );
423
[188]424    }
425    else
426    {
427        assert( false , __FUNCTION__ , "illegal device functionnal type\n" );
428    } 
429}  // end soclib_pic_bind_irq();
430
[205]431///////////////////////////////////////
432void soclib_pic_enable_irq( lid_t  lid,
433                            xptr_t src_chdev_xp )
[75]434{
[205]435    // get cluster and local pointer on remote src_chdev
436    cxy_t     src_chdev_cxy = GET_CXY( src_chdev_xp );
437    chdev_t * src_chdev_ptr = (chdev_t *)GET_PTR( src_chdev_xp );
[141]438
[205]439    // get local pointer on remote XCU segment base
440    uint32_t * seg_xcu_ptr = soclib_pic_remote_xcu_base( src_chdev_cxy );
441
[188]442    // get the source chdev IRQ type and index
[205]443    uint32_t irq_type = hal_remote_lw( XPTR( src_chdev_cxy , &src_chdev_ptr->irq_type ) );
444    uint32_t irq_id   = hal_remote_lw( XPTR( src_chdev_cxy , &src_chdev_ptr->irq_id ) );
[141]445
[188]446    if( irq_type == SOCLIB_TYPE_HWI )
447    {
[205]448        // enable this HWI in remote XCU controller
449        hal_remote_sw( XPTR( src_chdev_cxy , 
450                       &seg_xcu_ptr[(XCU_MSK_HWI_ENABLE << 5) | lid] ) , (1 << irq_id) );
[188]451    }
452    else if( irq_type == SOCLIB_TYPE_WTI )
453    {
[279]454        // enable this WTI in remote XCU controller
[205]455        hal_remote_sw( XPTR( src_chdev_cxy , 
456                       &seg_xcu_ptr[(XCU_MSK_WTI_ENABLE << 5) | lid] ) , (1 << irq_id) );
[188]457    }
458    else
459    {
460        assert( false , __FUNCTION__ , "illegal IRQ type\n" );
461    }
462} // end soclib_pic_enable_irq()
[75]463
[205]464////////////////////////////////////////
465void soclib_pic_disable_irq( lid_t  lid,
466                             xptr_t src_chdev_xp )
[188]467{
[205]468    // get cluster and local pointer on remote src_chdev
469    cxy_t     src_chdev_cxy = GET_CXY( src_chdev_xp );
470    chdev_t * src_chdev_ptr = (chdev_t *)GET_PTR( src_chdev_xp );
[75]471
[205]472    // get local pointer on remote XCU segment base
473    uint32_t * seg_xcu_ptr = soclib_pic_remote_xcu_base( src_chdev_cxy );
474
[188]475    // get the source chdev IRQ type and index
[205]476    uint32_t irq_type = hal_remote_lw( XPTR( src_chdev_cxy , &src_chdev_ptr->irq_type ) );
477    uint32_t irq_id   = hal_remote_lw( XPTR( src_chdev_cxy , &src_chdev_ptr->irq_id ) );
[75]478
[188]479    if( irq_type == SOCLIB_TYPE_HWI )
480    {
[205]481        // enable this HWI in remote XCU controller
482        hal_remote_sw( XPTR( src_chdev_cxy , 
483                       &seg_xcu_ptr[(XCU_MSK_HWI_DISABLE << 5) | lid] ) , (1 << irq_id) );
[188]484    }
485    else if( irq_type == SOCLIB_TYPE_WTI )
486    {
[279]487        // enable this WTI in remote XCU controller
[205]488        hal_remote_sw( XPTR( src_chdev_cxy , 
489                       &seg_xcu_ptr[(XCU_MSK_WTI_DISABLE << 5) | lid] ) , (1 << irq_id) );
[188]490    }
491    else
492    {
493        assert( false , __FUNCTION__ , "illegal IRQ type\n" );
494    }
495} // end soclib_pic_enable_irq()
[75]496
[188]497///////////////////////////////////////////////
498void soclib_pic_enable_timer( uint32_t period )
[75]499{
[188]500    // calling core local index
501    lid_t  lid = CURRENT_CORE->lid;
[141]502
[188]503    // get XCU segment base
504    uint32_t * base = soclib_pic_xcu_base();
[141]505
[380]506    // set period value in XCU (in cycles)
[407]507    uint32_t cycles = period * SOCLIB_CYCLES_PER_MS;
[380]508    base[(XCU_PTI_PER << 5) | lid] = cycles;
[75]509
[279]510    // enable PTI in local XCU controller
[188]511    base[(XCU_MSK_PTI_ENABLE << 5) | lid] = 1 << lid;
[75]512}
513
[279]514////////////////////////////
515void soclib_pic_enable_ipi()
516{
517    // calling core local index
518    lid_t  lid = CURRENT_CORE->lid;
519
520    // get XCU segment base
521    uint32_t * base = soclib_pic_xcu_base();
522
523    // enable WTI in local XCU controller
524    base[(XCU_MSK_WTI_ENABLE << 5) | lid] = 1 << lid;
525}
526
[188]527///////////////////////////////////////
528void soclib_pic_send_ipi( cxy_t    cxy,
529                          lid_t    lid )
[75]530{
[188]531    // get pointer on local XCU segment base
532    uint32_t * base = soclib_pic_xcu_base();
[141]533
[188]534    // write to WTI mailbox[cxy][lid]
535    hal_remote_sw( XPTR( cxy , &base[(XCU_WTI_REG << 5) | lid] ) , 0 );
536}
[141]537
[407]538/////////////////////////
539void soclib_pic_ack_ipi()
540{
541    // get calling core local index
542    lid_t      lid  = CURRENT_THREAD->core->lid;
[75]543
[407]544    // get pointer on local XCU segment base
545    uint32_t * base = soclib_pic_xcu_base();
[75]546
[407]547    // acknowlege IPI
548    uint32_t   ack  = base[(XCU_WTI_REG << 5) | lid];
549
550    // we must make a fake use for ack value to avoid a warning
[424]551    if( (ack + 1) == 0 ) asm volatile( "nop" );
[407]552}
553   
554
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