source: trunk/hal/tsar_mips32/drivers/soclib_pic.c @ 435

Last change on this file since 435 was 435, checked in by alain, 4 years ago

Fix a bad bug in scheduler...

File size: 20.8 KB
Line 
1/*
2 * soclib_pic.c - soclib PIC driver implementation.
3 *
4 * Author  Alain Greiner (2016,2017)
5 *
6 * Copyright (c) UPMC Sorbonne Universites
7 *
8 * This file is part of ALMOS-MKH.
9 *
10 * ALMOS-MKH is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2.0 of the License.
13 *
14 * ALMOS-MKH is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with ALMOS-MKH; if not, write to the Free Software Foundation,
21 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24#include <hal_types.h>
25#include <chdev.h>
26#include <soclib_pic.h>
27#include <errno.h>
28#include <string.h>
29#include <vfs.h>
30#include <rpc.h>
31#include <cluster.h>
32#include <printk.h>
33#include <core.h>
34#include <thread.h>
35
36//////////////////////////////////////////////////////////////////////////////////////
37//         Extern variables
38//////////////////////////////////////////////////////////////////////////////////////
39
40extern  chdev_directory_t chdev_dir;    // defined in chdev.h / allocated in kerneL-init.c
41
42extern  iopic_input_t  iopic_input;  // defined in dev_pic.h / allocated in kernel_init.c
43extern  lapic_input_t  lapic_input;  // defined in dev_pic.h / allocated in kernel_init.c
44 
45
46
47//////////////////////////////////////////////////////////////////////////////////////
48//        SOCLIB PIC private functions
49//////////////////////////////////////////////////////////////////////////////////////
50
51///////////////////////////////
52uint32_t soclib_pic_wti_alloc()
53{
54    uint32_t index;
55
56    // get pointer on cluster extension for SOCLIB PIC (XCU descriptor)
57    soclib_pic_cluster_t * ext_ptr = LOCAL_CLUSTER->pic_extend;
58
59    assert( (ext_ptr->first_free_wti < ext_ptr->wti_nr) , __FUNCTION__ ,
60            "no free WTI found : too much external IRQs\n");
61
62    // update WTI allocator
63    index = ext_ptr->first_free_wti;
64    ext_ptr->first_free_wti++;
65
66    return index;
67
68}  // end soclib_pic_wti_alloc()
69
70///////////////////////////////////////
71inline uint32_t * soclib_pic_xcu_base()
72{
73    return ((soclib_pic_cluster_t *)(LOCAL_CLUSTER->pic_extend))->xcu_base;
74}
75
76/////////////////////////////////////////////////////////
77inline uint32_t * soclib_pic_remote_xcu_base( cxy_t cxy )
78{
79    soclib_pic_cluster_t * extend;
80
81    // get extended pointer on PIC extension in remote cluster
82    extend = hal_remote_lpt( XPTR( cxy , &cluster_manager.pic_extend ) );
83
84        return (uint32_t *)hal_remote_lpt( XPTR( cxy , &extend->xcu_base ) );
85                 
86}
87
88///////////////////////////////////////////
89void soclib_pic_xcu_status( lid_t      lid,
90                            uint32_t * hwi_status,
91                            uint32_t * wti_status,
92                            uint32_t * pti_status )
93{
94    // get local XCU segment base
95        uint32_t * base = soclib_pic_xcu_base();
96
97    // read PRIO register
98    // in TSAR : XCU output [4*lid] is connected to core [lid]
99        uint32_t prio = base[ (XCU_PRIO << 5) | (lid<<2) ];
100
101    *wti_status = (prio & 0x4) ? (((prio >> 24) & 0x1F) + 1) : 0;
102    *hwi_status = (prio & 0x2) ? (((prio >> 16) & 0x1F) + 1) : 0;
103    *pti_status = (prio & 0x1) ? (((prio >>  8) & 0x1F) + 1) : 0;
104
105}
106
107////////////////////////////////////////////////////
108inline uint32_t soclib_pic_xcu_ack( uint32_t * reg )
109{
110    return *reg;
111}
112
113/////////////////////////////
114void soclib_pic_irq_handler()
115{
116    uint32_t   hwi_status;   // HWI index + 1  / no pending HWI if 0
117    uint32_t   wti_status;   // WTI index + 1  / no pending WTI if 0
118    uint32_t   pti_status;   // PTI index + 1  / no pending PTI if 0
119    chdev_t  * src_chdev;    // pointer on source chdev descriptor
120    uint32_t   index;        // WTI / HWI / PTI index
121
122    uint32_t * xcu_base = soclib_pic_xcu_base();
123
124    core_t   * core = CURRENT_THREAD->core;
125
126    // get XCU status
127    soclib_pic_xcu_status( core->lid,
128                           &hwi_status,
129                           &wti_status,
130                           &pti_status );
131
132#if CONFIG_DEBUG_HAL_IRQS
133uint32_t cycle = (uint32_t)hal_get_cycles();
134if (CONFIG_DEBUG_HAL_IRQS < cycle )
135printk("\n[DBG] %s : core[%x,%d] enter / WTI = %x / HWI = %x / PTI = %x / cycle %d\n",
136__FUNCTION__ , local_cxy , core->lid , wti_status , hwi_status , pti_status, cycle );
137#endif
138
139    // analyse status and handle up to 3 pending IRQ (one WTI, one HWI, one PTI)
140
141    if( wti_status )          // pending WTI
142        {
143        index = wti_status - 1;
144
145        if( index < LOCAL_CLUSTER->cores_nr )   // it is an IPI
146        {
147            assert( (index == core->lid) , __FUNCTION__ , "illegal IPI index" );
148
149#if CONFIG_DEBUG_HAL_IRQS
150if (CONFIG_DEBUG_HAL_IRQS < cycle )
151printk("\n[DBG] %s : core[%x,%d] received an IPI\n", __FUNCTION__ , local_cxy , core->lid );
152#endif
153            // acknowledge WTI (this require an XCU read)
154            uint32_t   ack  = xcu_base[(XCU_WTI_REG << 5) | core->lid];
155           
156            // check RPC FIFO,  and activate or create a RPC thread
157            // condition is always true, but we must use the ack value
158            if( ack + 1 ) rpc_check();
159        }
160        else                                    // it is an external device
161        {
162            // get pointer on source chdev
163            src_chdev = ((soclib_pic_core_t *)core->pic_extend)->wti_vector[index];
164
165                    if( src_chdev == NULL )        // strange, but not fatal
166                    {
167                printk("\n[WARNING] in %s : no handler for WTI %d on core %d in cluster %x\n",
168                       __FUNCTION__ , index , core->lid , local_cxy );
169
170                    core->spurious_irqs ++;
171
172                // disable WTI in local XCU controller
173                uint32_t * base = soclib_pic_xcu_base();
174                base[(XCU_MSK_WTI_DISABLE << 5) | core->lid] = 1 << core->lid;
175            }
176            else                                 // call relevant ISR
177            {
178
179#if CONFIG_DEBUG_HAL_IRQS
180if (CONFIG_DEBUG_HAL_IRQS < cycle )
181printk("\n[DBG] %s : core[%x,%d] received external WTI %d\n",
182__FUNCTION__ , local_cxy , core->lid , index );
183#endif
184                // call ISR
185                    src_chdev->isr( src_chdev );
186            }
187        }
188        }
189
190        if( hwi_status )      // pending HWI
191        {
192        index = hwi_status - 1;
193
194        // get pointer on source chdev
195        src_chdev = ((soclib_pic_core_t *)core->pic_extend)->hwi_vector[index];
196
197                if( src_chdev == NULL )        // strange, but not fatal
198                {
199            printk("\n[WARNING] in %s : no handler for HWI %d on core %d in cluster %x\n",
200                   __FUNCTION__ , index , core->lid , local_cxy );
201
202                core->spurious_irqs ++;
203
204            // disable HWI in local XCU controller
205            xcu_base[(XCU_MSK_HWI_DISABLE << 5) | core->lid] = 1 << core->lid;
206                }
207        else                    // call relevant ISR
208        {
209
210#if CONFIG_DEBUG_HAL_IRQS
211if (CONFIG_DEBUG_HAL_IRQS < cycle )
212printk("\n[DBG] %s : core[%x,%d] received HWI %d\n",
213__FUNCTION__ , local_cxy , core->lid , index );
214#endif
215            // call ISR
216                    src_chdev->isr( src_chdev );
217        }
218        }
219
220    if( pti_status )      // pending PTI
221        {
222        index = pti_status - 1;
223
224        assert( (index == core->lid) , __FUNCTION__ , "unconsistent PTI index\n");
225
226#if CONFIG_DEBUG_HAL_IRQS
227if (CONFIG_DEBUG_HAL_IRQS < cycle )
228printk("\n[DBG] %s : core[%x,%d] received PTI %d\n",
229__FUNCTION__ , core->lid , local_cxy , index );
230#endif
231        // acknowledge PTI (this require a read access to XCU)
232        uint32_t   ack  = xcu_base[(XCU_PTI_ACK << 5) | core->lid];
233
234        // execute all actions related to TICK event
235        // condition is always true, but we must use the ack value
236        if( ack + 1 ) core_clock( core );
237        }
238}  // end soclib_pic_irq_handler()
239
240
241
242
243//////////////////////////////////////////////////////////////////////////////////////
244//         SOCLIC PIC device  generic API
245//////////////////////////////////////////////////////////////////////////////////////
246
247/////////////////////////////////////
248void soclib_pic_init( chdev_t * pic )
249{
250    uint32_t    i;      // for loop on IOPIC inputs
251    uint32_t    x;      // for loop on clusters in a row
252    uint32_t    y;      // for loop on clusters in a column inputs
253    uint32_t    lid;    // for loop on cores in a cluster
254
255    // get target architecture parameters
256    cluster_t * cluster = LOCAL_CLUSTER;
257    uint32_t    x_size  = cluster->x_size;
258    uint32_t    y_size  = cluster->y_size;
259    uint32_t    y_width = cluster->y_width;
260    uint32_t    ncores  = cluster->cores_nr;
261
262    // get IOPIC controller cluster and segment base pointer
263    cxy_t      iopic_seg_cxy = (cxy_t)GET_CXY( pic->base );
264    uint32_t * iopic_seg_ptr = (uint32_t *)GET_PTR( pic->base );
265
266    // reset the IOPIC component registers : disable all input IRQs
267    for( i = 0 ; i < CONFIG_MAX_EXTERNAL_IRQS ; i++ )
268    {
269        xptr_t iopic_seg_xp = XPTR( iopic_seg_cxy,
270                                    iopic_seg_ptr + i*IOPIC_SPAN + IOPIC_MASK ); 
271        hal_remote_sw( iopic_seg_xp , 0 ); 
272    }
273   
274    // GET XCU controller segment base
275    uint32_t * base = soclib_pic_xcu_base();
276
277    // reset the XCU component registers in all clusters:
278    // mask all HWIs, all WTIs, and all PTIs, for all cores   
279    for( x = 0 ; x < x_size ; x++ )
280    {
281        for( y = 0 ; y < y_size ; y++ )
282        {
283            for( lid = 0 ; lid < ncores ; lid++ )
284            {
285                cxy_t cxy = (x<<y_width) + y;
286                xptr_t hwi_mask_xp = XPTR( cxy , base + (XCU_MSK_HWI_DISABLE << 5 | lid) );
287                xptr_t wti_mask_xp = XPTR( cxy , base + (XCU_MSK_WTI_DISABLE << 5 | lid) );
288                xptr_t pti_mask_xp = XPTR( cxy , base + (XCU_MSK_PTI_DISABLE << 5 | lid) );
289                hal_remote_sw( hwi_mask_xp , 0xFFFFFFFF );
290                hal_remote_sw( wti_mask_xp , 0xFFFFFFFF );
291                hal_remote_sw( pti_mask_xp , 0xFFFFFFFF );
292            }
293        }
294    }
295}  // end soclib_pic_init()
296
297//////////////////////////////////////////////////
298void soclib_pic_extend_init( uint32_t * xcu_base )
299{
300    soclib_pic_cluster_t * cluster_ext_ptr;   
301    soclib_pic_core_t    * core_ext_ptr;
302    kmem_req_t             req;
303    uint32_t               lid;
304    uint32_t               idx;
305
306    cluster_t            * cluster = LOCAL_CLUSTER;
307
308    // create core extension for all cores in cluster
309    for( lid = 0 ; lid < cluster->cores_nr ; lid++ )
310    {
311        // allocate memory for core extension
312        req.type     = KMEM_GENERIC;
313        req.size     = sizeof(soclib_pic_core_t);
314        req.flags    = AF_KERNEL;
315        core_ext_ptr = kmem_alloc( &req );
316
317        assert( (core_ext_ptr != NULL) , __FUNCTION__ ,
318                "cannot allocate memory for core extension\n");
319   
320        // reset the HWI / WTI  interrupt vectors
321        for( idx = 0 ; idx < SOCLIB_MAX_HWI ; idx++ ) core_ext_ptr->hwi_vector[idx] = NULL;
322        for( idx = 0 ; idx < SOCLIB_MAX_WTI ; idx++ ) core_ext_ptr->wti_vector[idx] = NULL;
323
324        // register PIC extension in core descriptor
325        cluster->core_tbl[lid].pic_extend = core_ext_ptr;
326    }
327
328    // allocate memory for cluster extension
329    req.type        = KMEM_GENERIC;
330    req.size        = sizeof(soclib_pic_cluster_t);
331    req.flags       = AF_KERNEL;
332    cluster_ext_ptr = kmem_alloc( &req );
333
334    assert( (cluster_ext_ptr != NULL) , __FUNCTION__ ,
335            "cannot allocate memory for cluster extension\n");
336
337    // get XCU characteristics from the XCU config register
338    uint32_t  config = xcu_base[XCU_CONFIG<<5];
339    uint32_t  wti_nr = (config >> 16) & 0xFF; 
340    uint32_t  hwi_nr = (config >> 8 ) & 0xFF; 
341    uint32_t  pti_nr = (config      ) & 0xFF; 
342
343    // initialize the cluster extension
344    // The first WTI slots are for IPIs (one slot per core)
345    cluster_ext_ptr->xcu_base       = xcu_base;
346    cluster_ext_ptr->hwi_nr         = hwi_nr;
347    cluster_ext_ptr->wti_nr         = wti_nr;
348    cluster_ext_ptr->pti_nr         = pti_nr;
349    cluster_ext_ptr->first_free_wti = cluster->cores_nr;
350
351    // register PIC extension in cluster manager
352    cluster->pic_extend = cluster_ext_ptr;
353
354}  // end soclib_pic_extend_init()
355
356////////////////////////////////////////
357void soclib_pic_bind_irq( lid_t     lid,
358                          chdev_t * src_chdev )
359{
360
361#if CONFIG_DEBUG_HAL_IRQS
362uint32_t cycle = (uint32_t)hal_get_cycles();
363if( CONFIG_DEBUG_HAL_IRQS < cycle )
364printk("\n[DBG] %s : thread %x enter for core[%x,%d] / cycle %d\n",
365__FUNCTION__ , CURRENT_THREAD , local_cxy , lid , cycle );
366#endif
367
368    // get extended & local pointers on PIC chdev descriptor
369    xptr_t     pic_xp  = chdev_dir.pic;
370    cxy_t      pic_cxy = GET_CXY( pic_xp );
371    chdev_t *  pic_ptr = (chdev_t *)GET_PTR( pic_xp );
372
373    // get extended and local pointers on IOPIC  segment base
374    xptr_t     seg_pic_xp  = hal_remote_lwd( XPTR( pic_cxy , &pic_ptr->base ) );
375    cxy_t      seg_pic_cxy = GET_CXY( seg_pic_xp );
376    uint32_t * seg_pic_ptr = (uint32_t *)GET_PTR( seg_pic_xp );
377
378    // get local pointer on XCU segment base
379    uint32_t * seg_xcu_ptr = soclib_pic_xcu_base();
380
381    // get the source chdev functionnal type, channel, and direction
382    uint32_t func    = src_chdev->func;
383    uint32_t channel = src_chdev->channel;
384    bool_t   is_rx   = src_chdev->is_rx;
385
386    if( (func == DEV_FUNC_IOC) || (func == DEV_FUNC_NIC) ||
387        (func == DEV_FUNC_TXT) || (func == DEV_FUNC_IOB) )          // external IRQ => WTI
388    {
389        // get external IRQ index
390        uint32_t  hwi_id;   
391        if     (  func == DEV_FUNC_IOC            ) hwi_id = iopic_input.ioc[channel];
392        else if(  func == DEV_FUNC_TXT  &&  is_rx ) hwi_id = iopic_input.txt_rx[channel];
393        else if(  func == DEV_FUNC_TXT  && !is_rx ) hwi_id = iopic_input.txt_tx[channel];
394        else if( (func == DEV_FUNC_NIC) &&  is_rx ) hwi_id = iopic_input.nic_rx[channel];
395        else if( (func == DEV_FUNC_NIC) && !is_rx ) hwi_id = iopic_input.nic_tx[channel];
396        else if(  func == DEV_FUNC_IOB            ) hwi_id = iopic_input.iob;
397        else      assert( false , __FUNCTION__ , "illegal device functionnal type\n");
398
399        // get a WTI mailbox from local XCU descriptor 
400        uint32_t wti_id = soclib_pic_wti_alloc();
401
402        // register IRQ type and index in chdev
403        src_chdev->irq_type = SOCLIB_TYPE_WTI;
404        src_chdev->irq_id   = wti_id;
405
406        // compute extended pointer on WTI mailbox in local XCU
407        xptr_t wti_xp = XPTR( local_cxy , &seg_xcu_ptr[(XCU_WTI_REG << 5) | wti_id] );
408
409            // set the IOPIC_ADDRESS and IOPIC_EXTEND registers in IOPIC
410        uint32_t lsb_wdata = (uint32_t)wti_xp;
411        uint32_t msb_wdata = (uint32_t)(wti_xp >> 32);
412        xptr_t   lsb_xp = XPTR( seg_pic_cxy , seg_pic_ptr+hwi_id*IOPIC_SPAN+IOPIC_ADDRESS );
413        xptr_t   msb_xp = XPTR( seg_pic_cxy , seg_pic_ptr+hwi_id*IOPIC_SPAN+IOPIC_EXTEND );
414        hal_remote_sw( lsb_xp , lsb_wdata );
415        hal_remote_sw( msb_xp , msb_wdata );
416
417        // enable IRQ in IOPIC
418        hal_remote_sw( XPTR( seg_pic_cxy , seg_pic_ptr+hwi_id*IOPIC_SPAN+IOPIC_MASK ), 1 );
419
420        // update the WTI interrupt vector for core[lid]
421        core_t * core = &LOCAL_CLUSTER->core_tbl[lid];
422        ((soclib_pic_core_t *)core->pic_extend)->wti_vector[wti_id] = src_chdev;
423
424#if CONFIG_DEBUG_HAL_IRQS
425if( CONFIG_DEBUG_HAL_IRQS < cycle )
426printk("\n[DBG] %s : %s / channel = %d / rx = %d / hwi_id = %d / wti_id = %d / cluster = %x\n",
427__FUNCTION__ , chdev_func_str( func ) , channel , is_rx , hwi_id , wti_id , local_cxy );
428#endif
429
430    }
431    else if( (func == DEV_FUNC_DMA) || (func == DEV_FUNC_MMC) )   // internal IRQ => HWI
432    {
433        // get internal IRQ index
434        uint32_t hwi_id;
435        if( func == DEV_FUNC_DMA ) hwi_id = lapic_input.dma[channel];
436        else                       hwi_id = lapic_input.mmc;
437
438        // register IRQ type and index in chdev
439        src_chdev->irq_type = SOCLIB_TYPE_HWI;
440        src_chdev->irq_id   = hwi_id;
441
442        // update the HWI interrupt vector for core[lid]
443        core_t * core = &LOCAL_CLUSTER->core_tbl[lid];
444        ((soclib_pic_core_t *)core->pic_extend)->wti_vector[hwi_id] = src_chdev;
445
446#if CONFIG_DEBUG_HAL_IRQS
447if( CONFIG_DEBUG_HAL_IRQS < cycle )
448printk("\n[DBG] %s : %s / channel = %d / hwi_id = %d / cluster = %x\n",
449__FUNCTION__ , chdev_func_str( func ) , channel , hwi_id , local_cxy );
450#endif
451
452    }
453    else
454    {
455        assert( false , __FUNCTION__ , "illegal device functionnal type\n" );
456    } 
457}  // end soclib_pic_bind_irq();
458
459///////////////////////////////////////
460void soclib_pic_enable_irq( lid_t  lid,
461                            xptr_t src_chdev_xp )
462{
463    // get cluster and local pointer on remote src_chdev
464    cxy_t     src_chdev_cxy = GET_CXY( src_chdev_xp );
465    chdev_t * src_chdev_ptr = (chdev_t *)GET_PTR( src_chdev_xp );
466
467    // get local pointer on remote XCU segment base
468    uint32_t * seg_xcu_ptr = soclib_pic_remote_xcu_base( src_chdev_cxy );
469
470    // get the source chdev IRQ type and index
471    uint32_t irq_type = hal_remote_lw( XPTR( src_chdev_cxy , &src_chdev_ptr->irq_type ) );
472    uint32_t irq_id   = hal_remote_lw( XPTR( src_chdev_cxy , &src_chdev_ptr->irq_id ) );
473
474    if( irq_type == SOCLIB_TYPE_HWI )
475    {
476        // enable this HWI in remote XCU controller
477        // in TSAR : XCU output [4*lid] is connected to core [lid]
478        hal_remote_sw( XPTR( src_chdev_cxy , 
479                       &seg_xcu_ptr[ (XCU_MSK_HWI_ENABLE << 5) | (lid<<4) ] ) , (1 << irq_id) );
480    }
481    else if( irq_type == SOCLIB_TYPE_WTI )
482    {
483        // enable this WTI in remote XCU controller
484        // in TSAR : XCU output [4*lid] is connected to core [lid]
485        hal_remote_sw( XPTR( src_chdev_cxy , 
486                       &seg_xcu_ptr[ (XCU_MSK_WTI_ENABLE << 5) | (lid<<4) ] ) , (1 << irq_id) );
487    }
488    else
489    {
490        assert( false , __FUNCTION__ , "illegal IRQ type\n" );
491    }
492} // end soclib_pic_enable_irq()
493
494////////////////////////////////////////
495void soclib_pic_disable_irq( lid_t  lid,
496                             xptr_t src_chdev_xp )
497{
498    // get cluster and local pointer on remote src_chdev
499    cxy_t     src_chdev_cxy = GET_CXY( src_chdev_xp );
500    chdev_t * src_chdev_ptr = (chdev_t *)GET_PTR( src_chdev_xp );
501
502    // get local pointer on remote XCU segment base
503    uint32_t * seg_xcu_ptr = soclib_pic_remote_xcu_base( src_chdev_cxy );
504
505    // get the source chdev IRQ type and index
506    uint32_t irq_type = hal_remote_lw( XPTR( src_chdev_cxy , &src_chdev_ptr->irq_type ) );
507    uint32_t irq_id   = hal_remote_lw( XPTR( src_chdev_cxy , &src_chdev_ptr->irq_id ) );
508
509    if( irq_type == SOCLIB_TYPE_HWI )
510    {
511        // enable this HWI in remote XCU controller
512        // in TSAR : XCU output [4*lid] is connected to core [lid]
513        hal_remote_sw( XPTR( src_chdev_cxy , 
514                       &seg_xcu_ptr[(XCU_MSK_HWI_DISABLE << 5) | (lid<<2) ] ) , (1 << irq_id) );
515    }
516    else if( irq_type == SOCLIB_TYPE_WTI )
517    {
518        // enable this WTI in remote XCU controller
519        // in TSAR : XCU output [4*lid] is connected to core [lid]
520        hal_remote_sw( XPTR( src_chdev_cxy , 
521                       &seg_xcu_ptr[(XCU_MSK_WTI_DISABLE << 5) | (lid<<4) ] ) , (1 << irq_id) );
522    }
523    else
524    {
525        assert( false , __FUNCTION__ , "illegal IRQ type\n" );
526    }
527} // end soclib_pic_enable_irq()
528
529///////////////////////////////////////////////
530void soclib_pic_enable_timer( uint32_t period )
531{
532    // calling core local index
533    lid_t  lid = CURRENT_CORE->lid;
534
535    // get XCU segment base
536    uint32_t * base = soclib_pic_xcu_base();
537
538    // set period value in XCU (in cycles)
539    uint32_t cycles = period * SOCLIB_CYCLES_PER_MS;
540    base[(XCU_PTI_PER << 5) | lid] = cycles;
541
542    // enable PTI in local XCU controller
543    // In TSAR : XCU output [4*lid] is connected to core [lid]
544    base[ (XCU_MSK_PTI_ENABLE << 5) | (lid<<2) ] = 1 << lid;
545}
546
547////////////////////////////
548void soclib_pic_enable_ipi()
549{
550    // calling core local index
551    lid_t  lid = CURRENT_CORE->lid;
552
553    // get XCU segment base
554    uint32_t * base = soclib_pic_xcu_base();
555
556    // enable WTI in local XCU controller
557    // In TSAR : XCU output [4*lid] is connected to core [lid]
558    base[ (XCU_MSK_WTI_ENABLE << 5) | (lid<<2) ] = 1 << lid;
559}
560
561///////////////////////////////////////
562void soclib_pic_send_ipi( cxy_t    cxy,
563                          lid_t    lid )
564{
565    // get pointer on local XCU segment base
566    uint32_t * base = soclib_pic_xcu_base();
567
568    // write to WTI mailbox[cxy][lid]
569    hal_remote_sw( XPTR( cxy , &base[(XCU_WTI_REG << 5) | lid ] ) , 0 );
570}
571
572/////////////////////////
573void soclib_pic_ack_ipi()
574{
575    // get calling core local index
576    lid_t      lid  = CURRENT_THREAD->core->lid;
577
578    // get pointer on local XCU segment base
579    uint32_t * base = soclib_pic_xcu_base();
580
581    // acknowlege IPI
582    uint32_t   ack  = base[ (XCU_WTI_REG << 5) | lid ];
583
584    // we must make a fake use for ack value to avoid a warning
585    if( (ack + 1) == 0 ) asm volatile( "nop" );
586}
587   
588
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