[45] | 1 | /* |
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[82] | 2 | * hal_apic.c - Advanced Programmable Interrupt Controller |
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[45] | 3 | * |
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| 4 | * Copyright (c) 2017 Maxime Villard |
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| 5 | * |
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| 6 | * This file is part of ALMOS-MKH. |
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| 7 | * |
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| 8 | * ALMOS-MKH is free software; you can redistribute it and/or modify it |
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| 9 | * under the terms of the GNU General Public License as published by |
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| 10 | * the Free Software Foundation; version 2.0 of the License. |
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| 11 | * |
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| 12 | * ALMOS-MKH is distributed in the hope that it will be useful, but |
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| 13 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 15 | * General Public License for more details. |
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| 16 | * |
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| 17 | * You should have received a copy of the GNU General Public License |
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| 18 | * along with ALMOS-MKH.; if not, write to the Free Software Foundation, |
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| 19 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 20 | */ |
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| 21 | |
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| 22 | #include <hal_types.h> |
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[83] | 23 | #include <hal_boot.h> |
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[82] | 24 | #include <hal_register.h> |
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[45] | 25 | #include <hal_segmentation.h> |
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[82] | 26 | #include <hal_apic.h> |
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[45] | 27 | #include <hal_internal.h> |
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| 28 | |
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| 29 | #include <memcpy.h> |
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| 30 | #include <thread.h> |
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| 31 | #include <string.h> |
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| 32 | #include <process.h> |
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| 33 | #include <printk.h> |
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| 34 | #include <vmm.h> |
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| 35 | #include <core.h> |
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| 36 | #include <cluster.h> |
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| 37 | |
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[82] | 38 | /* -------------------------------------------------------------------------- */ |
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| 39 | |
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| 40 | #define PIC1_CMD 0x0020 |
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| 41 | #define PIC1_DATA 0x0021 |
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| 42 | #define PIC2_CMD 0x00a0 |
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| 43 | #define PIC2_DATA 0x00a1 |
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| 44 | |
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| 45 | static void hal_pic_init() |
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| 46 | { |
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| 47 | /* |
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| 48 | * Disable the PIC (8259A). We are going to use IOAPIC instead. |
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| 49 | */ |
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| 50 | out8(PIC1_DATA, 0xff); |
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| 51 | out8(PIC2_DATA, 0xff); |
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| 52 | } |
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| 53 | |
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| 54 | /* -------------------------------------------------------------------------- */ |
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| 55 | |
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[117] | 56 | uint64_t pit_ticks_base __in_kdata = 0; |
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| 57 | |
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| 58 | #define PIT_FREQUENCY 1193182 |
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| 59 | #define HZ 100 /* 1/HZ = 10ms */ |
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| 60 | |
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| 61 | #define PIT_TIMER0 0x40 |
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| 62 | |
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| 63 | #define PIT_CMD 0x43 |
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| 64 | # define CMD_BINARY 0x00 /* Use Binary counter values */ |
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| 65 | # define CMD_BCD 0x01 /* Use Binary Coded Decimal counter values */ |
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| 66 | # define CMD_MODE0 0x00 /* Interrupt on Terminal Count */ |
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| 67 | # define CMD_MODE1 0x02 /* Hardware Retriggerable One-Shot */ |
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| 68 | # define CMD_MODE2 0x04 /* Rate Generator */ |
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| 69 | # define CMD_MODE3 0x06 /* Square Wave */ |
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| 70 | # define CMD_MODE4 0x08 /* Software Trigerred Strobe */ |
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| 71 | # define CMD_MODE5 0x0a /* Hardware Trigerred Strobe */ |
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| 72 | # define CMD_LATCH 0x00 /* latch counter for reading */ |
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| 73 | # define CMD_LSB 0x10 /* LSB, 8 bits */ |
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| 74 | # define CMD_MSB 0x20 /* MSB, 8 bits */ |
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| 75 | # define CMD_16BIT 0x30 /* LSB and MSB, 16 bits */ |
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| 76 | # define CMD_COUNTER0 0x00 |
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| 77 | # define CMD_COUNTER1 0x40 |
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| 78 | # define CMD_COUNTER2 0x80 |
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| 79 | # define CMD_READBACK 0xc0 |
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| 80 | |
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| 81 | void hal_pit_init() |
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| 82 | { |
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| 83 | /* Initialize PIT clock 0 to the maximum counter value, 65535. */ |
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| 84 | out8(PIT_CMD, CMD_COUNTER0|CMD_MODE2|CMD_16BIT); |
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| 85 | out8(PIT_TIMER0, 0xFF); |
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| 86 | out8(PIT_TIMER0, 0xFF); |
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| 87 | } |
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| 88 | |
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| 89 | uint64_t |
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| 90 | hal_pit_timer_read() |
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| 91 | { |
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| 92 | static uint16_t last; |
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| 93 | |
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| 94 | uint8_t lo, hi; |
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| 95 | uint16_t ctr; |
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| 96 | uint64_t ticks; |
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| 97 | |
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| 98 | /* Read the current timer counter. */ |
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| 99 | out8(PIT_CMD, CMD_COUNTER0|CMD_LATCH); |
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| 100 | lo = in8(PIT_TIMER0); |
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| 101 | hi = in8(PIT_TIMER0); |
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| 102 | ctr = (hi << 8) | lo; |
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| 103 | |
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| 104 | /* If the counter has wrapped, assume we're into the next tick. */ |
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| 105 | if (ctr > last) |
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| 106 | pit_ticks_base += 0xFFFF; |
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| 107 | last = ctr; |
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| 108 | |
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| 109 | ticks = pit_ticks_base + (0xFFFF - ctr); |
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| 110 | |
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| 111 | return ticks; |
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| 112 | } |
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| 113 | |
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| 114 | /* -------------------------------------------------------------------------- */ |
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| 115 | |
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[89] | 116 | paddr_t ioapic_pa __in_kdata = 0; |
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| 117 | vaddr_t ioapic_va __in_kdata = 0; |
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| 118 | |
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| 119 | #define IRQ_TIMER 0x00 |
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| 120 | #define IRQ_KEYBOARD 0x01 |
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| 121 | #define IRQ_COM2 0x03 |
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| 122 | #define IRQ_COM1 0x04 |
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| 123 | #define IRQ_FLOPPY 0x06 |
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| 124 | #define IRQ_ATA0 0x0e |
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| 125 | #define IRQ_ATA1 0x0f |
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| 126 | |
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| 127 | #define IOREGSEL 0x00 |
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| 128 | #define IOWIN 0x10 |
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| 129 | |
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| 130 | #define IOAPICID 0x00 |
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| 131 | #define IOAPICVER 0x01 |
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| 132 | #define IOAPICARB 0x02 |
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| 133 | #define IOREDTBL 0x10 |
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| 134 | |
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| 135 | #define IOENTRY_DISABLE 0x10000 |
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| 136 | |
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| 137 | void hal_ioapic_write(uint8_t reg, uint32_t val) |
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| 138 | { |
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| 139 | *((volatile uint32_t *)((uint8_t *)ioapic_va + IOREGSEL)) = reg; |
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| 140 | *((volatile uint32_t *)((uint8_t *)ioapic_va + IOWIN)) = val; |
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| 141 | } |
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| 142 | |
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| 143 | uint32_t hal_ioapic_read(uint8_t reg) |
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| 144 | { |
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| 145 | *((volatile uint32_t *)((uint8_t *)ioapic_va + IOREGSEL)) = reg; |
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| 146 | return *((volatile uint32_t *)((uint8_t *)ioapic_va + IOWIN)); |
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| 147 | } |
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| 148 | |
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| 149 | void hal_ioapic_set_entry(uint8_t index, uint64_t data) |
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| 150 | { |
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| 151 | hal_ioapic_write(IOREDTBL + index * 2, (uint32_t)(data & 0xFFFFFFFF)); |
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| 152 | hal_ioapic_write(IOREDTBL + index * 2 + 1, (uint32_t)(data >> 32)); |
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| 153 | } |
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| 154 | |
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| 155 | static void hal_ioapic_init() |
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| 156 | { |
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| 157 | size_t i, pins; |
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| 158 | uint32_t ver; |
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| 159 | |
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| 160 | ioapic_va = hal_gpt_bootstrap_valloc(1); // XXX: should be shared |
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| 161 | |
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| 162 | hal_gpt_enter(ioapic_va, ioapic_pa, PG_V|PG_KW|PG_NX|PG_N); |
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| 163 | |
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| 164 | ver = hal_ioapic_read(IOAPICVER); |
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| 165 | pins = ((ver >> 16) & 0xFF) + 1; |
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| 166 | |
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| 167 | /* Explicitly disable (mask) each vector */ |
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| 168 | for (i = 0; i < pins; i++) { |
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| 169 | hal_ioapic_set_entry(i, IOENTRY_DISABLE); |
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| 170 | } |
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| 171 | |
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| 172 | /* Now, enable the keyboard */ |
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| 173 | hal_ioapic_set_entry(IRQ_KEYBOARD, IOAPIC_KEYBOARD_VECTOR); |
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| 174 | } |
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| 175 | |
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| 176 | /* -------------------------------------------------------------------------- */ |
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| 177 | |
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[45] | 178 | paddr_t lapic_pa __in_kdata = 0; |
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| 179 | vaddr_t lapic_va __in_kdata = 0; |
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| 180 | |
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[46] | 181 | void hal_lapic_write(uint32_t reg, uint32_t val) |
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[45] | 182 | { |
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[82] | 183 | *((volatile uint32_t *)((uint8_t *)lapic_va + reg)) = val; |
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[45] | 184 | } |
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| 185 | |
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[46] | 186 | uint32_t hal_lapic_read(uint32_t reg) |
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[45] | 187 | { |
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[82] | 188 | return *((volatile uint32_t *)((uint8_t *)lapic_va + reg)); |
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[45] | 189 | } |
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| 190 | |
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[46] | 191 | uint32_t hal_lapic_gid() |
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[45] | 192 | { |
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[46] | 193 | return hal_lapic_read(LAPIC_ID) >> LAPIC_ID_SHIFT; |
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| 194 | } |
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[45] | 195 | |
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[82] | 196 | /* |
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[117] | 197 | * Use the PIT, which has a standard clock frequency, to determine the CPU's |
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| 198 | * exact bus frequency. |
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| 199 | */ |
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| 200 | static void hal_lapic_calibrate() |
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| 201 | { |
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| 202 | uint64_t pittick, lapictick0, lapictick1; |
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| 203 | uint32_t lapicticks, lapicstart; |
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| 204 | |
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| 205 | /* Initialize the LAPIC timer to the maximum value */ |
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| 206 | hal_lapic_write(LAPIC_ICR_TIMER, 0xFFFFFFFF); |
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| 207 | |
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| 208 | pittick = hal_pit_timer_read() + 1; |
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| 209 | while (hal_pit_timer_read() < pittick) { |
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| 210 | /* Wait until start of a PIT tick */ |
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| 211 | } |
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| 212 | |
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| 213 | /* Read base count from LAPIC */ |
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| 214 | lapictick0 = hal_lapic_read(LAPIC_CCR_TIMER); |
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| 215 | |
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| 216 | while (hal_pit_timer_read() < pittick + (PIT_FREQUENCY + HZ/2) / HZ) { |
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| 217 | /* Wait 1/HZ sec = 10ms */ |
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| 218 | } |
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| 219 | |
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| 220 | /* Read final count from LAPIC */ |
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| 221 | lapictick1 = hal_lapic_read(LAPIC_CCR_TIMER); |
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| 222 | |
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| 223 | /* Total number of LAPIC ticks per 1/HZ tick */ |
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| 224 | lapicticks = (lapictick1 - lapictick0); |
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| 225 | |
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| 226 | /* Finally, calibrate the timer, an interrupt each 1s. */ |
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| 227 | lapicstart = - (lapicticks * 100); |
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| 228 | hal_lapic_write(LAPIC_ICR_TIMER, lapicstart); |
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| 229 | } |
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| 230 | |
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| 231 | /* |
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[82] | 232 | * We have 8 interrupt sources: |
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| 233 | * - Spurious |
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| 234 | * - APIC Timer (TMR) |
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| 235 | * - Local Interrupt 0 (LINT0) |
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| 236 | * - Local Interrupt 1 (LINT1) |
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| 237 | * - Performance Monitor Counters (PMC) |
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| 238 | * - Thermal Sensors (THM) |
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| 239 | * - APIC internal error (ERR) |
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| 240 | * - Extended (Implementation dependent) |
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| 241 | */ |
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| 242 | static void hal_lapic_init() |
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[46] | 243 | { |
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[45] | 244 | lapic_va = hal_gpt_bootstrap_valloc(1); // XXX: should be shared |
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| 245 | |
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[82] | 246 | if ((rdmsr(MSR_APICBASE) & APICBASE_PHYSADDR) != lapic_pa) { |
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| 247 | x86_panic("APICBASE and ACPI don't match!\n"); |
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| 248 | } |
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| 249 | wrmsr(MSR_APICBASE, lapic_pa | APICBASE_EN); |
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| 250 | |
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[83] | 251 | hal_gpt_enter(lapic_va, lapic_pa, PG_V|PG_KW|PG_NX|PG_N); |
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[45] | 252 | |
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[46] | 253 | hal_lapic_write(LAPIC_TPR, 0); |
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[82] | 254 | hal_lapic_write(LAPIC_EOI, 0); |
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[46] | 255 | hal_lapic_write(LAPIC_SVR, LAPIC_SVR_ENABLE|LAPIC_SPURIOUS_VECTOR); |
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[82] | 256 | |
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| 257 | /* Explicitly disable (mask) each vector */ |
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| 258 | hal_lapic_write(LAPIC_LVT_TMR, LAPIC_TMR_M); |
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| 259 | hal_lapic_write(LAPIC_LVT_LINT0, LAPIC_LINT_M); |
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| 260 | hal_lapic_write(LAPIC_LVT_LINT1, LAPIC_LINT_M); |
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| 261 | hal_lapic_write(LAPIC_LVT_PMC, LAPIC_PMC_M); |
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| 262 | hal_lapic_write(LAPIC_LVT_THM, LAPIC_THM_M); |
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| 263 | hal_lapic_write(LAPIC_LVT_ERR, LAPIC_ERR_M); |
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[86] | 264 | |
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| 265 | /* Now, enable the timer in repeated mode. */ |
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| 266 | hal_lapic_write(LAPIC_LVT_TMR, LAPIC_TMR_TM|LAPIC_TMR_M); |
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| 267 | hal_lapic_write(LAPIC_DCR_TIMER, LAPIC_DCRT_DIV1); |
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[117] | 268 | hal_lapic_calibrate(); |
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[86] | 269 | hal_lapic_write(LAPIC_LVT_TMR, LAPIC_TMR_TM|LAPIC_TIMER_VECTOR); |
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[45] | 270 | } |
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| 271 | |
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[82] | 272 | /* -------------------------------------------------------------------------- */ |
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| 273 | |
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| 274 | void hal_apic_init() |
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| 275 | { |
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| 276 | /* Disable the PIC */ |
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| 277 | hal_pic_init(); |
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| 278 | |
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| 279 | /* Enable the LAPIC */ |
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| 280 | hal_lapic_init(); |
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[89] | 281 | |
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| 282 | /* Enable the IOAPIC */ |
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| 283 | hal_ioapic_init(); |
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[82] | 284 | } |
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| 285 | |
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