source: trunk/hal/x86_64/core/hal_apic.c @ 83

Last change on this file since 83 was 83, checked in by max@…, 5 years ago

we want to have the LAPIC non-cacheable

File size: 3.1 KB
Line 
1/*
2 * hal_apic.c - Advanced Programmable Interrupt Controller
3 *
4 * Copyright (c) 2017 Maxime Villard
5 *
6 * This file is part of ALMOS-MKH.
7 *
8 * ALMOS-MKH is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2.0 of the License.
11 *
12 * ALMOS-MKH is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with ALMOS-MKH.; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22#include <hal_types.h>
23#include <hal_boot.h>
24#include <hal_register.h>
25#include <hal_segmentation.h>
26#include <hal_apic.h>
27#include <hal_internal.h>
28
29#include <memcpy.h>
30#include <thread.h>
31#include <string.h>
32#include <process.h>
33#include <printk.h>
34#include <vmm.h>
35#include <core.h>
36#include <cluster.h>
37
38/* -------------------------------------------------------------------------- */
39
40#define PIC1_CMD        0x0020
41#define PIC1_DATA       0x0021
42#define PIC2_CMD        0x00a0
43#define PIC2_DATA       0x00a1
44
45static void hal_pic_init()
46{
47        /*
48         * Disable the PIC (8259A). We are going to use IOAPIC instead.
49         */
50        out8(PIC1_DATA, 0xff);
51        out8(PIC2_DATA, 0xff);
52}
53
54/* -------------------------------------------------------------------------- */
55
56paddr_t lapic_pa __in_kdata = 0;
57vaddr_t lapic_va __in_kdata = 0;
58
59void hal_lapic_write(uint32_t reg, uint32_t val)
60{
61        *((volatile uint32_t *)((uint8_t *)lapic_va + reg)) = val;
62}
63
64uint32_t hal_lapic_read(uint32_t reg)
65{
66        return *((volatile uint32_t *)((uint8_t *)lapic_va + reg));
67}
68
69uint32_t hal_lapic_gid()
70{
71        return hal_lapic_read(LAPIC_ID) >> LAPIC_ID_SHIFT;
72}
73
74/*
75 * We have 8 interrupt sources:
76 *  - Spurious
77 *  - APIC Timer (TMR)
78 *  - Local Interrupt 0 (LINT0)
79 *  - Local Interrupt 1 (LINT1)
80 *  - Performance Monitor Counters (PMC)
81 *  - Thermal Sensors (THM)
82 *  - APIC internal error (ERR)
83 *  - Extended (Implementation dependent)
84 */
85static void hal_lapic_init()
86{
87        lapic_va = hal_gpt_bootstrap_valloc(1); // XXX: should be shared
88
89        if ((rdmsr(MSR_APICBASE) & APICBASE_PHYSADDR) != lapic_pa) {
90                x86_panic("APICBASE and ACPI don't match!\n");
91        }
92        wrmsr(MSR_APICBASE, lapic_pa | APICBASE_EN);
93
94        hal_gpt_enter(lapic_va, lapic_pa, PG_V|PG_KW|PG_NX|PG_N);
95
96        hal_lapic_write(LAPIC_TPR, 0);
97        hal_lapic_write(LAPIC_EOI, 0);
98        hal_lapic_write(LAPIC_SVR, LAPIC_SVR_ENABLE|LAPIC_SPURIOUS_VECTOR);
99
100        /* Explicitly disable (mask) each vector */
101        hal_lapic_write(LAPIC_LVT_TMR, LAPIC_TMR_M);
102        hal_lapic_write(LAPIC_LVT_LINT0, LAPIC_LINT_M);
103        hal_lapic_write(LAPIC_LVT_LINT1, LAPIC_LINT_M);
104        hal_lapic_write(LAPIC_LVT_PMC, LAPIC_PMC_M);
105        hal_lapic_write(LAPIC_LVT_THM, LAPIC_THM_M);
106        hal_lapic_write(LAPIC_LVT_ERR, LAPIC_ERR_M);
107}
108
109/* -------------------------------------------------------------------------- */
110
111void hal_apic_init()
112{
113        /* Disable the PIC */
114        hal_pic_init();
115
116        /* Enable the LAPIC */
117        hal_lapic_init();
118}
119
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