source: trunk/hal/x86_64/core/hal_apic.c @ 89

Last change on this file since 89 was 89, checked in by max@…, 5 years ago

Parse the IOAPIC structure in ACPI, map the IOAPIC, and enable
the keyboard interrupt. Its queue is not flushed yet.

File size: 4.9 KB
Line 
1/*
2 * hal_apic.c - Advanced Programmable Interrupt Controller
3 *
4 * Copyright (c) 2017 Maxime Villard
5 *
6 * This file is part of ALMOS-MKH.
7 *
8 * ALMOS-MKH is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2.0 of the License.
11 *
12 * ALMOS-MKH is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with ALMOS-MKH.; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22#include <hal_types.h>
23#include <hal_boot.h>
24#include <hal_register.h>
25#include <hal_segmentation.h>
26#include <hal_apic.h>
27#include <hal_internal.h>
28
29#include <memcpy.h>
30#include <thread.h>
31#include <string.h>
32#include <process.h>
33#include <printk.h>
34#include <vmm.h>
35#include <core.h>
36#include <cluster.h>
37
38/* -------------------------------------------------------------------------- */
39
40#define PIC1_CMD        0x0020
41#define PIC1_DATA       0x0021
42#define PIC2_CMD        0x00a0
43#define PIC2_DATA       0x00a1
44
45static void hal_pic_init()
46{
47        /*
48         * Disable the PIC (8259A). We are going to use IOAPIC instead.
49         */
50        out8(PIC1_DATA, 0xff);
51        out8(PIC2_DATA, 0xff);
52}
53
54/* -------------------------------------------------------------------------- */
55
56paddr_t ioapic_pa __in_kdata = 0;
57vaddr_t ioapic_va __in_kdata = 0;
58
59#define IRQ_TIMER       0x00
60#define IRQ_KEYBOARD    0x01
61#define IRQ_COM2        0x03
62#define IRQ_COM1        0x04
63#define IRQ_FLOPPY      0x06
64#define IRQ_ATA0        0x0e
65#define IRQ_ATA1        0x0f
66
67#define IOREGSEL        0x00
68#define IOWIN   0x10
69
70#define IOAPICID        0x00
71#define IOAPICVER       0x01
72#define IOAPICARB       0x02
73#define IOREDTBL        0x10
74
75#define IOENTRY_DISABLE 0x10000
76
77void hal_ioapic_write(uint8_t reg, uint32_t val)
78{
79        *((volatile uint32_t *)((uint8_t *)ioapic_va + IOREGSEL)) = reg;
80        *((volatile uint32_t *)((uint8_t *)ioapic_va + IOWIN)) = val;
81}
82
83uint32_t hal_ioapic_read(uint8_t reg)
84{
85        *((volatile uint32_t *)((uint8_t *)ioapic_va + IOREGSEL)) = reg;
86        return *((volatile uint32_t *)((uint8_t *)ioapic_va + IOWIN));
87}
88
89void hal_ioapic_set_entry(uint8_t index, uint64_t data)
90{
91        hal_ioapic_write(IOREDTBL + index * 2, (uint32_t)(data & 0xFFFFFFFF));
92        hal_ioapic_write(IOREDTBL + index * 2 + 1, (uint32_t)(data >> 32));
93}
94
95static void hal_ioapic_init()
96{
97        size_t i, pins;
98        uint32_t ver;
99
100        ioapic_va = hal_gpt_bootstrap_valloc(1); // XXX: should be shared
101
102        hal_gpt_enter(ioapic_va, ioapic_pa, PG_V|PG_KW|PG_NX|PG_N);
103
104        ver = hal_ioapic_read(IOAPICVER);
105        pins = ((ver >> 16) & 0xFF) + 1;
106
107        /* Explicitly disable (mask) each vector */
108        for (i = 0; i < pins; i++) {
109                hal_ioapic_set_entry(i, IOENTRY_DISABLE);
110        }
111
112        /* Now, enable the keyboard */
113        hal_ioapic_set_entry(IRQ_KEYBOARD, IOAPIC_KEYBOARD_VECTOR);
114}
115
116/* -------------------------------------------------------------------------- */
117
118paddr_t lapic_pa __in_kdata = 0;
119vaddr_t lapic_va __in_kdata = 0;
120
121void hal_lapic_write(uint32_t reg, uint32_t val)
122{
123        *((volatile uint32_t *)((uint8_t *)lapic_va + reg)) = val;
124}
125
126uint32_t hal_lapic_read(uint32_t reg)
127{
128        return *((volatile uint32_t *)((uint8_t *)lapic_va + reg));
129}
130
131uint32_t hal_lapic_gid()
132{
133        return hal_lapic_read(LAPIC_ID) >> LAPIC_ID_SHIFT;
134}
135
136/*
137 * We have 8 interrupt sources:
138 *  - Spurious
139 *  - APIC Timer (TMR)
140 *  - Local Interrupt 0 (LINT0)
141 *  - Local Interrupt 1 (LINT1)
142 *  - Performance Monitor Counters (PMC)
143 *  - Thermal Sensors (THM)
144 *  - APIC internal error (ERR)
145 *  - Extended (Implementation dependent)
146 */
147static void hal_lapic_init()
148{
149        lapic_va = hal_gpt_bootstrap_valloc(1); // XXX: should be shared
150
151        if ((rdmsr(MSR_APICBASE) & APICBASE_PHYSADDR) != lapic_pa) {
152                x86_panic("APICBASE and ACPI don't match!\n");
153        }
154        wrmsr(MSR_APICBASE, lapic_pa | APICBASE_EN);
155
156        hal_gpt_enter(lapic_va, lapic_pa, PG_V|PG_KW|PG_NX|PG_N);
157
158        hal_lapic_write(LAPIC_TPR, 0);
159        hal_lapic_write(LAPIC_EOI, 0);
160        hal_lapic_write(LAPIC_SVR, LAPIC_SVR_ENABLE|LAPIC_SPURIOUS_VECTOR);
161
162        /* Explicitly disable (mask) each vector */
163        hal_lapic_write(LAPIC_LVT_TMR, LAPIC_TMR_M);
164        hal_lapic_write(LAPIC_LVT_LINT0, LAPIC_LINT_M);
165        hal_lapic_write(LAPIC_LVT_LINT1, LAPIC_LINT_M);
166        hal_lapic_write(LAPIC_LVT_PMC, LAPIC_PMC_M);
167        hal_lapic_write(LAPIC_LVT_THM, LAPIC_THM_M);
168        hal_lapic_write(LAPIC_LVT_ERR, LAPIC_ERR_M);
169
170        /* Now, enable the timer in repeated mode. */
171        hal_lapic_write(LAPIC_LVT_TMR, LAPIC_TMR_TM|LAPIC_TMR_M);
172        hal_lapic_write(LAPIC_DCR_TIMER, LAPIC_DCRT_DIV1);
173        hal_lapic_write(LAPIC_ICR_TIMER, 1000000000); // XXX calibrate
174        hal_lapic_write(LAPIC_LVT_TMR, LAPIC_TMR_TM|LAPIC_TIMER_VECTOR);
175}
176
177/* -------------------------------------------------------------------------- */
178
179void hal_apic_init()
180{
181        /* Disable the PIC */
182        hal_pic_init();
183
184        /* Enable the LAPIC */
185        hal_lapic_init();
186
187        /* Enable the IOAPIC */
188        hal_ioapic_init();
189}
190
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