source: trunk/hal/x86_64/core/hal_boot.h @ 368

Last change on this file since 368 was 272, checked in by max@…, 4 years ago

Use local_cxy for GET_PTR, instead of the triple map. This fixes a number
of inconsistencies.

File size: 5.2 KB
Line 
1/*
2 * hal_boot.h - General values used by the boot procedure
3 *
4 * Copyright (c) 2017 Maxime Villard
5 *
6 * This file is part of ALMOS-MKH.
7 *
8 * ALMOS-MKH is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2.0 of the License.
11 *
12 * ALMOS-MKH is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with ALMOS-MKH; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22#define PAGE_SIZE       4096
23#define PGOFSET         (PAGE_SIZE-1)
24#define PGSHIFT         12
25
26#define KERNBASE        0xfffff00000000000
27#define KERNBASE_HI     0xfffff000
28#define KERNBASE_LO     0x00000000
29
30#define KERNTEXTOFF     0xfffff00000200000
31#define KERNTEXTOFF_HI  0xfffff000
32#define KERNTEXTOFF_LO  0x00200000
33
34/* -------------------------------------------------------------------------- */
35
36#define ASM_ALIGN_TEXT  .align 16
37#define ASM_ENTRY(x) \
38        .text; ASM_ALIGN_TEXT; .globl x; .type x,@function; x:
39
40#define LABEL(x) \
41        .globl x; .type x,@function; x:
42
43/* -------------------------------------------------------------------------- */
44
45#define STKPAGES        4
46#define STKSIZE         (PAGE_SIZE * STKPAGES)
47
48#define NKL4_KIMG_ENTRIES       1
49#define NKL3_KIMG_ENTRIES       1
50#define NKL2_KIMG_ENTRIES       32
51
52/* -------------------------------------------------------------------------- */
53
54#define L1_SHIFT        12
55#define L2_SHIFT        21
56#define L3_SHIFT        30
57#define L4_SHIFT        39
58#define NBPD_L1         (1UL << L1_SHIFT) /* # bytes mapped by L1 ent (4K) */
59#define NBPD_L2         (1UL << L2_SHIFT) /* # bytes mapped by L2 ent (2MB) */
60#define NBPD_L3         (1UL << L3_SHIFT) /* # bytes mapped by L3 ent (1G) */
61#define NBPD_L4         (1UL << L4_SHIFT) /* # bytes mapped by L4 ent (512G) */
62
63#define L4_MASK         0x0000ff8000000000
64#define L3_MASK         0x0000007fc0000000
65#define L2_MASK         0x000000003fe00000
66#define L1_MASK         0x00000000001ff000
67
68#define L4_FRAME        L4_MASK
69#define L3_FRAME        (L4_FRAME|L3_MASK)
70#define L2_FRAME        (L3_FRAME|L2_MASK)
71#define L1_FRAME        (L2_FRAME|L1_MASK)
72
73#define PDE_SIZE        8
74
75/* PDE/PTE bits. */
76#define PG_V            0x0000000000000001      /* valid */
77#define PG_RO           0x0000000000000000      /* read-only */
78#define PG_RW           0x0000000000000002      /* read-write */
79#define PG_u            0x0000000000000004      /* user accessible */
80#define PG_PROT         0x0000000000000006
81#define PG_WT           0x0000000000000008      /* write-through */
82#define PG_N            0x0000000000000010      /* non-cacheable */
83#define PG_U            0x0000000000000020      /* used */
84#define PG_M            0x0000000000000040      /* modified */
85#define PG_PAT          0x0000000000000080      /* PAT (on pte) */
86#define PG_PS           0x0000000000000080      /* 2MB page size (on pde) */
87#define PG_G            0x0000000000000100      /* not flushed */
88#define PG_AVAIL1       0x0000000000000200
89#define PG_AVAIL2       0x0000000000000400
90#define PG_AVAIL3       0x0000000000000800
91#define PG_LGPAT        0x0000000000001000      /* PAT on large pages */
92#define PG_FRAME        0x000ffffffffff000
93#define PG_NX           0x8000000000000000
94
95#define PG_2MFRAME      0x000fffffffe00000      /* large (2M) page frame mask */
96#define PG_1GFRAME      0x000fffffc0000000      /* large (1G) page frame mask */
97#define PG_LGFRAME      PG_2MFRAME
98
99/* Short forms of protection codes. */
100#define PG_KR           0x0000000000000000      /* kernel read-only */
101#define PG_KW           0x0000000000000002      /* kernel read-write */
102
103/* -------------------------------------------------------------------------- */
104
105#define IOM_BEGIN       0x0a0000                /* Start of I/O Memory "hole" */
106#define IOM_END         0x100000                /* End of I/O Memory "hole" */
107#define IOM_SIZE        (IOM_END - IOM_BEGIN)
108
109/* -------------------------------------------------------------------------- */
110
111#define VA_SIGN_MASK            0xffff000000000000
112#define VA_SIGN_POS(va)         ((va) & ~VA_SIGN_MASK)
113
114#define pl1_i(VA)       (((VA_SIGN_POS(VA)) & L1_FRAME) >> L1_SHIFT)
115#define pl2_i(VA)       (((VA_SIGN_POS(VA)) & L2_FRAME) >> L2_SHIFT)
116#define pl3_i(VA)       (((VA_SIGN_POS(VA)) & L3_FRAME) >> L3_SHIFT)
117#define pl4_i(VA)       (((VA_SIGN_POS(VA)) & L4_FRAME) >> L4_SHIFT)
118
119#define L4_SLOT_PTE             255
120#define L4_SLOT_KERNBASE        pl4_i(KERNBASE)
121#define L3_SLOT_KERNBASE        (pl3_i(KERNBASE) % 512)
122#define L2_SLOT_KERNBASE        (pl2_i(KERNBASE) % 512)
123
124#define PDIR_SLOT_PTE   L4_SLOT_PTE
125
126#define PTE_BASE        ((pt_entry_t *)(L4_SLOT_PTE * NBPD_L4))
127#define L1_BASE PTE_BASE
128#define L2_BASE ((pt_entry_t *)((char *)L1_BASE + L4_SLOT_PTE * NBPD_L3))
129#define L3_BASE ((pt_entry_t *)((char *)L2_BASE + L4_SLOT_PTE * NBPD_L2))
130#define L4_BASE ((pt_entry_t *)((char *)L3_BASE + L4_SLOT_PTE * NBPD_L1))
131
132#define NPDPG   (PAGE_SIZE / sizeof (pt_entry_t))
133
134/* -------------------------------------------------------------------------- */
135
136#define SMP_TRAMPOLINE_PA       (2 * PAGE_SIZE)
137
138/* -------------------------------------------------------------------------- */
139
140#define KERNEL_VA_SIZE          (NKL2_KIMG_ENTRIES * NBPD_L2)
141#define CLUSTERS_BASE_VA        HAL_VA_BASE
142
143/* These parameters are configurable. */
144#define CLUSTER_VA_SIZE 0x1000000000 /* 64GB */
145#define CLUSTER_PA_SIZE 0x0200000000 /* 8GB */
146
147/* Macros to get the VA ranges for a cluster */
148#define CLUSTER_MIN_VA(n) \
149        (CLUSTERS_BASE_VA + n * CLUSTER_VA_SIZE)
150#define CLUSTER_MAX_VA(n) \
151        (CLUSTER_MIN_VA(n) + CLUSTER_VA_SIZE)
152
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