source: trunk/hal/x86_64/core/hal_init.c @ 167

/*
 * hal_init.c - C initialization procedure for x86.
 *
 * Copyright (c) 2017 Maxime Villard
 *
 * This file is part of ALMOS-MKH.
 *
 * ALMOS-MKH is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2.0 of the License.
 *
 * ALMOS-MKH is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with ALMOS-MKH.; if not, write to the Free Software Foundation,
 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 */

#include <hal_types.h>
#include <hal_boot.h>
#include <hal_multiboot.h>
#include <hal_segmentation.h>
#include <hal_acpi.h>
#include <hal_apic.h>
#include <hal_internal.h>
#include <hal_register.h>

#include <hal_remote.h>
#include <hal_irqmask.h>

#include <memcpy.h>
#include <thread.h>
#include <string.h>
#include <process.h>
#include <printk.h>
#include <vmm.h>
#include <core.h>
#include <cluster.h>
#include <chdev.h>

#include <boot_info.h>

void kernel_init(boot_info_t *info);

static void gdt_create();
static void idt_create();
void cpu_identify();
void cpu_attach();

size_t mytest __in_kdata = 0;

struct multiboot_info mb_info __in_kdata;
char mb_loader_name[PAGE_SIZE] __in_kdata;
uint8_t mb_mmap[PAGE_SIZE] __in_kdata;

/* -------------------------------------------------------------------------- */

static void
dump_memmap()
{
        size_t mmap_length = mb_info.mi_mmap_length;
        uint8_t *mmap_addr = (uint8_t *)&mb_mmap;
        size_t i;

        if (!(mb_info.mi_flags & MULTIBOOT_INFO_HAS_MMAP))
                x86_panic("No mmap");

        i = 0;
        while (i < mmap_length) {
                struct multiboot_mmap *mm;

                mm = (struct multiboot_mmap *)(mmap_addr + i);

                x86_printf("-> [%Z, %Z] %s\n", mm->mm_base_addr,
                    mm->mm_base_addr + mm->mm_length,
                    (mm->mm_type == 1) ? "ram" : "rsv" );

                i += mm->mm_size + 4;
        }
}

/* -------------------------------------------------------------------------- */

static void init_bootinfo_icu(boot_device_t *dev)
{
        extern uint32_t hwi_baseidx;
        extern uint32_t wti_baseidx;
        extern uint32_t pti_baseidx;
        extern size_t ioapic_pins;

        memset(dev, 0, sizeof(boot_device_t));

        dev->base = 0;
        dev->type = (DEV_FUNC_ICU << 16) | IMPL_ICU_XCU;
        dev->channels = 1;

#if NOTYET
        /*
         * Give 20% of the pins to HWI, 80% to WTI.
         */
        dev->param0 = (ioapic_pins * 20) / 100;  /* hwi_nr */
        dev->param1 = ioapic_pins - dev->param0; /* wti_nr */
#else
        dev->param0 = 1; /* hwi_nr */
        dev->param1 = 1; /* wti_nr */
#endif

        /*
         * We always set 1 for pti_nr. On x86, timer interrupts are handled by
         * LAPIC, which is per-cpu and not global. Therefore, we always have one
         * timer for each CPU, and its IRQ number is faked to 0.
         */
        dev->param2 = 1; /* pti_nr */

        dev->param3 = 0;

        /* Set the base idx for the XCU driver */
        hwi_baseidx = 0;
        wti_baseidx = dev->param0;
        pti_baseidx = 0xFFFFFFFF;

#ifdef NOTYET
    uint32_t    irqs;                 /*! number of input IRQs                              */
    boot_irq_t  irq[32];              /*! array of input IRQS (PIC and ICU only)            */
#endif
}

static size_t init_bootinfo_pages_nr()
{
        size_t mmap_length = mb_info.mi_mmap_length;
        uint8_t *mmap_addr = (uint8_t *)&mb_mmap;
        paddr_t maxpa, pa;
        size_t i;

        i = 0;
        maxpa = 0;
        while (i < mmap_length) {
                struct multiboot_mmap *mm;

                mm = (struct multiboot_mmap *)(mmap_addr + i);

                if (mm->mm_type == 1) {
                        pa = mm->mm_base_addr + mm->mm_length;
                        if (pa > maxpa)
                                maxpa = pa;
                }

                i += mm->mm_size + 4;
        }

        return (maxpa / PAGE_SIZE);
}

static size_t init_bootinfo_rsvd(boot_rsvd_t *rsvd)
{
        size_t mmap_length = mb_info.mi_mmap_length;
        uint8_t *mmap_addr = (uint8_t *)&mb_mmap;
        size_t i, rsvd_nr;

        memset(rsvd, 0, sizeof(boot_rsvd_t) * CONFIG_PPM_MAX_RSVD);

        i = 0, rsvd_nr = 0;
        while (i < mmap_length) {
                struct multiboot_mmap *mm;

                mm = (struct multiboot_mmap *)(mmap_addr + i);

                if (mm->mm_type != 1) {
                        rsvd[rsvd_nr].first_page =
                            rounddown(mm->mm_base_addr, PAGE_SIZE) / PAGE_SIZE;
                        rsvd[rsvd_nr].npages =
                            roundup(mm->mm_length, PAGE_SIZE) / PAGE_SIZE;
                        rsvd_nr++;
                        if (rsvd_nr == CONFIG_PPM_MAX_RSVD)
                                x86_panic("too many memory holes");
                }

                i += mm->mm_size + 4;
        }

        return rsvd_nr;
}

static void init_bootinfo_core(boot_core_t *core)
{
        memset(core, 0, sizeof(boot_core_t));

        core->gid = hal_lapic_gid();
        core->lid = 0;
        core->cxy = 0;
}

static void init_bootinfo_txt(boot_device_t *dev)
{
        memset(dev, 0, sizeof(boot_device_t));

        dev->base = 0xB8000;
        dev->type = (DEV_FUNC_TXT << 16) | IMPL_TXT_X86;
        dev->channels = 1;
        dev->param0 = 0;
        dev->param1 = 0;
        dev->param2 = 0;
        dev->param3 = 0;

#ifdef NOTYET
    uint32_t    irqs;    /*! number of input IRQs                    */
    boot_irq_t  irq[32]; /*! array of input IRQS (PIC and ICU only)  */
#endif
}

static void init_bootinfo(boot_info_t *info)
{
        size_t offset;

        extern uint64_t __kernel_data_start;
        extern uint64_t __kernel_end;

        memset(info, 0, sizeof(boot_info_t));

        info->signature = 0;

        info->paddr_width = 0;
        info->x_width = 1;
        info->y_width = 1;
        info->x_size = 1;
        info->y_size = 1;
        info->io_cxy = 0;

        info->ext_dev_nr = 1;
        init_bootinfo_txt(&info->ext_dev[0]);

        info->cxy = 0;
        info->cores_nr = 1;
        init_bootinfo_core(&info->core[0]);

        info->rsvd_nr = init_bootinfo_rsvd((boot_rsvd_t *)&info->rsvd);

        init_bootinfo_icu(&info->dev_icu);
        /* TODO: dev_mmc */
        /* TODO: dev_dma */

        offset = hal_gpt_bootstrap_uniformize();
        info->pages_offset = offset / PAGE_SIZE;
        info->pages_nr = init_bootinfo_pages_nr();

        info->kernel_code_start = (intptr_t)(KERNTEXTOFF - KERNBASE);
        info->kernel_code_end = (intptr_t)(&__kernel_data_start - KERNBASE) - 1;
        info->kernel_data_start = (intptr_t)(&__kernel_data_start - KERNBASE);
        info->kernel_code_end = (intptr_t)(&__kernel_end - KERNBASE) - 1;
}

/* -------------------------------------------------------------------------- */

void init_x86_64(paddr_t firstpa)
{
        boot_info_t btinfo;

        /* Initialize the serial port */
        hal_com_init_early();

        x86_printf("[+] init_x86_64 called\n");

        /* Create the global structures */
        gdt_create();
        idt_create();

        /* Identify the features of the cpu */
        cpu_identify();

        /* Attach cpu0 */
        cpu_attach(0);
        x86_printf("[+] cpu_attach called\n");

        x86_printf("[+] bootloader: '%s'\n", mb_loader_name);

        dump_memmap();
        x86_printf("[+] dump finished\n");

        hal_gpt_init(firstpa);
        x86_printf("[+] hal_gpt_init called\n");

        hal_acpi_init();
        x86_printf("[+] hal_acpi_init called\n");

        hal_gpt_bootstrap_reset();
        x86_printf("[+] hal_gpt_bootstrap_reset called\n");

        hal_apic_init();
        x86_printf("[+] hal_apic_init called\n");

        hal_tls_init_cpu0();
        x86_printf("[+] hal_tls_init_cpu0 called\n");

        x86_printf("-> mytest = %z\n", mytest);
        void *hoho = &init_x86_64;
        xptr_t myptr = XPTR(0, &mytest);

        hal_remote_spt(myptr, hoho);
        x86_printf("-> mytest = %Z\n", hal_remote_lpt(myptr));

        init_bootinfo(&btinfo);

        reg_t dummy;
        hal_enable_irq(&dummy);

        while (1);

        kernel_init(&btinfo);

        x86_printf("[+] kernel_init called\n");

        while (1);

//      void x86_stop();
//      x86_stop();
}

/* -------------------------------------------------------------------------- */

/* x86-specific per-cluster structures */
uint8_t gdtstore[PAGE_SIZE] __in_kdata;
uint8_t idtstore[PAGE_SIZE] __in_kdata;

/* x86-specific per-cpu structures */
typedef struct {
        struct tss tss;
        uint8_t intr_stack[STKSIZE];
        uint8_t dbfl_stack[STKSIZE];
        uint8_t nmfl_stack[STKSIZE];
} percpu_archdata_t;
percpu_archdata_t cpudata[CONFIG_MAX_LOCAL_CORES] __in_kdata;

static void
setregion(struct region_descriptor *rd, void *base, uint16_t limit)
{
        rd->rd_limit = limit;
        rd->rd_base = (uint64_t)base;
}

/* -------------------------------------------------------------------------- */

static void
gdt_set_memseg(struct gdt_memseg *sd, void *base, size_t limit,
        int type, int dpl, int gran, int is64)
{
        sd->sd_lolimit = (unsigned)limit;
        sd->sd_lobase = (unsigned long)base;
        sd->sd_type = type;
        sd->sd_dpl = dpl;
        sd->sd_p = 1;
        sd->sd_hilimit = (unsigned)limit >> 16;
        sd->sd_avl = 0;
        sd->sd_long = is64;
        sd->sd_def32 = 0;
        sd->sd_gran = gran;
        sd->sd_hibase = (unsigned long)base >> 24;
}

static void
gdt_set_sysseg(struct gdt_sysseg *sd, void *base, size_t limit,
        int type, int dpl, int gran)
{
        memset(sd, 0, sizeof *sd);
        sd->sd_lolimit = (unsigned)limit;
        sd->sd_lobase = (uint64_t)base;
        sd->sd_type = type;
        sd->sd_dpl = dpl;
        sd->sd_p = 1;
        sd->sd_hilimit = (unsigned)limit >> 16;
        sd->sd_gran = gran;
        sd->sd_hibase = (uint64_t)base >> 24;
}

static void gdt_create()
{
        memset(&gdtstore, 0, PAGE_SIZE);

        /* Flat segments */
        gdt_set_memseg(GDT_ADDR_MEM(gdtstore, GDT_KCODE_SEL), 0,
            0xfffff, SDT_MEMERA, SEL_KPL, 1, 1);
        gdt_set_memseg(GDT_ADDR_MEM(gdtstore, GDT_KDATA_SEL), 0,
            0xfffff, SDT_MEMRWA, SEL_KPL, 1, 1);
        gdt_set_memseg(GDT_ADDR_MEM(gdtstore, GDT_UCODE_SEL), 0,
            0xfffff, SDT_MEMERA, SEL_UPL, 1, 1);
        gdt_set_memseg(GDT_ADDR_MEM(gdtstore, GDT_UDATA_SEL), 0,
            0xfffff, SDT_MEMRWA, SEL_UPL, 1, 1);
}

void cpu_load_gdt()
{
        struct region_descriptor region;
        setregion(&region, &gdtstore, PAGE_SIZE - 1);
        lgdt(&region);
}

/* -------------------------------------------------------------------------- */

static void
idt_set_seg(struct idt_seg *seg, void *func, int ist, int type, int dpl, int sel)
{
        seg->gd_looffset = (uint64_t)func & 0xffff;
        seg->gd_selector = sel;
        seg->gd_ist = ist;
        seg->gd_type = type;
        seg->gd_dpl = dpl;
        seg->gd_p = 1;
        seg->gd_hioffset = (uint64_t)func >> 16;
        seg->gd_zero = 0;
        seg->gd_xx1 = 0;
        seg->gd_xx2 = 0;
        seg->gd_xx3 = 0;
}

static void idt_create()
{
        extern uint64_t x86_traps[], x86_intrs[], x86_rsvd;
        struct idt_seg *idt;
        size_t i;

        idt = (struct idt_seg *)&idtstore;

        /* First, put a dead entry */
        for (i = 0; i < NIDT; i++) {
                idt_set_seg(&idt[i], (void *)&x86_rsvd, 0,
                    SDT_SYS386IGT, SEL_KPL, GDT_FIXED_SEL(GDT_KCODE_SEL, SEL_KPL));
        }

        /* General exceptions */
        for (i = CPUVEC_MIN; i < CPUVEC_MAX; i++) {
                idt_set_seg(&idt[i], (void *)x86_traps[i - CPUVEC_MIN], 0,
                    SDT_SYS386IGT, SEL_KPL, GDT_FIXED_SEL(GDT_KCODE_SEL, SEL_KPL));
        }

        /* Dynamically configured interrupts */
        for (i = DYNVEC_MIN; i < DYNVEC_MAX; i++) {
                idt_set_seg(&idt[i], (void *)x86_intrs[i - DYNVEC_MIN], 0,
                    SDT_SYS386IGT, SEL_KPL, GDT_FIXED_SEL(GDT_KCODE_SEL, SEL_KPL));
        }
}

void cpu_load_idt()
{
        struct region_descriptor region;
        setregion(&region, &idtstore, PAGE_SIZE - 1);
        lidt(&region);
}

/* -------------------------------------------------------------------------- */

int tss_alloc(struct tss *tss, size_t lid)
{
        int slot;

        slot = GDT_CPUTSS_SEL + lid;

        gdt_set_sysseg(GDT_ADDR_SYS(gdtstore, slot), tss,
            sizeof(*tss) - 1, SDT_SYS386TSS, SEL_KPL, 0);

        return GDT_DYNAM_SEL(slot, SEL_KPL);
}

void cpu_create_tss(size_t lid)
{
        percpu_archdata_t *data = &cpudata[lid];
        struct tss *tss = &data->tss;
        int sel;

        /* Create the tss */
        memset(tss, 0, sizeof(*tss));

        /* tss->tss_rsp0 */
        tss->tss_ist[0] = (uint64_t)data->intr_stack[lid] + STKSIZE;
        tss->tss_ist[1] = (uint64_t)data->dbfl_stack[lid] + STKSIZE;
        tss->tss_ist[2] = (uint64_t)data->nmfl_stack[lid] + STKSIZE;
        tss->tss_iobase = IOMAP_INVALOFF << 16;
        sel = tss_alloc(tss, lid);

        /* Load it */
        ltr(sel);
}

/* -------------------------------------------------------------------------- */

uint64_t cpu_features[4] __in_kdata;

void cpu_identify()
{
        /*
         * desc[0] = eax
         * desc[1] = ebx
         * desc[2] = ecx
         * desc[3] = edx
         */
        uint32_t desc[4];
        char vendor[13];
        size_t lvl;

        /*
         * Get information from the standard cpuid leafs
         */
        cpuid(0, 0, (uint32_t *)&desc);

        lvl = (uint64_t)desc[0];
        x86_printf("-> cpuid standard level: %z\n", lvl);

        memcpy(vendor + 0, &desc[1], sizeof(uint32_t));
        memcpy(vendor + 8, &desc[2], sizeof(uint32_t));
        memcpy(vendor + 4, &desc[3], sizeof(uint32_t));
        vendor[12] = '\0';
        x86_printf("-> CPU vendor: '%s'\n", vendor);

        if (lvl >= 1) {
                cpuid(1, 0, (uint32_t *)&desc);
                cpu_features[0] = desc[3];
                cpu_features[1] = desc[2];
        }

        /*
         * Get information from the extended cpuid leafs
         */
        cpuid(0x80000000, 0, desc);

        lvl = (uint64_t)desc[0];
        x86_printf("-> cpuid extended level: %Z\n", lvl);
}

/* -------------------------------------------------------------------------- */

void cpu_attach(size_t lid)
{
        cpu_load_gdt();
        cpu_load_idt();
        cpu_create_tss(lid);

        if (cpu_features[0] & CPUID_PSE) {
                lcr4(rcr4() | CR4_PSE);
                tlbflushg();
        } else {
                /*
                 * amd64 supports PSE by default, if it's not here we have a
                 * problem
                 */
                x86_panic("PSE not supported");
        }
}