source: trunk/hal/x86_64/core/hal_register.h

Last change on this file was 234, checked in by max@…, 5 years ago

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1/*
2 * hal_register.h - Values available in some x86 registers
3 *
4 * Copyright (c) 2017 Maxime Villard
5 *
6 * This file is part of ALMOS-MKH.
7 *
8 * ALMOS-MKH is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2.0 of the License.
11 *
12 * ALMOS-MKH is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with ALMOS-MKH; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22/*
23 * %cr0
24 */
25#define CR0_PE  0x00000001      /* Protected mode Enable */
26#define CR0_MP  0x00000002      /* "Math" Present (NPX or NPX emulator) */
27#define CR0_EM  0x00000004      /* EMulate non-NPX coproc. (trap ESC only) */
28#define CR0_TS  0x00000008      /* Task Switched (if MP, trap ESC and WAIT) */
29#define CR0_ET  0x00000010      /* Extension Type (387 (if set) vs 287) */
30#define CR0_NE  0x00000020      /* Numeric Error enable (EX16 vs IRQ13) */
31#define CR0_WP  0x00010000      /* Write Protect (honor PG_RW in all modes) */
32#define CR0_AM  0x00040000      /* Alignment Mask (set to enable AC flag) */
33#define CR0_NW  0x20000000      /* Not Write-through */
34#define CR0_CD  0x40000000      /* Cache Disable */
35#define CR0_PG  0x80000000      /* PaGing enable */
36
37/*
38 * %cr4
39 */
40#define CR4_VME         0x00000001 /* virtual 8086 mode extension enable */
41#define CR4_PVI         0x00000002 /* protected mode virtual interrupt enable */
42#define CR4_TSD         0x00000004 /* restrict RDTSC instruction to cpl 0 */
43#define CR4_DE          0x00000008 /* debugging extension */
44#define CR4_PSE         0x00000010 /* large (4MB) page size enable */
45#define CR4_PAE         0x00000020 /* physical address extension enable */
46#define CR4_MCE         0x00000040 /* machine check enable */
47#define CR4_PGE         0x00000080 /* page global enable */
48#define CR4_PCE         0x00000100 /* enable RDPMC instruction for all cpls */
49#define CR4_OSFXSR      0x00000200 /* enable fxsave/fxrestor and SSE */
50#define CR4_OSXMMEXCPT  0x00000400 /* enable unmasked SSE exceptions */
51#define CR4_UMIP        0x00000800 /* user-mode instruction prevention */
52#define CR4_VMXE        0x00002000 /* enable VMX operations */
53#define CR4_SMXE        0x00004000 /* enable SMX operations */
54#define CR4_FSGSBASE    0x00010000 /* enable *FSBASE and *GSBASE instructions */
55#define CR4_PCIDE       0x00020000 /* enable Process Context IDentifiers */
56#define CR4_OSXSAVE     0x00040000 /* enable xsave and xrestore */
57#define CR4_SMEP        0x00100000 /* enable SMEP support */
58#define CR4_SMAP        0x00200000 /* enable SMAP support */
59#define CR4_PKE         0x00400000 /* protection key enable */
60
61/*
62 * MSRs
63 */
64#define MSR_EFER        0xc0000080              /* Extended feature enable */
65#define         EFER_SCE        0x00000001      /* SYSCALL extension */
66#define         EFER_LME        0x00000100      /* Long Mode Active */
67#define         EFER_LMA        0x00000400      /* Long Mode Enabled */
68#define         EFER_NXE        0x00000800      /* No-Execute Enabled */
69#define         EFER_SVME       0x00001000      /* Secure Virtual Machine En. */
70#define         EFER_LMSLE      0x00002000      /* Long Mode Segment Limit E. */
71#define         EFER_FFXSR      0x00004000      /* Fast FXSAVE/FXRSTOR En. */
72#define         EFER_TCE        0x00008000      /* Translation Cache Ext. */
73
74#define MSR_STAR        0xc0000081              /* 32 bit syscall gate addr */
75#define MSR_LSTAR       0xc0000082              /* 64 bit syscall gate addr */
76#define MSR_CSTAR       0xc0000083              /* compat syscall gate addr */
77#define MSR_SFMASK      0xc0000084              /* flags to clear on syscall */
78
79#define MSR_FSBASE      0xc0000100              /* 64bit offset for fs: */
80#define MSR_GSBASE      0xc0000101              /* 64bit offset for gs: */
81#define MSR_KERNELGSBASE 0xc0000102             /* storage for swapgs ins */
82
83#define MSR_APICBASE            0x01b
84#define         APICBASE_BSP            0x00000100      /* boot processor */
85#define         APICBASE_EXTD           0x00000400      /* x2APIC mode */
86#define         APICBASE_EN             0x00000800      /* software enable */
87#define         APICBASE_PHYSADDR       0xfffff000      /* physical address */
88
89/*
90 * CPUID
91 */
92/* Fn00000001 %edx features */
93#define CPUID_FPU       0x00000001      /* processor has an FPU? */
94#define CPUID_VME       0x00000002      /* has virtual mode (%cr4's VME/PVI) */
95#define CPUID_DE        0x00000004      /* has debugging extension */
96#define CPUID_PSE       0x00000008      /* has 4MB page size extension */
97#define CPUID_TSC       0x00000010      /* has time stamp counter */
98#define CPUID_MSR       0x00000020      /* has mode specific registers */
99#define CPUID_PAE       0x00000040      /* has phys address extension */
100#define CPUID_MCE       0x00000080      /* has machine check exception */
101#define CPUID_CX8       0x00000100      /* has CMPXCHG8B instruction */
102#define CPUID_APIC      0x00000200      /* has enabled APIC */
103#define CPUID_B10       0x00000400      /* reserved, MTRR */
104#define CPUID_SEP       0x00000800      /* has SYSENTER/SYSEXIT extension */
105#define CPUID_MTRR      0x00001000      /* has memory type range register */
106#define CPUID_PGE       0x00002000      /* has page global extension */
107#define CPUID_MCA       0x00004000      /* has machine check architecture */
108#define CPUID_CMOV      0x00008000      /* has CMOVcc instruction */
109#define CPUID_PAT       0x00010000      /* Page Attribute Table */
110#define CPUID_PSE36     0x00020000      /* 36-bit PSE */
111#define CPUID_PN        0x00040000      /* processor serial number */
112#define CPUID_CFLUSH    0x00080000      /* CLFLUSH insn supported */
113#define CPUID_B20       0x00100000      /* reserved */
114#define CPUID_DS        0x00200000      /* Debug Store */
115#define CPUID_ACPI      0x00400000      /* ACPI performance modulation regs */
116#define CPUID_MMX       0x00800000      /* MMX supported */
117#define CPUID_FXSR      0x01000000      /* fast FP/MMX save/restore */
118#define CPUID_SSE       0x02000000      /* streaming SIMD extensions */
119#define CPUID_SSE2      0x04000000      /* streaming SIMD extensions #2 */
120#define CPUID_SS        0x08000000      /* self-snoop */
121#define CPUID_HTT       0x10000000      /* Hyper-Threading Technology */
122#define CPUID_TM        0x20000000      /* thermal monitor (TCC) */
123#define CPUID_IA64      0x40000000      /* IA-64 architecture */
124#define CPUID_SBF       0x80000000      /* signal break on FERR */
125
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