[25] | 1 | /* |
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| 2 | * hal_boot.S - Kernel boot entry point |
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| 3 | * |
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[29] | 4 | * Copyright (c) 2017 Maxime Villard |
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| 5 | * This code is inspired a lot from the NetBSD boot procedure, written by |
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| 6 | * Maxime Villard too. XXX copyright |
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[25] | 7 | * |
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[29] | 8 | * This file is part of ALMOS-MKH. |
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[25] | 9 | * |
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[29] | 10 | * ALMOS-MKH is free software; you can redistribute it and/or modify it |
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[25] | 11 | * under the terms of the GNU General Public License as published by |
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| 12 | * the Free Software Foundation; version 2.0 of the License. |
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| 13 | * |
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[29] | 14 | * ALMOS-MKH is distributed in the hope that it will be useful, but |
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[25] | 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 17 | * General Public License for more details. |
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| 18 | * |
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| 19 | * You should have received a copy of the GNU General Public License |
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[29] | 20 | * along with ALMOS-MKH.; if not, write to the Free Software Foundation, |
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[25] | 21 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 22 | */ |
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| 23 | |
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[29] | 24 | #define x86_ASM |
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[25] | 25 | #include <hal_boot.h> |
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| 26 | #include <hal_register.h> |
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| 27 | #include <hal_segmentation.h> |
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| 28 | |
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| 29 | #define MULTIBOOT_HEADER_MAGIC 0x1BADB002 |
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| 30 | #define MULTIBOOT_HEADER_FLAGS 0x00000000 |
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| 31 | #define MULTIBOOT_INFO_MAGIC 0x2BADB002 |
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| 32 | #define CHECKSUM -(MULTIBOOT_HEADER_MAGIC + MULTIBOOT_HEADER_FLAGS) |
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| 33 | |
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| 34 | #if L2_SLOT_KERNBASE > 0 |
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| 35 | #define TABLE_L2_ENTRIES (2 * (NKL2_KIMG_ENTRIES + 1)) |
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| 36 | #else |
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| 37 | #define TABLE_L2_ENTRIES (NKL2_KIMG_ENTRIES + 1) |
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| 38 | #endif |
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| 39 | |
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| 40 | #if L3_SLOT_KERNBASE > 0 |
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| 41 | #define TABLE_L3_ENTRIES (2 * NKL3_KIMG_ENTRIES) |
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| 42 | #else |
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| 43 | #define TABLE_L3_ENTRIES NKL3_KIMG_ENTRIES |
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| 44 | #endif |
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| 45 | |
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| 46 | #define PROC0_PML4_OFF 0 |
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| 47 | #define PROC0_STK_OFF (PROC0_PML4_OFF + 1 * PAGE_SIZE) |
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| 48 | #define PROC0_PTP3_OFF (PROC0_STK_OFF + STKPAGES * PAGE_SIZE) |
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| 49 | #define PROC0_PTP2_OFF (PROC0_PTP3_OFF + NKL4_KIMG_ENTRIES * PAGE_SIZE) |
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| 50 | #define PROC0_PTP1_OFF (PROC0_PTP2_OFF + TABLE_L3_ENTRIES * PAGE_SIZE) |
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| 51 | #define TABLESIZE \ |
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| 52 | ((NKL4_KIMG_ENTRIES + TABLE_L3_ENTRIES + TABLE_L2_ENTRIES + 1 + STKPAGES) \ |
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| 53 | * PAGE_SIZE) |
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| 54 | |
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| 55 | /* |
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| 56 | * fillkpt - Fill in a kernel page table |
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| 57 | * eax = pte (page frame | control | status) |
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| 58 | * ebx = page table address |
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| 59 | * ecx = number of pages to map |
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| 60 | * |
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| 61 | * Each entry is 8 (PDE_SIZE) bytes long: we must set the 4 upper bytes to 0. |
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| 62 | */ |
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| 63 | #define fillkpt \ |
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| 64 | cmpl $0,%ecx ; /* zero-sized? */ \ |
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| 65 | je 2f ; \ |
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| 66 | 1: movl $0,(PDE_SIZE-4)(%ebx) ; /* upper 32 bits: 0 */ \ |
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| 67 | movl %eax,(%ebx) ; /* store phys addr */ \ |
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| 68 | addl $PDE_SIZE,%ebx ; /* next PTE/PDE */ \ |
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| 69 | addl $PAGE_SIZE,%eax ; /* next phys page */ \ |
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| 70 | loop 1b ; \ |
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| 71 | 2: ; |
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| 72 | |
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| 73 | /* |
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| 74 | * fillkpt_nox - Same as fillkpt, but sets the NX/XD bit. |
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| 75 | */ |
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| 76 | #define fillkpt_nox \ |
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| 77 | cmpl $0,%ecx ; /* zero-sized? */ \ |
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| 78 | je 2f ; \ |
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| 79 | 1: movl $PG_NX32,(PDE_SIZE-4)(%ebx); /* upper 32 bits: NX */ \ |
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| 80 | movl %eax,(%ebx) ; /* store phys addr */ \ |
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| 81 | addl $PDE_SIZE,%ebx ; /* next PTE/PDE */ \ |
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| 82 | addl $PAGE_SIZE,%eax ; /* next phys page */ \ |
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| 83 | loop 1b ; \ |
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| 84 | 2: ; |
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| 85 | |
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| 86 | /* |
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| 87 | * fillkpt_blank - Fill in a kernel page table with blank entries |
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| 88 | * ebx = page table address |
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| 89 | * ecx = number of pages to map |
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| 90 | */ |
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| 91 | #define fillkpt_blank \ |
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| 92 | cmpl $0,%ecx ; /* zero-sized? */ \ |
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| 93 | je 2f ; \ |
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| 94 | 1: movl $0,(PDE_SIZE-4)(%ebx) ; /* upper 32 bits: 0 */ \ |
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| 95 | movl $0,(%ebx) ; /* lower 32 bits: 0 */ \ |
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| 96 | addl $PDE_SIZE,%ebx ; /* next PTE/PDE */ \ |
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| 97 | loop 1b ; \ |
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| 98 | 2: ; |
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| 99 | |
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[29] | 100 | /* |
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| 101 | * killkpt - Destroy a kernel page table (long mode) |
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| 102 | * rbx = page table address |
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| 103 | * rcx = number of pages to destroy |
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| 104 | */ |
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| 105 | #define killkpt \ |
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| 106 | 1: movq $0,(%rbx) ; \ |
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| 107 | addq $PDE_SIZE,%rbx ; \ |
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| 108 | loop 1b ; |
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| 109 | |
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[25] | 110 | /* 32bit version of PG_NX */ |
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| 111 | #define PG_NX32 0x80000000 |
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| 112 | |
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| 113 | #define RELOC(x) ((x) - KERNBASE) |
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| 114 | |
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| 115 | .globl start_x86_64 |
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| 116 | .globl L4paddr |
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[29] | 117 | .globl iom_base |
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[25] | 118 | |
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| 119 | /* |
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| 120 | * The multiboot header |
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| 121 | */ |
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| 122 | .section .boot,"ax",@progbits |
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| 123 | multiboot_header: |
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| 124 | .align 4 |
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| 125 | .long MULTIBOOT_HEADER_MAGIC |
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| 126 | .long MULTIBOOT_HEADER_FLAGS |
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| 127 | .long CHECKSUM |
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| 128 | |
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| 129 | /* |
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| 130 | * The variables used in the boot procedure. |
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| 131 | */ |
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| 132 | .section .data |
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| 133 | .align 4 |
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| 134 | |
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| 135 | .type L4paddr, @object |
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| 136 | L4paddr: .quad 0 /* paddr of L4 */ |
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| 137 | |
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[29] | 138 | .type iom_base, @object |
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| 139 | iom_base: .quad 0 /* virt. addr. of ISA I/O MEM */ |
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| 140 | |
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| 141 | |
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[25] | 142 | #define GDT64_LIMIT gdt64_end-gdt64_start-1 |
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| 143 | /* Temporary gdt64, with base address in low memory */ |
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| 144 | .type gdt64_lo, @object |
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| 145 | gdt64_lo: |
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| 146 | .word GDT64_LIMIT |
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| 147 | .quad RELOC(gdt64_start) |
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| 148 | .align 64 |
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| 149 | |
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| 150 | /* Temporary gdt64, with base address in high memory */ |
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| 151 | .type gdt64_hi, @object |
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| 152 | gdt64_hi: |
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| 153 | .word GDT64_LIMIT |
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| 154 | .quad gdt64_start |
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| 155 | .align 64 |
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| 156 | #undef GDT64_LIMIT |
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| 157 | |
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| 158 | .type gdt64_start, @object |
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| 159 | gdt64_start: |
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| 160 | .quad 0x0000000000000000 /* always empty */ |
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| 161 | .quad 0x00af9a000000ffff /* kernel CS */ |
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| 162 | .quad 0x00cf92000000ffff /* kernel DS */ |
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| 163 | gdt64_end: |
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| 164 | |
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| 165 | .type farjmp64, @object |
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| 166 | farjmp64: |
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| 167 | .long RELOC(longmode) |
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[29] | 168 | .word GDT_FIXED_SEL(GDT_KCODE_SEL, SEL_KPL) |
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[25] | 169 | .align 64 |
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| 170 | |
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| 171 | /* Space for the temporary stack */ |
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| 172 | .size tmpstk, tmpstk - . |
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| 173 | .space 512 |
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| 174 | tmpstk: |
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| 175 | |
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| 176 | .text |
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| 177 | |
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| 178 | start_x86_64: |
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| 179 | .code32 |
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| 180 | |
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| 181 | /* Warm boot */ |
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| 182 | movw $0x1234,0x472 |
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| 183 | |
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| 184 | /* Make sure it is a multiboot-compliant bootloader. */ |
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[29] | 185 | // cmpl $MULTIBOOT_INFO_MAGIC,%eax |
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| 186 | // jne boot_panic |
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[25] | 187 | |
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| 188 | movl $RELOC(tmpstk),%esp |
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| 189 | |
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| 190 | /* Reset the PSL. */ |
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| 191 | pushl $PSL_MBO |
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| 192 | popfl |
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| 193 | |
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| 194 | /* |
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| 195 | * There are four levels of pages in amd64: PML4 -> PDP -> PD -> PT. They will |
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| 196 | * be referred to as: L4 -> L3 -> L2 -> L1. |
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| 197 | * |
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| 198 | * Virtual address space of the kernel: |
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| 199 | * +---------------+------------+-----------------------------------+--- |
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| 200 | * | TEXT + RODATA | DATA + BSS | L4 -> PROC0 STK -> L3 -> L2 -> L1 | |
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| 201 | * +---------------+------------+-----------------------------------+--- |
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| 202 | * (1) |
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| 203 | * |
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| 204 | * ---+-------------+ |
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| 205 | * | ISA I/O MEM | |
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| 206 | * ---+-------------+ |
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| 207 | * (2) |
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| 208 | * |
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| 209 | * PROC0 STK is obviously not linked as a page level. It just happens to be |
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| 210 | * caught between L4 and L3. |
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| 211 | * |
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| 212 | * (PROC0 STK + L4 + L3 + L2 + L1) is later referred to as BOOTSTRAP TABLES. |
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| 213 | * |
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| 214 | * ISA I/O MEM has no physical page allocated here, just virtual addresses. |
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| 215 | * |
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| 216 | * Important note: the kernel segments are properly 4k-aligned |
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| 217 | * (see kern.ldscript), so there's no need to enforce alignment. |
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| 218 | */ |
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| 219 | |
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| 220 | /* Find end of kernel image; brings us on (1). */ |
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| 221 | movl $RELOC(__kernel_end),%edi |
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| 222 | |
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| 223 | /* Align up for BOOTSTRAP TABLES. */ |
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| 224 | movl %edi,%esi |
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| 225 | addl $PGOFSET,%esi |
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| 226 | andl $~PGOFSET,%esi |
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| 227 | |
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| 228 | /* We are on the BOOTSTRAP TABLES. Save L4's physical address. */ |
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| 229 | movl $RELOC(L4paddr),%ebp |
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| 230 | movl %esi,(%ebp) |
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| 231 | movl $0,4(%ebp) |
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| 232 | |
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| 233 | /* Now, zero out the BOOTSTRAP TABLES (before filling them in). */ |
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| 234 | movl %esi,%edi |
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| 235 | xorl %eax,%eax |
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| 236 | cld |
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| 237 | movl $TABLESIZE,%ecx |
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| 238 | shrl $2,%ecx |
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| 239 | rep |
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| 240 | stosl /* copy eax -> edi */ |
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| 241 | |
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| 242 | /* |
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| 243 | * Build the page tables and levels. We go from L1 to L4, and link the levels |
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| 244 | * together. Note: RELOC computes &addr - KERNBASE in 32 bits; the value can't |
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| 245 | * be > 4G, or we can't deal with it anyway, since we are in 32bit mode. |
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| 246 | */ |
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| 247 | /* |
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| 248 | * Build L1. |
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| 249 | */ |
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| 250 | leal (PROC0_PTP1_OFF)(%esi),%ebx |
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| 251 | |
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| 252 | /* Skip the area below the kernel text. */ |
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| 253 | movl $(KERNTEXTOFF_LO - KERNBASE_LO),%ecx |
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| 254 | shrl $PGSHIFT,%ecx |
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| 255 | fillkpt_blank |
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| 256 | |
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| 257 | /* Map the kernel code RX. */ |
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| 258 | movl $(KERNTEXTOFF_LO - KERNBASE_LO),%eax /* start of TEXT */ |
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| 259 | movl $RELOC(__kernel_data_start),%ecx |
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| 260 | subl %eax,%ecx |
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| 261 | shrl $PGSHIFT,%ecx |
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[29] | 262 | orl $(PG_V|PG_KR|PG_G),%eax |
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[25] | 263 | fillkpt |
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| 264 | |
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| 265 | /* Map the kernel data RW. */ |
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| 266 | movl $RELOC(__kernel_data_start),%eax |
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| 267 | movl $RELOC(__kernel_end),%ecx |
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| 268 | subl %eax,%ecx |
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| 269 | shrl $PGSHIFT,%ecx |
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[29] | 270 | orl $(PG_V|PG_KW|PG_G),%eax |
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[25] | 271 | fillkpt_nox |
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| 272 | |
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| 273 | /* Map the BOOTSTRAP TABLES RW. */ |
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| 274 | movl $RELOC(__kernel_end),%eax /* start of BOOTSTRAP TABLES */ |
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| 275 | movl $TABLESIZE,%ecx /* length of BOOTSTRAP TABLES */ |
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| 276 | shrl $PGSHIFT,%ecx |
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[29] | 277 | orl $(PG_V|PG_KW|PG_G),%eax |
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[25] | 278 | fillkpt_nox |
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| 279 | |
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| 280 | /* We are on (2). Map ISA I/O MEM RW. */ |
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| 281 | movl $IOM_BEGIN,%eax |
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| 282 | movl $IOM_SIZE,%ecx /* size of ISA I/O MEM */ |
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| 283 | shrl $PGSHIFT,%ecx |
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[29] | 284 | orl $(PG_V|PG_KW|PG_G),%eax |
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[25] | 285 | fillkpt_nox |
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| 286 | |
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| 287 | /* |
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| 288 | * Build L2. Linked to L1. |
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| 289 | */ |
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| 290 | leal (PROC0_PTP2_OFF)(%esi),%ebx |
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| 291 | leal (PROC0_PTP1_OFF)(%esi),%eax |
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| 292 | orl $(PG_V|PG_KW),%eax |
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| 293 | movl $(NKL2_KIMG_ENTRIES+1),%ecx |
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| 294 | fillkpt |
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| 295 | |
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| 296 | #if L2_SLOT_KERNBASE > 0 |
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| 297 | /* If needed, set up level 2 entries for actual kernel mapping */ |
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| 298 | leal (PROC0_PTP2_OFF + L2_SLOT_KERNBASE * PDE_SIZE)(%esi),%ebx |
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| 299 | leal (PROC0_PTP1_OFF)(%esi),%eax |
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| 300 | orl $(PG_V|PG_KW),%eax |
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| 301 | movl $(NKL2_KIMG_ENTRIES+1),%ecx |
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| 302 | fillkpt |
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| 303 | #endif |
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| 304 | |
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| 305 | /* |
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| 306 | * Build L3. Linked to L2. |
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| 307 | */ |
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| 308 | leal (PROC0_PTP3_OFF)(%esi),%ebx |
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| 309 | leal (PROC0_PTP2_OFF)(%esi),%eax |
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| 310 | orl $(PG_V|PG_KW),%eax |
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| 311 | movl $NKL3_KIMG_ENTRIES,%ecx |
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| 312 | fillkpt |
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| 313 | |
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| 314 | #if L3_SLOT_KERNBASE > 0 |
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| 315 | /* If needed, set up level 3 entries for actual kernel mapping */ |
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| 316 | leal (PROC0_PTP3_OFF + L3_SLOT_KERNBASE * PDE_SIZE)(%esi),%ebx |
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| 317 | leal (PROC0_PTP2_OFF)(%esi),%eax |
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| 318 | orl $(PG_V|PG_KW),%eax |
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| 319 | movl $NKL3_KIMG_ENTRIES,%ecx |
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| 320 | fillkpt |
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| 321 | #endif |
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| 322 | |
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| 323 | /* |
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| 324 | * Build L4 for identity mapping. Linked to L3. |
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| 325 | */ |
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| 326 | leal (PROC0_PML4_OFF)(%esi),%ebx |
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| 327 | leal (PROC0_PTP3_OFF)(%esi),%eax |
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| 328 | orl $(PG_V|PG_KW),%eax |
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| 329 | movl $NKL4_KIMG_ENTRIES,%ecx |
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| 330 | fillkpt |
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| 331 | |
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| 332 | /* Set up L4 entries for actual kernel mapping */ |
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| 333 | leal (PROC0_PML4_OFF + L4_SLOT_KERNBASE * PDE_SIZE)(%esi),%ebx |
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| 334 | leal (PROC0_PTP3_OFF)(%esi),%eax |
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| 335 | orl $(PG_V|PG_KW),%eax |
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| 336 | movl $NKL4_KIMG_ENTRIES,%ecx |
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| 337 | fillkpt |
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| 338 | |
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| 339 | /* Install recursive top level PDE (one entry) */ |
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| 340 | leal (PROC0_PML4_OFF + PDIR_SLOT_PTE * PDE_SIZE)(%esi),%ebx |
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| 341 | leal (PROC0_PML4_OFF)(%esi),%eax |
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| 342 | orl $(PG_V|PG_KW),%eax |
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| 343 | movl $1,%ecx |
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| 344 | fillkpt_nox |
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| 345 | |
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| 346 | /* |
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| 347 | * Startup checklist: |
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| 348 | * 1. Enable PAE (and SSE while here). |
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| 349 | */ |
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| 350 | movl %cr4,%eax |
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[29] | 351 | orl $(CR4_PAE|CR4_OSFXSR|CR4_OSXMMEXCPT|CR4_PGE),%eax |
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[25] | 352 | movl %eax,%cr4 |
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| 353 | |
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| 354 | /* |
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| 355 | * 2. Set Long Mode Enable in EFER. Also enable the syscall extensions, |
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| 356 | * and NOX. |
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| 357 | */ |
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| 358 | movl $MSR_EFER,%ecx |
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| 359 | rdmsr |
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| 360 | xorl %eax,%eax /* XXX */ |
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| 361 | orl $(EFER_LME|EFER_SCE|EFER_NXE),%eax |
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| 362 | wrmsr |
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| 363 | |
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| 364 | /* |
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| 365 | * 3. Load %cr3 with pointer to PML4. |
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| 366 | */ |
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| 367 | movl %esi,%eax |
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| 368 | movl %eax,%cr3 |
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| 369 | |
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| 370 | /* |
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| 371 | * 4. Enable paging and the rest of it. |
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| 372 | */ |
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| 373 | movl %cr0,%eax |
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| 374 | orl $(CR0_PE|CR0_PG|CR0_NE|CR0_TS|CR0_MP|CR0_WP|CR0_AM),%eax |
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| 375 | movl %eax,%cr0 |
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| 376 | jmp compat |
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| 377 | compat: |
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| 378 | |
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| 379 | /* |
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| 380 | * 5. Not quite done yet, we're now in a compatibility segment, in |
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| 381 | * legacy mode. We must jump to a long mode segment. Need to set up |
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| 382 | * a temporary GDT with a long mode segment in it to do that. |
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| 383 | */ |
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| 384 | movl $RELOC(gdt64_lo),%eax |
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| 385 | lgdt (%eax) |
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| 386 | movl $RELOC(farjmp64),%eax |
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| 387 | ljmp *(%eax) |
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| 388 | |
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| 389 | .code64 |
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| 390 | longmode: |
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| 391 | /* |
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| 392 | * 6. Finally, we're in long mode. However, we're still in the identity |
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| 393 | * mapped area (could not jump out of that earlier because it would |
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| 394 | * have been a > 32bit jump). We can do that now, so here we go. |
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| 395 | */ |
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| 396 | movabsq $longmode_hi,%rax |
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[29] | 397 | jmp *%rax |
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[25] | 398 | |
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| 399 | longmode_hi: |
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| 400 | /* |
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| 401 | * We left the identity mapped area. Base address of |
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| 402 | * the temporary gdt64 should now be in high memory. |
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| 403 | */ |
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| 404 | movq $RELOC(gdt64_hi),%rax |
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| 405 | lgdt (%rax) |
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| 406 | |
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| 407 | /* |
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| 408 | * We have arrived. There's no need anymore for the identity mapping in |
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| 409 | * low memory, remove it. |
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| 410 | */ |
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| 411 | movq $KERNBASE,%r8 |
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| 412 | |
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[29] | 413 | #if L2_SLOT_KERNBASE > 0 |
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| 414 | movq $(NKL2_KIMG_ENTRIES+1),%rcx |
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| 415 | leaq (PROC0_PTP2_OFF)(%rsi),%rbx /* old, phys address */ |
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| 416 | addq %r8,%rbx /* new, virt address */ |
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| 417 | killkpt |
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| 418 | #endif |
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[25] | 419 | |
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[29] | 420 | #if L3_SLOT_KERNBASE > 0 |
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| 421 | movq $NKL3_KIMG_ENTRIES,%rcx |
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| 422 | leaq (PROC0_PTP3_OFF)(%rsi),%rbx /* old, phys address */ |
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| 423 | addq %r8,%rbx /* new, virt address */ |
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| 424 | killkpt |
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| 425 | #endif |
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[25] | 426 | |
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[29] | 427 | movq $NKL4_KIMG_ENTRIES,%rcx |
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| 428 | leaq (PROC0_PML4_OFF)(%rsi),%rbx /* old, phys address of PML4 */ |
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| 429 | addq %r8,%rbx /* new, virt address of PML4 */ |
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| 430 | killkpt |
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[25] | 431 | |
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[29] | 432 | /* Relocate atdevbase. */ |
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| 433 | movq $(TABLESIZE+KERNBASE),%rdx |
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| 434 | addq %rsi,%rdx |
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| 435 | movq %rdx,iom_base(%rip) |
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[25] | 436 | |
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[29] | 437 | /* Set up bootstrap stack. */ |
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| 438 | leaq (PROC0_STK_OFF)(%rsi),%rax |
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| 439 | addq %r8,%rax |
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| 440 | leaq (STKSIZE)(%rax),%rsp |
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| 441 | xorq %rbp,%rbp /* mark end of frames */ |
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| 442 | |
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| 443 | xorw %ax,%ax |
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| 444 | movw %ax,%gs |
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| 445 | movw %ax,%fs |
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| 446 | |
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| 447 | /* The first physical page available. */ |
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| 448 | leaq (TABLESIZE)(%rsi),%rdi |
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| 449 | |
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| 450 | call init_x86_64 |
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| 451 | |
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