source: trunk/kernel/arch/tsar/mmu-info.c @ 1

Last change on this file since 1 was 1, checked in by alain, 5 years ago

First import

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1/*
2 * mmu-info.c - TSAR MMU exceptions related informations
3 *
4 * Copyright (c) 2008,2009,2010,2011,2012 Ghassan Almaless
5 * Copyright (c) 2011,2012 UPMC Sorbonne Universites
6 *
7 * This file is part of ALMOS-kernel.
8 *
9 * ALMOS-kernel is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2.0 of the License.
12 *
13 * ALMOS-kernel is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with ALMOS-kernel; if not, write to the Free Software Foundation,
20 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 */
22
23#define _USE_MMU_INFO_H_
24#include <mmu-info.h>
25#include <bits.h>
26
27#define MMU_UNKNOWN_ERR  0x0000
28
29static mmu_except_info_t mmu_except_db[] = 
30{{0x0001, "MMU_WRITE_PT1_UNMAPPED", "Write access : Page fault on Table 1 (invalid PTE)", "Non Fatal Error"},
31 {0x0002, "MMU_WRITE_PT2_UNMAPPED", "Write access : Page fault on Table 2 (invalid PTE)", "Non Fatal Error"},
32 {0x0004, "MMU_WRITE_PRIVILEGE_VIOLATION", "Write access : Protected access in user mode", "User Error"},
33 {0x0008, "MMU_WRITE_ACCES_VIOLATION","Write access : Write to a non writable page", "User error"},
34 {0x0020, "MMU_WRITE_UNDEFINED_XTN","Write access : Undefined external access address","User error"},
35 {0x0040, "MMU_WRITE_PT1_ILLEGAL_ACCESS","Write access : Bus Error in Table1 access","Kernel error"},
36 {0x0080, "MMU_WRITE_PT2_ILLEGAL_ACCESS","Write access : Bus Error in Table2 access","Kernel error"},
37 {0x0100, "MMU_WRITE_DATA_ILLEGAL_ACCESS","Write access : Bus Error during the cache access","Kernel error"},
38 {0x1001, "MMU_READ_PT1_UNMAPPED","Read access : Page fault on Table1 (invalid PTE)","non fatal error"},
39 {0x1002, "MMU_READ_PT2_UNMAPPED","Read access : Page fault on Table 2 (invalid PTE)","non fatal error"},
40 {0x1004, "MMU_READ_PRIVILEGE_VIOLATION","Read access : Protected access in user mode","User error"},
41 {0x1010, "MMU_READ_EXEC_VIOLATION","Read access : Exec access to a non exec page","User error"},
42 {0x1020, "MMU_READ_UNDEFINED_XTN","Read access : Undefined external access address","User error"},
43 {0x1040, "MMU_READ_PT1_ILLEGAL_ACCESS","Read access : Bus Error in Table1 access","Kernel error"},
44 {0x1080, "MMU_READ_PT2_ILLEGAL_ACCESS","Read access : Bus Error in Table2 access","Kernel error"},
45 {0x1100, "MMU_READ_DATA_ILLEGAL_ACCESS","Read access : Bus Error during the cache access","Kernel error"},
46 {MMU_UNKNOWN_ERR, "UNKNOWN", "Exception Detected but no MMU Error code has been found", "Disfunction of MMU's Error Report"}}; 
47
48
49
50inline mmu_except_info_t* mmu_except_get_entry(uint_t mmu_err_val)
51{
52        uint_t entry = 0;
53
54        while(mmu_except_db[entry].err != MMU_UNKNOWN_ERR)
55        {
56                if(mmu_except_db[entry].err == mmu_err_val)
57                        break;
58
59                entry ++;
60        }
61 
62        return &mmu_except_db[entry];
63}
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