source: trunk/kernel/arch/tsar/mmu-info.h @ 1

Last change on this file since 1 was 1, checked in by alain, 5 years ago

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1/*
2 * mmu-info.h - TSAR MMU registers & exceptions related informations
3 *
4 * Copyright (c) 2008,2009,2010,2011,2012 Ghassan Almaless
5 * Copyright (c) 2011,2012 UPMC Sorbonne Universites
6 *
7 * This file is part of ALMOS-kernel.
8 *
9 * ALMOS-kernel is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2.0 of the License.
12 *
13 * ALMOS-kernel is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with ALMOS-kernel; if not, write to the Free Software Foundation,
20 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 */
22
23#ifndef _MMU_INFO_H_
24#define _MMU_INFO_H_
25
26#ifndef _USE_MMU_INFO_H_
27#error This file must not be used directly
28#endif
29
30/* MMU Registers Interface */
31#define MMU_PTPR                0       /* Page Table Pointer Register                R/W  */
32#define MMU_MODE                1       /* Mode Register                              R/W  */
33#define MMU_ICACHE_FLUSH        2       /* Instruction Cache flush                    W    */
34#define MMU_DCACHE_FLUSH        3       /* Data Cache flush                           W    */
35#define MMU_ITLB_INVAL          4       /* Instruction TLB line invalidation          W    */
36#define MMU_DTLB_INVAL          5       /* Data TLB line Invalidation                 W    */
37#define MMU_ICACHE_INVAL        6       /* Instruction Cache line invalidation        W    */
38#define MMU_DCACHE_INVAL        7       /* Data Cache line invalidation               W    */
39#define MMU_ICACHE_PREFETCH     8       /* Instruction Cache line prefetch            W    */
40#define MMU_DCACHE_PREFETCH     9       /* Data Cache line prefetch                   W    */
41#define MMU_SYNC                10      /* Complete pending writes                    W    */
42#define MMU_IETR                11      /* Instruction Exception Type Register        R    */
43#define MMU_DETR                12      /* Data Exception Type Register               R    */
44#define MMU_IBVAR               13      /* Instruction Bad Virtual Address Register   R    */
45#define MMU_DBVAR               14      /* Data Bad Virtual Address Register          R    */
46#define MMU_PARAMS              15      /* Caches & TLBs hardware parameters          R    */
47#define MMU_RELEASE             16      /* Generic MMU release number                 R    */
48#define MMU_WORD_LO             17      /* Lowest part of a double word               R/W  */
49#define MMU_WORD_HI             18      /* Highest part of a double word              R/W  */
50#define MMU_ICACHE_PA_INV       19      /* Instruction cache inval physical adressing W    */
51#define MMU_DCACHE_PA_INV       20      /* Data cache inval physical addressing       W    */
52#define MMU_DOUBLE_LL           21      /* Double word linked load                    W    */
53#define MMU_DOUBLE_SC           22      /* Double word store conditional              W    */ 
54
55#include <types.h>
56
57/* MMU Exception Descriptor */
58struct mmu_except_info_s
59{
60        uint_t err;
61        char *name;
62        char *info;
63        char *severty;
64};
65
66typedef struct mmu_except_info_s mmu_except_info_t;
67
68inline mmu_except_info_t* mmu_except_get_entry(uint_t mmu_err_val);
69
70#endif  /* _MMU_INFO_H_ */
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