source: trunk/kernel/devices/dev_mmc.h @ 1

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1/*
2 * dev_mmc.h - MMC (Generic L2 cache controller) device API definition.
3 *
4 * Authors   Alain Greiner  (2016)
5 *
6 * Copyright (c) UPMC Sorbonne Universites
7 *
8 * This file is part of ALMOS-MKH.
9 *
10 * ALMOS-MKH is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2.0 of the License.
13 *
14 * ALMOS-MKH is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with ALMOS-MKH; if not, write to the Free Software Foundation,
21 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24#ifndef _DEV_MMC_H_
25#define _DEV_MMC_H_
26
27#include <almos_config.h>
28#include <hal_types.h>
29#include <spinlock.h>
30
31/*****************************************************************************************
32 *     Generic L2 cache controller definition
33 *
34 * The MMC (Memory Cache Controller) device describes an internal peripheral,
35 * acting in all clusters containing a level 2 cache controller.
36 *
37 * It supports  five command types:
38 * - MMC_CC_INVAL   : invalidate all cache lines covering a given buffer in L2 cache.
39 * - MMC_CC_SYNC    : synchronize all cache lines covering a given buffer to L3 cache.
40 * - MMC_GET_ERROR  : return content of a given error signaling register.
41 * - MMC_SET_ERROR  : set a given error signaling register.
42 * - MMC_GET_INSTRU : return content of a given instrumentation register.
43 *
44 * As all L2 caches can be accessed by any thread running in any cluster, a calling
45 * thread must get exclusive access to the MMC configuration interface.
46 * As these operations consume few cycles, and access conflicts are expected to be
47 * rare events, the calling threads use a busy waiting strategy to get the device
48 * spinlock, do not register in the device waiting queue, and no server thread
49 * is used for this device.
50 ****************************************************************************************/
51 
52/******************************************************************************************
53 * This enum defines the various implementations of the generic MMC peripheral.
54 * It must be kept consistent with the define in arch_info.h file.
55 *****************************************************************************************/
56
57enum mmc_impl_e
58{
59    IMPL_MMC_TSR =   0,     
60}
61mmc_impl_t;
62
63/*****************************************************************************************
64 * This structure defines the (implementation independant) command pased to the driver.
65 * To have a fixed format, the arguments interpretation depends on the command type.
66 ****************************************************************************************/
67
68enum
69{
70    MMC_CC_INVAL   = 0,
71    MMC_CC_SYNC    = 1,
72    MMC_GET_ERROR  = 2,
73    MMC_SET_ERROR  = 3,
74    MMC_GET_INSTRU = 4,
75};
76
77typedef struct mmc_command_s
78{
79    xptr_t      dev_xp;     /*! extended pointer on the relevant MMC device descriptor  */
80    uint32_t    type;       /*! CC_INVAL / CC_SYNC / GET_ERROR / SET_ERROR / GET_INSTRU */
81    paddr_t     buf_paddr;  /*! buffer physical address          (used by INVAL/SYNC)   */
82    uint32_t    buf_size;   /*! buffer size in bytes             (used by INVAL/SYNC)   */
83    uint32_t    reg_index;  /*! register index in MMC peripheral (used by SET/GET)      */
84    uint32_t  * reg_ptr;    /*! local pointer on src/dst buffer  (used by SET/GET)      */
85    error_t     error;      /*! operation status (0 if success)                         */
86}
87mmc_command_t;
88
89/*****************************************************************************************
90 * This function initializes the driver specific fields in the generic MMC device
91 * descriptor, and the implementation specific driver.
92 * It must be executed once in any cluster containing an L2 cache.
93 *****************************************************************************************
94 * @ mmc_xp     : extended pointer on MMC device descriptor.
95 ****************************************************************************************/
96void dev_mmc_init( xptr_t  mmc_xp );
97
98/*****************************************************************************************
99 * This function invalidates all cache lines covering a memory buffer
100 * in the physical address space.
101 * It can be executed by any thread in any cluster, because it uses remote accesses
102 * to access both the MMC device descriptor, and the L2 cache configuration interface.
103 *****************************************************************************************
104 * @ buf_paddr  : buffer local physical addresse.
105 * @ buf_size   : buffer size (bytes).
106 * @ return 0 if success / return EINVAL if failure
107 ****************************************************************************************/
108error_t dev_mmc_inval( paddr_t   buf_paddr,
109                       uint32_t  buf_size );
110
111/*****************************************************************************************
112 * This function forces the L2 cache to synchronize the L3 cache for all cache lines
113 * covering a memory buffer in the physical address space.
114 * It can be executed by any thread in any cluster, because it uses remote accesses
115 * to access both the MMC device descriptor, and the L2 cache configuration interface.
116 *****************************************************************************************
117 * @ buf_paddr  : buffer local physical addresse.
118 * @ buf_size   : buffer size (bytes).
119 * @ return 0 if success / return EINVAL if failure
120 ****************************************************************************************/
121error_t dev_mmc_sync( paddr_t    buf_paddr,
122                      uint32_t   buf_size );
123                       
124/*****************************************************************************************
125 * This function set a value in one error signaling MMC register.
126 * It can be executed by any thread in any cluster, because it uses remote accesses
127 * to access the L2 cache instrumentation interface in any cluster.
128 *****************************************************************************************
129 * @ cxy     : MMC cluster identifier.
130 * @ index   : register index in MMC peripheral.
131 * @ wdata   : value to be written.
132 * @ return 0 if success / return EINVAL if failure
133 ****************************************************************************************/
134error_t dev_mmc_set_error( cxy_t    cxy,
135                           uint32_t index,
136                           uint32_t wdata );
137             
138/*****************************************************************************************
139 * This function returns the value contained in one error signaling MMC register.
140 * It can be executed by any thread in any cluster, because it uses remote accesses
141 * to access the L2 cache instrumentation interface in any cluster.
142 *****************************************************************************************
143 * @ cxy     : MMC cluster identifier.
144 * @ index   : error register index in MMC peripheral.
145 * @ rdata   : local pointer on buffer for returned value.
146 * @ return 0 if success / return EINVAL if failure
147 ****************************************************************************************/
148error_t dev_mmc_get_error( cxy_t      cxy,
149                           uint32_t   index, 
150                           uint32_t * rdata );
151             
152
153/*****************************************************************************************
154 * This function returns the value contained in one instrumentation MMC register.
155 * It can be executed by any thread in any cluster, because it uses remote accesses
156 * to access the L2 cache configuration interface in any cluster.
157 *****************************************************************************************
158 * @ cxy     : MMC cluster identifier.
159 * @ index   : instrumentation register index in MMC peripheral.
160 * @ rdata   : local pointer on buffer for returned value.
161 * @ return 0 if success / return EINVAL if failure
162 ****************************************************************************************/
163error_t dev_mmc_get_instrumentation( cxy_t      cxy,
164                                     uint32_t   index,
165                                     uint32_t * rdata );
166
167#endif  /* _DEV_MMC_H_ */
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