source: trunk/kernel/devices/dev_pic.h @ 372

Last change on this file since 372 was 279, checked in by alain, 5 years ago

1) Introduce independant command fields for the various devices in the thread descriptor.
2) Introduce a new dev_pic_enable_ipi() function in the generic PIC device
3) Fix two bugs identified by Maxime in the scheduler initialisation, and in the sched_select().
4) fix several bugs in the TSAR hal_kentry.S.
5) Introduce a third kgiet segment (besides kdata and kcode) in the TSAR bootloader.

File size: 12.5 KB
Line 
1/*
2 * dev_pic.h - PIC (Programmable Interrupt Controler) generic device API definition.
3 *
4 * Authors   Alain Greiner  (2016)
5 *
6 * Copyright (c) UPMC Sorbonne Universites
7 *
8 * This file is part of ALMOS-MKH.
9 *
10 * ALMOS-MKH is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2.0 of the License.
13 *
14 * ALMOS-MKH is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with ALMOS-MKH; if not, write to the Free Software Foundation,
21 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24#ifndef _DEV_PIC_H_
25#define _DEV_PIC_H_
26
27#include <kernel_config.h>
28#include <hal_types.h>
29
30/*****************************************************************************************
31 *     Generic Programmable Interrupt Controler definition
32 *
33 * The PIC generic device describes the the programmable hardware infrastructure used
34 * to route a given IRQ to a given core, in a given cluster, and to help the interrupt
35 * handler to select  and execute the relevant ISR (Interrupt Service Routine).
36 * It handles the four following types of interrupts:
37 *
38 * 1) EXT_IRQ (External IRQ) generated by the external (shared) peripherals.
39 * 2) INT_IRQ (Internal IRQ) generated by the internal (replicated) peripherals.
40 * 3) TIM_IRQ (Timer IRQ) generated by the timers (one timer per core).
41 * 4) IPI_IRQ (Inter Processor IRQ) generated by software (one IPI per core).
42 *
43 * In supported manycores architectures, the PIC device contains two types
44 * of hardware components:
45 * - the IOPIC is an external component, handling all external peripherals IRQs.
46 * - The LAPIC is an internal component, replicated in each cluster, handling local
47 *   peripherals IRQS, Timer IRQs and IPIs (inter-processor-interupts).
48 *
49 * The "source" device for each input IRQ to the external IOPIC component, is defined
50 * in the "arch_info" file, and registered in the "iopic_input" global variable
51 * at kernel initialization.
52 *
53 * The "source" device for each input IRQ to the replicated LAPIC components, is defined
54 * in the "arch_info" file, and stored in the "lapic_input" global variable
55 * at kernel initialization.
56 *
57 * The PIC device defines generic commands that can be used by each kernel instance,
58 * - to create in local cluster the PIC implementation specific interupt vector(s),
59 * - to bind a given IRQ (internal or external IRQ to a given core in the local cluster,
60 * - to configure and activate the TICK timer for a given core in the local cluster,
61 * - to allows the software to send an IPI to any core in any cluster.
62 * This API is detailed below, and must be implemented by all PIC implementations.
63 *
64 * In each cluster, a PIC implementation specific structure can be linked to the
65 * cluster manager or to the core descriptors to register the interrupt vectors
66 * used by the kernel to select the relevant ISR when an interrupt is received
67 * by a given core in a given cluster.
68 
69 * This PIC device does not execute itself I/O operations. It is just acting as a
70 * configurable interrupt router for I/O operation executed by other peripherals.
71 * Therefore, ALMOS-MKH does not use the PIC device waiting queue, does not creates
72 * a server thread for the PIC device, and does not register the command in the calling
73 * thread descriptor, but call directly the relevant driver function.
74 ****************************************************************************************/
75 
76/****  Forward declarations  ****/
77
78struct chdev_s;
79
80/*****************************************************************************************
81 * This defines the specific extension for the PIC chdev descriptor.
82 * It contains four function pointers on the four PIC command types,
83 * that must be implemented by all drivers.
84 ****************************************************************************************/
85
86typedef void   (bind_irq_t)     ( lid_t lid , struct chdev_s * src_chdev );   
87typedef void   (enable_irq_t)   ( lid_t lid , xptr_t src_chdev_xp );   
88typedef void   (disable_irq_t)  ( lid_t lid , xptr_t src_chdev_xp );   
89typedef void   (enable_timer_t) ( uint32_t period );   
90typedef void   (enable_ipi_t)   ( );   
91typedef void   (send_ipi_t)     ( cxy_t cxy , lid_t lid ); 
92typedef void   (extend_init_t)  ( uint32_t * lapic_base ); 
93 
94typedef struct pic_extend_s
95{
96    bind_irq_t      * bind_irq;      /*! pointer on the driver "bind_irq" function      */ 
97    enable_irq_t    * enable_irq;    /*! pointer on the driver "enable_irq" function    */ 
98    disable_irq_t   * disable_irq;   /*! pointer on the driver "disable_irq" function   */ 
99    enable_timer_t  * enable_timer;  /*! pointer on the driver "enable_timer" function  */
100    enable_timer_t  * enable_ipi;    /*! pointer on the driver "enable_ipi" function    */
101    send_ipi_t      * send_ipi;      /*! pointer on the driver "send_ipi" function      */
102    extend_init_t   * extend_init;   /*! pointer on the driver "init_extend" function   */
103}
104pic_extend_t;
105
106/*****************************************************************************************
107 * This structure defines the input IRQS for the external IOPIC controller, that is used
108 * by external peripherals (IOC, NIC, TXT, etc.) to signal completion of an I/O operation.
109 * It describes the hardware wiring of IRQs between external peripherals and the IOPIC,
110 * as each entry contains the input IRQ index in IOPIC.
111 * For a multi-channels peripheral, there is one chdev and one IRQ per channel.
112 * This structure is replicated in each cluster. It is allocated as a global variable
113 * in the kernel_init.c file.
114 *****************************************************************************************/
115
116typedef struct iopic_input_s
117{
118    uint32_t   txt[CONFIG_MAX_TXT_CHANNELS];
119    uint32_t   ioc[CONFIG_MAX_IOC_CHANNELS];
120    uint32_t   nic_rx[CONFIG_MAX_NIC_CHANNELS];
121    uint32_t   nic_tx[CONFIG_MAX_NIC_CHANNELS];
122    uint32_t   iob;
123}
124iopic_input_t;
125
126/******************************************************************************************
127 * This structure defines the input IRQS for the internal LAPIC controllers, that are used
128 * by internal peripherals IRQS (DMA, MMC) to signal completion of an I/O operation.
129 * It describes the hardware wiring of IRQs between internal peripherals and ICU,
130 * as each entry contains the input IRQ index in the LAPIC component.
131 * For a multi-channels peripheral, there is one chdev and one IRQ per channel.
132 * This structure is replicated in each cluster. It is allocated as a global variable
133 * in the kernel_init.c file.
134 *****************************************************************************************/
135
136typedef struct lapic_input_s
137{
138    uint32_t   dma[CONFIG_MAX_DMA_CHANNELS];
139    uint32_t   mmc;                             // MMC is single channel
140}
141lapic_input_t;
142
143/*****************************************************************************************
144 * This enum defines the various implementations of the PIC device.
145 * This array must be kept consistent with the define in arch_info.h file
146 ****************************************************************************************/
147
148enum pic_impl_e
149{
150    IMPL_PIC_SCL =   0,     
151    IMPL_PIC_I86 =   1,
152}
153pic_impl_t;
154
155/*****************************************************************************************
156 * This function makes two initialisations :
157 * - It initializes the PIC specific fields of the chdev descriptor.
158 * - it initializes the implementation specific PIC hardware registers.
159 * It is executed once in cluster containing the PIC chdev, during kernel initialisation.
160 * The calling core goes to sleep in case of failure.
161 *****************************************************************************************
162 * @ pic        : local pointer on PIC device descriptor.
163 ****************************************************************************************/
164void dev_pic_init( struct chdev_s * pic );
165
166/*****************************************************************************************
167 * This function completes the PIC infrastructure initialisation in each cluster.
168 * It allocates memory for the local PIC extensions in the core descriptors and/or
169 * in the cluster manager, as required by the specific PIC implementation.
170 * This function is called by CPO in all clusters, during kernel initialisation phase.
171 * The calling core goes to sleep in case of failure.
172 *****************************************************************************************
173 * @ lapic_base  : local pointer on LAPIC component segment base.
174 ****************************************************************************************/
175void dev_pic_extend_init( uint32_t * lapic_base );
176
177/*****************************************************************************************
178 * This function configure the PIC device to route the IRQ generated by a local chdev,
179 * defined by the <src_chdev> argument, to a local core identified by the <lid> argument.
180 * This is a static binding, defined during kernel init: IRQ can be enabled/disabled,
181 * but the binding cannot be released. It can be used for both internal & external IRQs.
182 * WARNING : the IRQ must be explicitely enabled by the dev_pic_enable_irq() function.
183 *****************************************************************************************
184 * @ lid        : target core local index.
185 * @ src_chdev  : local pointer on source chdev descriptor.
186 ****************************************************************************************/
187void dev_pic_bind_irq( lid_t            lid,
188                       struct chdev_s * src_chdev );
189
190/*****************************************************************************************
191 * This function enables the IRQ generated by a remote chdev, defined by the
192 * <src_chdev_xp> argument. It can be called by any thread running in any cluster,
193 * and can be used for both internal & external IRQs.
194 *****************************************************************************************
195 * @ lid           : target core local index (in cluster containing the source chdev).
196 * @ src_chdev_xp  : extended  pointer on source chdev descriptor.
197 ****************************************************************************************/
198void dev_pic_enable_irq( lid_t   lid,
199                         xptr_t  src_chdev_xp );
200
201/*****************************************************************************************
202 * This function disables remote IRQ generated by a remote chdev, defined by the
203 * <src_chdev_xp> argument. It can be called by any thread running in any cluster,
204 * and can be used for both INT_IRq & EXT_IRQ.
205 *****************************************************************************************
206 * @ lid           : target core local index (in cluster containing the source chdev).
207 * @ src_chdev_xp  : extended pointer on sour chdev descriptor.
208 ****************************************************************************************/
209void dev_pic_disable_irq( lid_t   lid,
210                          xptr_t  src_chdev_xp );
211
212/*****************************************************************************************
213 * This function activates the TIM_IRQ for the calling core.
214 * The <period> argument define the number of cycles between twoo successive IRQs.
215 *****************************************************************************************
216 * @ period      : number of cycles between IRQs.
217 ****************************************************************************************/
218void dev_pic_enable_timer( uint32_t period );
219
220/*****************************************************************************************
221 * This function activates the IPI_IRQ for the calling core.
222 ****************************************************************************************/
223void dev_pic_enable_ipi();
224
225/*****************************************************************************************
226 * This function allows the calling thread to send an IPI to any core in any cluster.
227 * The target core is identified by the <cxy> & <lid> arguments.
228 *****************************************************************************************
229 * @ cxy        : target core cluster.
230 * @ lid        : target core local index.
231 ****************************************************************************************/
232void dev_pic_send_ipi( cxy_t  cxy,
233                       lid_t  lid );
234
235
236#endif  /* _DEV_PIC_H_ */
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