source: trunk/kernel/drivers/ibmpc/pci-bus.h @ 1

Last change on this file since 1 was 1, checked in by alain, 5 years ago

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1/*
2 * pci.c - PCI bus related registers and access functions
3 *
4 * Copyright (c) 2008,2009,2010,2011,2012 Ghassan Almaless
5 * Copyright (c) 2011,2012 UPMC Sorbonne Universites
6 *
7 * This file is part of ALMOS-kernel.
8 *
9 * ALMOS-kernel is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2.0 of the License.
12 *
13 * ALMOS-kernel is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with ALMOS-kernel; if not, write to the Free Software Foundation,
20 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 */
22
23#ifndef _PCI_BUS_H_
24#define _PCI_BUS_H_
25
26#include <types.h>
27#include <cpu-io.h>
28
29#define PCI_TGT_MAX_CONFIG_SPACE      256
30#define PCI_TGT_MAX_CONFIG_REG        64
31#define PCI_BUS_MAX_NR                255
32#define PCI_BUS_DEV_MAX_NR            32
33#define PCI_DEV_FUNC_MAX_NR           8
34
35#define PCI_CONFIG_ADDR               0xCF8
36#define PCI_CONFIG_DATA               0xCFC
37
38#define PCI_STD_DEV_TYPE              0x00
39#define PCI_BRIDGE_TYPE               0x01
40#define PCI_CARDBUS_BRIDGE_TYPE       0x02
41
42#define PCI_VENDOR_ID                 0x00
43#define PCI_DEVCIE_ID                 0x02
44#define PCI_CMD_REG                   0x04
45#define PCI_STATUS_REG                0x06
46#define PCI_REVISION_ID               0x08
47
48#define PCI_CLASS_ID                  0x0A
49#define PCI_HEADER_TYPE               0x0E
50
51#define PCI_BAR0                      0x10
52#define PCI_BAR1                      0x14
53#define PCI_BAR2                      0x18
54#define PCI_BAR3                      0x1C
55#define PCI_BAR4                      0x20
56#define PCI_BAR5                      0x24
57
58#define PCI_INT_INFO 0x3C
59
60#define pci_mkconfig1_addr(_bus,_dev,_func,_offset)     \
61        ((uint32_t)(0x80000000    | ((_bus) << 16) |    \
62                    ((_dev) << 11) | ((_func) << 8) |   \
63                    ((_offset) & 0xfc)))
64
65
66static inline uint16_t pci_config_read(uint_t bus, uint_t slot, uint_t func, uint_t offset)
67{ 
68        uint32_t addr;
69        uint32_t val; 
70
71        addr = pci_mkconfig1_addr(bus,slot,func,offset);
72
73        cpu_io_out32(PCI_CONFIG_ADDR, addr);
74        val = cpu_io_in32(PCI_CONFIG_DATA);
75
76        return val >> ((offset & 3) * 8);
77}
78
79#endif  /* _PCI_BUS_H_ */
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