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defBF52x_base.h @ 444

Last change on this file since 444 was 444, checked in by satin@…, 6 years ago
add newlib,libalmos-mkh, restructure shared_syscalls.h and mini-libc
File size: 118.9 KB

Line
1	/*
2	* The authors hereby grant permission to use, copy, modify, distribute,
3	* and license this software and its documentation for any purpose, provided
4	* that existing copyright notices are retained in all copies and that this
5	* notice is included verbatim in any distributions. No written agreement,
6	* license, or royalty fee is required for any of the authorized uses.
7	* Modifications to this software may be copyrighted by their authors
8	* and need not follow the licensing terms described here, provided that
9	* the new terms are clearly indicated on the first page of each file where
10	* they apply.
11	*/
12
13	/*
14	** defBF52x_base.h
15	**
16	** Copyright (C) 2007-2009 Analog Devices Inc., All Rights Reserved.
17	**
18	************************************************************************************
19	**
20	** This include file contains a list of macro "defines" to enable the programmer
21	** to use symbolic names for the registers common to the ADSP-BF52x peripherals.
22	**
23	************************************************************************************
24	** System MMR Register Map
25	************************************************************************************/
26
27	#ifndef _DEF_BF52X_H
28	#define _DEF_BF52X_H
29
30	#ifdef _MISRA_RULES
31	#pragma diag(push)
32	#pragma diag(suppress:misra_rule_19_4)
33	#pragma diag(suppress:misra_rule_19_7)
34	#include <stdint.h>
35	#endif /* _MISRA_RULES */
36
37
38	/* ************************************************************** */
39	/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x */
40	/* ************************************************************** */
41
42	/* ==== begin from defBF534.h ==== */
43
44	/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
45	#define PLL_CTL 0xFFC00000 /* PLL Control Register */
46	#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
47	#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
48	#define PLL_STAT 0xFFC0000C /* PLL Status Register */
49	#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
50	#define CHIPID 0xFFC00014 /* Device ID Register */
51
52
53	/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
54	#define SWRST 0xFFC00100 /* Software Reset Register */
55	#define SYSCR 0xFFC00104 /* System Configuration Register */
56
57	#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
58	/* legacy register name (below) provided for backwards code compatibility */
59	#define SIC_IMASK SIC_IMASK0
60
61	#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
62	#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
63	#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
64	#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
65
66	#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
67	/* legacy register name (below) provided for backwards code compatibility */
68	#define SIC_ISR SIC_ISR0
69
70	#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
71	/* legacy register name (below) provided for backwards code compatibility */
72	#define SIC_IWR SIC_IWR0
73
74	/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
75	#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
76	#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */
77	#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */
78	#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */
79	#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */
80	#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */
81	#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */
82
83
84	/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
85	#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
86	#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
87	#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
88
89
90	/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
91	#define RTC_STAT 0xFFC00300 /* RTC Status Register */
92	#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
93	#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
94	#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
95	#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
96	#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
97	#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
98
99
100	/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
101	#define UART0_THR 0xFFC00400 /* Transmit Holding register */
102	#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
103	#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
104	#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
105	#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
106	#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
107	#define UART0_LCR 0xFFC0040C /* Line Control Register */
108	#define UART0_MCR 0xFFC00410 /* Modem Control Register */
109	#define UART0_LSR 0xFFC00414 /* Line Status Register */
110	#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
111	#define UART0_GCTL 0xFFC00424 /* Global Control Register */
112
113
114	/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
115	#define SPI_CTL 0xFFC00500 /* SPI Control Register */
116	#define SPI_FLG 0xFFC00504 /* SPI Flag register */
117	#define SPI_STAT 0xFFC00508 /* SPI Status register */
118	#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
119	#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
120	#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
121	#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
122
123
124	/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
125	#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
126	#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
127	#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
128	#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
129
130	#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
131	#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
132	#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
133	#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
134
135	#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
136	#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
137	#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
138	#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
139
140	#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
141	#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
142	#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
143	#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
144
145	#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
146	#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
147	#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
148	#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
149
150	#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
151	#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
152	#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
153	#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
154
155	#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
156	#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
157	#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
158	#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
159
160	#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
161	#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
162	#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
163	#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
164
165	#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
166	#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
167	#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
168
169
170	/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
171	#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
172	#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
173	#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
174	#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
175	#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
176	#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
177	#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
178	#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
179	#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
180	#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
181	#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
182	#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
183	#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
184	#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
185	#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
186	#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
187	#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
188
189
190	/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
191	#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
192	#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
193	#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
194	#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
195	#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
196	#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
197	#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
198	#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
199	#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
200	#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
201	#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
202	#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
203	#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
204	#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
205	#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
206	#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
207	#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
208	#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
209	#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
210	#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
211	#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
212	#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
213
214
215	/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
216	#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
217	#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
218	#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
219	#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
220	#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
221	#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
222	#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
223	#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
224	#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
225	#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
226	#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
227	#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
228	#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
229	#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
230	#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
231	#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
232	#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
233	#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
234	#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
235	#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
236	#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
237	#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
238
239
240	/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
241	#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
242	#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
243	#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
244	#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
245	#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
246	#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
247	#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
248
249
250	/* DMA Traffic Control Registers */
251	#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
252	#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
253
254	/* Alternate deprecated register names (below) provided for backwards code compatibility */
255	#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
256	#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
257
258	/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
259	#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
260	#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
261	#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
262	#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
263	#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
264	#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
265	#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
266	#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
267	#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
268	#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
269	#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
270	#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
271	#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
272
273	#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
274	#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
275	#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
276	#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
277	#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
278	#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
279	#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
280	#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
281	#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
282	#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
283	#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
284	#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
285	#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
286
287	#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
288	#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
289	#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
290	#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
291	#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
292	#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
293	#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
294	#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
295	#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
296	#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
297	#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
298	#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
299	#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
300
301	#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
302	#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
303	#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
304	#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
305	#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
306	#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
307	#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
308	#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
309	#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
310	#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
311	#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
312	#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
313	#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
314
315	#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
316	#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
317	#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
318	#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
319	#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
320	#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
321	#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
322	#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
323	#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
324	#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
325	#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
326	#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
327	#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
328
329	#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
330	#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
331	#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
332	#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
333	#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
334	#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
335	#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
336	#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
337	#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
338	#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
339	#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
340	#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
341	#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
342
343	#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
344	#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
345	#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
346	#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
347	#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
348	#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
349	#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
350	#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
351	#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
352	#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
353	#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
354	#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
355	#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
356
357	#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
358	#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
359	#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
360	#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
361	#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
362	#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
363	#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
364	#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
365	#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
366	#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
367	#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
368	#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
369	#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
370
371	#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
372	#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
373	#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
374	#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
375	#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
376	#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
377	#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
378	#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
379	#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
380	#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
381	#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
382	#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
383	#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
384
385	#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
386	#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
387	#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
388	#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
389	#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
390	#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
391	#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
392	#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
393	#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
394	#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
395	#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
396	#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
397	#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
398
399	#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
400	#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
401	#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
402	#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
403	#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
404	#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
405	#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
406	#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
407	#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
408	#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
409	#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
410	#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
411	#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
412
413	#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
414	#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
415	#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
416	#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
417	#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
418	#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
419	#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
420	#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
421	#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
422	#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
423	#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
424	#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
425	#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
426
427	#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
428	#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
429	#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
430	#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
431	#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
432	#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
433	#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
434	#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
435	#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
436	#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
437	#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
438	#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
439	#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
440
441	#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
442	#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
443	#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
444	#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
445	#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
446	#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
447	#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
448	#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
449	#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
450	#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
451	#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
452	#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
453	#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
454
455	#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
456	#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
457	#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
458	#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
459	#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
460	#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
461	#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
462	#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
463	#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
464	#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
465	#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
466	#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
467	#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
468
469	#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
470	#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
471	#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
472	#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
473	#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
474	#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
475	#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
476	#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
477	#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
478	#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
479	#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
480	#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
481	#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
482
483
484	/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
485	#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
486	#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
487	#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
488	#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
489	#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
490
491
492	/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
493	#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
494	#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
495	#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
496	#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
497	#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
498	#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
499	#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
500	#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
501	#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
502	#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
503	#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
504	#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
505	#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
506	#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
507	#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
508	#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
509
510
511	/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
512	#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
513	#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
514	#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
515	#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
516	#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
517	#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
518	#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
519	#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
520	#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
521	#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
522	#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
523	#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
524	#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
525	#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
526	#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
527	#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
528	#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
529
530
531	/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
532	#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
533	#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
534	#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
535	#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
536	#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
537	#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
538	#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
539	#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
540	#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
541	#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
542	#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
543	#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
544	#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
545	#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
546	#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
547	#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
548	#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
549
550
551	/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
552	#define UART1_THR 0xFFC02000 /* Transmit Holding register */
553	#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
554	#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
555	#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
556	#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
557	#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
558	#define UART1_LCR 0xFFC0200C /* Line Control Register */
559	#define UART1_MCR 0xFFC02010 /* Modem Control Register */
560	#define UART1_LSR 0xFFC02014 /* Line Status Register */
561	#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
562	#define UART1_GCTL 0xFFC02024 /* Global Control Register */
563
564
565	/* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */
566
567	/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
568	#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag) /
569	#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag) /
570	#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag) /
571
572
573	/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
574	#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
575	#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
576	#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
577	#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
578	#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
579	#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
580	#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
581
582	#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
583	#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
584	#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
585	#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
586	#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
587	#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
588	#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
589
590	/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
591	#define PORTF_MUX 0xFFC03210 /* Port F mux control */
592	#define PORTG_MUX 0xFFC03214 /* Port G mux control */
593	#define PORTH_MUX 0xFFC03218 /* Port H mux control */
594	#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
595	#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
596	#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
597	#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */
598	#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */
599	#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */
600	#define NONGPIO_DRIVE 0xFFC03280 /* Drive strength control for non-GPIO pins */
601	#define NONGPIO_HYSTERESIS 0xFFC03288 /* Schmitt trigger control for non-GPIO pins */
602
603	/***********************************************************************************
604	** System MMR Register Bits And Macros
605	**
606	** Disclaimer: All macros are intended to make C and Assembly code more readable.
607	** Use these macros carefully, as any that do left shifts for field
608	** depositing will result in the lower order bits being destroyed. Any
609	** macro that shifts left to properly position the bit-field should be
610	** used as part of an OR to initialize a register and NOT as a dynamic
611	** modifier UNLESS the lower order bits are saved and ORed back in when
612	** the macro is used.
613	*************************************************************************************/
614	/*
615	***************** PLL AND RESET MASKS **************************************/
616	/* PLL_CTL Masks */
617	#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
618	#define PLL_OFF 0x0002 /* PLL Not Powered */
619	#define STOPCK 0x0008 /* Core Clock Off */
620	#define PDWN 0x0020 /* Enter Deep Sleep Mode */
621	#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
622	#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
623	#define BYPASS 0x0100 /* Bypass the PLL */
624	#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
625	/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
626	#ifdef _MISRA_RULES
627	#define SET_MSEL(x) (((x)&0x3Fu) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKINMSEL /
628	#else
629	#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKINMSEL /
630	#endif /* _MISRA_RULES */
631
632	/* PLL_DIV Masks */
633	#define SSEL 0x000F /* System Select */
634	#define CSEL 0x0030 /* Core Select */
635	#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
636	#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
637	#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
638	#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
639	/* PLL_DIV Macros */
640	#ifdef _MISRA_RULES
641	#define SET_SSEL(x) ((x)&0xFu) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
642	#else
643	#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
644	#endif /* _MISRA_RULES */
645
646	/* VR_CTL Masks */
647	#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */
648	#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
649
650	#define VLEV 0x00F0 /* Internal Voltage Level - Only Program Values Within Specifications */
651	#define VLEV_085 0x0040 /* VLEV = 0.85 V (See Datasheet for Regulator Tolerance) */
652	#define VLEV_090 0x0050 /* VLEV = 0.90 V (See Datasheet for Regulator Tolerance) */
653	#define VLEV_095 0x0060 /* VLEV = 0.95 V (See Datasheet for Regulator Tolerance) */
654	#define VLEV_100 0x0070 /* VLEV = 1.00 V (See Datasheet for Regulator Tolerance) */
655	#define VLEV_105 0x0080 /* VLEV = 1.05 V (See Datasheet for Regulator Tolerance) */
656	#define VLEV_110 0x0090 /* VLEV = 1.10 V (See Datasheet for Regulator Tolerance) */
657	#define VLEV_115 0x00A0 /* VLEV = 1.15 V (See Datasheet for Regulator Tolerance) */
658	#define VLEV_120 0x00B0 /* VLEV = 1.20 V (See Datasheet for Regulator Tolerance) */
659
660	#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
661	#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */
662	#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
663	#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
664	#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
665	#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
666
667	/* PLL_STAT Masks */
668	#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
669	#define FULL_ON 0x0002 /* Processor In Full On Mode */
670	#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
671	#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
672	#define VSTAT 0x0080 /* Voltage Regulator Status: Regulator at programmed voltage */
673
674	/* SWRST Masks */
675	#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
676	#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
677	#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
678	#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
679	#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
680
681	/* SYSCR Masks */
682
683	#define BMODE_BYPASS 0x0000 /* Bypass boot ROM, execute from 16-bit external memory */
684	#define BMODE_FLASH 0x0001 /* Use Boot ROM to load from 8-bit or 16-bit flash */
685	#define BMODE_SPIMEM 0x0003 /* Boot from serial SPI memory */
686	#define BMODE_SPIHOST 0x0004 /* Boot from SPI0 host (slave mode) */
687	#define BMODE_TWIMEM 0x0005 /* Boot from serial TWI memory */
688	#define BMODE_TWIHOST 0x0006 /* Boot from TWI0 host (slave mode) */
689	#define BMODE_UART0HOST 0x0007 /* Boot from UART0 host */
690	#define BMODE_UART1HOST 0x0008 /* Boot from UART1 host */
691	#define BMODE_SDRAMMEM 0x000A /* Boot from SDRAM memory (warm boot) */
692	#define BMODE_OTPMEM 0x000B /* Boot from OTP memory */
693	#define BMODE_HOSTDMA_ACK 0x000E /* Boot from 16-bit host DMA (ACK mode) */
694	#define BMODE_HOSTDMA_INT 0x000F /* Boot from 8-bit host DMA (INT mode) */
695	#define BMODE 0x000F /* Boot Mode. Mirror of BMODE Mode Pins */
696
697	#define BCODE 0x00F0
698	#define BCODE_NORMAL 0x0000 /* normal boot, update PLL/VR, quickboot as by WURESET */
699	#define BCODE_NOBOOT 0x0010 /* bypass boot, don't update PLL/VR */
700	#define BCODE_QUICKBOOT 0x0020 /* quick boot, overrule WURESET, don't update PLL/VR */
701	#define BCODE_ALLBOOT 0x0040 /* no quick boot, overrule WURESET, don't update PLL/VR */
702	#define BCODE_FULLBOOT 0x0060 /* no quick boot, overrule WURESET, update PLL/VR */
703
704	#define DCB1_PRIO 0x0100 /* DCB1 requests are urgent */
705	#define DCB_ROT_PRIO 0x0200 /* enable rotating DCB priority */
706	#define DEB1_PRIO 0x0400 /* DEB1 requests are urgent */
707	#define DEB_ROT_PRIO 0x0800 /* enable rotating DEB priority */
708
709	#define WURESET 0x1000 /* wakeup event since last hardware reset */
710	#define DFRESET 0x2000 /* recent reset was due to a double fault event */
711	#define WDRESET 0x4000 /* recent reset was due to a watchdog event */
712	#define SWRESET 0x8000 /* recent reset was issued by software */
713
714	/* *********** SYSTEM INTERRUPT CONTROLLER MASKS ***********************************/
715	/* Peripheral Masks For SIC_ISR0, SIC_IWR0, SIC_IMASK0 */
716	#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
717
718	#define IRQ_DMA_ERR0 0x00000002 /* Error Interrupt (DMA error 0 interrupt (generic)) */
719	#define IRQ_DMAR0 0x00000004 /* DMAR0 Block (DMAR0 block interrupt) */
720	#define IRQ_DMAR1 0x00000008 /* DMAR1 Block (DMAR1 block interrupt) */
721	#define IRQ_DMAR0_ERR 0x00000010 /* Error Interrupt (DMAR0 overflow error interrupt) */
722	#define IRQ_DMAR1_ERR 0x00000020 /* Error Interrupt (DMAR1 overflow error interrupt) */
723	#define IRQ_PPI_ERR 0x00000040 /* Error Interrupt (PPI error interrupt) */
724	#define IRQ_MAC_ERR 0x00000080 /* Error Interrupt (MAC status interrupt) */
725	#define IRQ_SPORT0_ERR 0x00000100 /* Error Interrupt (SPORT0 status interrupt) */
726	#define IRQ_SPORT1_ERR 0x00000200 /* Error Interrupt (SPORT1 status interrupt) */
727	#define IRQ_UART0_ERR 0x00001000 /* Error Interrupt (UART0 status interrupt) */
728	#define IRQ_UART1_ERR 0x00002000 /* Error Interrupt (UART1 status interrupt) */
729	#define IRQ_RTC 0x00004000 /* Real Time Clock Interrupt */
730	#define IRQ_DMA0 0x00008000 /* DMA channel 0 (PPI/NFC) Interrupt */
731	#define IRQ_DMA3 0x00010000 /* DMA Channel 3 (SPORT0 RX) Interrupt */
732	#define IRQ_DMA4 0x00020000 /* DMA Channel 4 (SPORT0 TX) Interrupt */
733	#define IRQ_DMA5 0x00040000 /* DMA Channel 5 (SPORT1 RX) Interrupt */
734	#define IRQ_DMA6 0x00080000 /* DMA Channel 6 (SPORT1 TX) Interrupt */
735	#define IRQ_TWI 0x00100000 /* TWI Interrupt */
736	#define IRQ_DMA7 0x00200000 /* DMA Channel 7 (SPI) Interrupt */
737	#define IRQ_DMA8 0x00400000 /* DMA Channel 8 (UART0 RX) Interrupt */
738	#define IRQ_DMA9 0x00800000 /* DMA Channel 9 (UART0 TX) Interrupt */
739	#define IRQ_DMA10 0x01000000 /* DMA Channel 10 (UART1 RX) Interrupt */
740	#define IRQ_DMA11 0x02000000 /* DMA Channel 11 (UART1 TX) Interrupt */
741	#define IRQ_OTP 0x04000000 /* OTP Interrupt */
742	#define IRQ_CNT 0x08000000 /* GP Counter Interrupt */
743	#define IRQ_DMA1 0x10000000 /* DMA Channel 1 (EthernetRX/HOSTDP) Interrupt */
744	#define IRQ_PFA_PORTH 0x20000000 /* PF Port H Interrupt A */
745	#define IRQ_DMA2 0x40000000 /* DMA Channel 2 (Ethernet TX/NFC) Interrupt */
746	#define IRQ_PFB_PORTH 0x80000000 /* PF Port H Interrupt B */
747
748	/* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1 */
749
750	#define IRQ_TIMER0 0x00000001 /* Timer 0 Interrupt */
751	#define IRQ_TIMER1 0x00000002 /* Timer 1 Interrupt */
752	#define IRQ_TIMER2 0x00000004 /* Timer 2 Interrupt */
753	#define IRQ_TIMER3 0x00000008 /* Timer 3 Interrupt */
754	#define IRQ_TIMER4 0x00000010 /* Timer 4 Interrupt */
755	#define IRQ_TIMER5 0x00000020 /* Timer 5 Interrupt */
756	#define IRQ_TIMER6 0x00000040 /* Timer 6 Interrupt */
757	#define IRQ_TIMER7 0x00000080 /* Timer 7 Interrupt */
758	#define IRQ_PFA_PORTG 0x00000100 /* PF Port G Interrupt A */
759	#define IRQ_PFB_PORTG 0x00000200 /* PF Port G Interrupt B */
760	#define IRQ_DMA12 0x00000400 /* DMA Channels 12 (MDMA0 Destination) TX Interrupt */
761	#define IRQ_DMA13 0x00000400 /* DMA Channels 13 (MDMA0 Source) RX Interrupt */
762	#define IRQ_DMA14 0x00000800 /* DMA Channels 14 (MDMA1 Destination) TX Interrupt */
763	#define IRQ_DMA15 0x00000800 /* DMA Channels 15 (MDMA1 Source) RX Interrupt */
764	#define IRQ_WDOG 0x00001000 /* Software Watchdog Timer Interrupt */
765	#define IRQ_PFA_PORTF 0x00002000 /* PF Port F Interrupt A */
766	#define IRQ_PFB_PORTF 0x00004000 /* PF Port F Interrupt B */
767	#define IRQ_SPI_ERR 0x00008000 /* Error Interrupt (SPI status interrupt) */
768	#define IRQ_NAND_ERR 0x00010000 /* NAND error interrupt */
769	#define IRQ_HOSTDP_STATUS 0x00020000 /* HOSTDP status interrupt */
770	#define IRQ_HOSTRD_DONE 0x00040000 /* Host Read Done interrupt */
771	#define IRQ_USB_EINT 0x00080000 /* USB EINT interrupt */
772	#define IRQ_USB_INT0 0x00100000 /* USB INT0 interrupt */
773	#define IRQ_USB_INT1 0x00200000 /* USB INT1 interrupt */
774	#define IRQ_USB_INT2 0x00400000 /* USB INT1 interrupt */
775	#define IRQ_USB_DMAINT 0x00800000 /* USB DMAINT interrupt */
776
777	/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
778	#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
779	#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
780	/* x = pos 0 to 31, for 32-63 use value-32 */
781	#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
782	#ifdef _MISRA_RULES
783	#define IWR_DISABLE(x) (0xFFFFFFFFu^(1<<(x)))/* Wakeup Disable Peripheral #x */
784	#else
785	#define IWR_DISABLE(x) (0xFFFFFFFF^(1<<(x)))/* Wakeup Disable Peripheral #x */
786	#endif /* _MISRA_RULES */
787
788
789	#ifdef _MISRA_RULES
790	#define _MF15 0xFu
791	#define _MF7 7u
792	#else
793	#define _MF15 0xF
794	#define _MF7 7
795	#endif /* _MISRA_RULES */
796
797	/* SIC_IAR0 Macros */
798	#define P0_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #0 assigned IVG #x */
799	#define P1_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #1 assigned IVG #x */
800	#define P2_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #2 assigned IVG #x */
801	#define P3_IVG(x) ((((x)&_MF15)-_MF7) << 0xC) /* Peripheral #3 assigned IVG #x */
802	#define P4_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #4 assigned IVG #x */
803	#define P5_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #5 assigned IVG #x */
804	#define P6_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #6 assigned IVG #x */
805	#define P7_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #7 assigned IVG #x */
806
807	/* SIC_IAR1 Macros */
808	#define P8_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #8 assigned IVG #x */
809	#define P9_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #9 assigned IVG #x */
810	#define P10_IVG(x) /* Reserved */
811	#define P11_IVG(x) /* Reserved */
812	#define P12_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #12 assigned IVG #x */
813	#define P13_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #13 assigned IVG #x */
814	#define P14_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #14 assigned IVG #x */
815	#define P15_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #15 assigned IVG #x */
816
817	/* SIC_IAR2 Macros */
818	#define P16_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #16 assigned IVG #x */
819	#define P17_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #17 assigned IVG #x */
820	#define P18_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #18 assigned IVG #x */
821	#define P19_IVG(x) ((((x)&_MF15)-_MF7) << 0xC) /* Peripheral #19 assigned IVG #x */
822	#define P20_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #20 assigned IVG #x */
823	#define P21_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #21 assigned IVG #x */
824	#define P22_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #22 assigned IVG #x */
825	#define P23_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #23 assigned IVG #x */
826
827	/* SIC_IAR3 Macros */
828	#define P24_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #24 assigned IVG #x */
829	#define P25_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #25 assigned IVG #x */
830	#define P26_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #26 assigned IVG #x */
831	#define P27_IVG(x) ((((x)&_MF15)-_MF7) << 0xC) /* Peripheral #27 assigned IVG #x */
832	#define P28_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #28 assigned IVG #x */
833	#define P29_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #29 assigned IVG #x */
834	#define P30_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #30 assigned IVG #x */
835	#define P31_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #31 assigned IVG #x */
836
837	/* SIC_IAR4 Macros */
838	#define P32_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #32 assigned IVG #x */
839	#define P33_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #33 assigned IVG #x */
840	#define P34_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #34 assigned IVG #x */
841	#define P35_IVG(x) ((((x)&_MF15)-_MF7) << 0xC) /* Peripheral #35 assigned IVG #x */
842	#define P36_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #36 assigned IVG #x */
843	#define P37_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #37 assigned IVG #x */
844	#define P38_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #38 assigned IVG #x */
845	#define P39_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #39 assigned IVG #x */
846
847	/* SIC_IAR5 Macros */
848	#define P40_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #40 assigned IVG #x */
849	#define P41_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #41 assigned IVG #x */
850	#define P42_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #42 assigned IVG #x */
851	#define P43_IVG(x) ((((x)&_MF15)-_MF7) << 0xC) /* Peripheral #43 assigned IVG #x */
852	#define P44_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #44 assigned IVG #x */
853	#define P45_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #45 assigned IVG #x */
854	#define P46_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #46 assigned IVG #x */
855	#define P47_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #47 assigned IVG #x */
856
857	/* SIC_IAR6 Macros */
858	#define P48_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #48 assigned IVG #x */
859	#define P49_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #49 assigned IVG #x */
860	#define P50_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #50 assigned IVG #x */
861	#define P51_IVG(x) /* Reserved */
862	#define P52_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #52 assigned IVG #x */
863	#define P53_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #53 assigned IVG #x */
864	#define P54_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #54 assigned IVG #x */
865	#define P55_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #55 assigned IVG #x */
866
867	/* SIC_IAR7 Macros */
868	#define P56_IVG(x) /* Reserved */
869	#define P57_IVG(x) /* Reserved */
870	#define P58_IVG(x) /* Reserved */
871	#define P59_IVG(x) /* Reserved */
872	#define P60_IVG(x) /* Reserved */
873	#define P61_IVG(x) /* Reserved */
874	#define P62_IVG(x) /* Reserved */
875	#define P63_IVG(x) /* Reserved */
876
877
878	/* SIC_IMASK0 Masks*/
879	#define SIC_UNMASK0_ALL 0x00000000 /* Unmask all peripheral interrupts */
880	#define SIC_MASK0_ALL 0xFFFFF3FF /* Mask all peripheral interrupts */
881	#ifdef _MISRA_RULES
882	#define SIC_MASK0(x) ((int32_t)1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
883	#define SIC_UNMASK0(x) (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu))) /Unmask Peripheral #x interrupt/
884	#else
885	#define SIC_MASK0(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
886	#define SIC_UNMASK0(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
887	#endif /* _MISRA_RULES */
888
889	/* SIC_IMASK1 Masks*/
890	#define SIC_UNMASK1_ALL 0x00000000 /* Unmask all peripheral interrupts */
891	#define SIC_MASK1_ALL 0xFFFFFF /* Mask all peripheral interrupts */
892	#ifdef _MISRA_RULES
893	#define SIC_MASK1(x) ((int32_t)1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
894	#define SIC_UNMASK1(x) (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu))) /Unmask Peripheral #x interrupt/
895	#else
896	#define SIC_MASK1(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
897	#define SIC_UNMASK1(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
898	#endif /* _MISRA_RULES */
899
900
901	/* SIC_IWR0 Masks*/
902	#define IWR0_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
903	#define IWR0_ENABLE_ALL 0xFFFFF3FF /* Wakeup Enable all peripherals */
904	#ifdef _MISRA_RULES
905	#define IWR0_ENABLE(x) ((int32_t)1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
906	#define IWR0_DISABLE(x) (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu))) /Wakeup Disable Peripheral #x /
907	#else
908	#define IWR0_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
909	#define IWR0_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
910	#endif /* _MISRA_RULES */
911
912	/* SIC_IWR1 Masks*/
913	#define IWR1_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
914	#define IWR1_ENABLE_ALL 0xFFFFFF /* Wakeup Enable all peripherals */
915	#ifdef _MISRA_RULES
916	#define IWR1_ENABLE(x) ((int32_t)1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
917	#define IWR1_DISABLE(x) (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x*/
918	#else
919	#define IWR1_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
920	#define IWR1_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F)))/* Wakeup Disable Peripheral #x */
921	#endif /* _MISRA_RULES */
922
923
924	/* ******* WATCHDOG TIMER MASKS ****************** */
925
926	/* Watchdog Timer WDOG_CTL Register Masks */
927
928	#ifdef _MISRA_RULES
929	#define WDEV(x) (((x)<<1) & 0x0006u) /* event generated on roll over */
930	#else
931	#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
932	#endif /* _MISRA_RULES */
933	#define WDEV_RESET 0x0000 /* generate reset event on roll over */
934	#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
935	#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
936	#define WDEV_NONE 0x0006 /* no event on roll over */
937	#define WDEN 0x0FF0 /* enable watchdog */
938	#define WDDIS 0x0AD0 /* disable watchdog */
939	#define WDRO 0x8000 /* watchdog rolled over latch */
940
941	/* depreciated WDOG_CTL Register Masks for legacy code */
942
943
944	#define ICTL WDEV
945	#define ENABLE_RESET WDEV_RESET
946	#define WDOG_RESET WDEV_RESET
947	#define ENABLE_NMI WDEV_NMI
948	#define WDOG_NMI WDEV_NMI
949	#define ENABLE_GPI WDEV_GPI
950	#define WDOG_GPI WDEV_GPI
951	#define DISABLE_EVT WDEV_NONE
952	#define WDOG_NONE WDEV_NONE
953
954	#define TMR_EN WDEN
955	#define TMR_DIS WDDIS
956	#define TRO WDRO
957	#define ICTL_P0 0x01
958	#define ICTL_P1 0x02
959	#define TRO_P 0x0F
960
961
962
963	/* ************* REAL TIME CLOCK MASKS ************************/
964	/* RTC_STAT and RTC_ALARM Masks */
965	#define RTC_SEC 0x0000003F /* Real-Time Clock Seconds */
966	#define RTC_MIN 0x00000FC0 /* Real-Time Clock Minutes */
967	#define RTC_HR 0x0001F000 /* Real-Time Clock Hours */
968	#define RTC_DAY 0xFFFE0000 /* Real-Time Clock Days */
969
970	/* RTC_ALARM Macro z=day y=hr x=min w=sec */
971	#ifdef _MISRA_RULES
972	#define SET_ALARM(z,y,x,w) ((((z)&0x7FFFu)<<0x11)\|(((y)&0x1Fu)<<0xC)\|(((x)&0x3Fu)<<0x6)\|((w)&0x3Fu))
973	#else
974	#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)\|(((y)&0x1F)<<0xC)\|(((x)&0x3F)<<0x6)\|((w)&0x3F))
975	#endif /* _MISRA_RULES */
976
977	/* RTC_ICTL and RTC_ISTAT Masks */
978	#define STOPWATCH 0x0001 /* Stopwatch Interrupt Enable */
979	#define ALARM 0x0002 /* Alarm Interrupt Enable */
980	#define SECOND 0x0004 /* Seconds (1 Hz) Interrupt Enable */
981	#define MINUTE 0x0008 /* Minutes Interrupt Enable */
982	#define HOUR 0x0010 /* Hours Interrupt Enable */
983	#define DAY 0x0020 /* 24 Hours (Days) Interrupt Enable */
984	#define DAY_ALARM 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
985	#define WRITE_PENDING 0x4000 /* Write Pending Status */
986	#define WRITE_COMPLETE 0x8000 /* Write Complete Interrupt Enable */
987
988	/* RTC_FAST / RTC_PREN Mask */
989	#define PREN 0x0001 /* Enable Prescaler, RTC Runs @1 Hz */
990
991
992	/* ************ UART CONTROLLER MASKS ***********************/
993	/* UARTx_LCR Masks */
994	#ifdef _MISRA_RULES
995	#define WLS(x) (((x)-5u) & 0x03u) /* Word Length Select */
996	#else
997	#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
998	#endif /* _MISRA_RULES */
999	#define STB 0x04 /* Stop Bits */
1000	#define PEN 0x08 /* Parity Enable */
1001	#define EPS 0x10 /* Even Parity Select */
1002	#define STP 0x20 /* Stick Parity */
1003	#define SB 0x40 /* Set Break */
1004	#define DLAB 0x80 /* Divisor Latch Access */
1005
1006	/* UARTx_MCR Mask */
1007	#define LOOP_ENA 0x10 /* Loopback Mode Enable */
1008	#define LOOP_ENA_P 0x04
1009
1010	/* UARTx_LSR Masks */
1011	#define DR 0x01 /* Data Ready */
1012	#define OE 0x02 /* Overrun Error */
1013	#define PE 0x04 /* Parity Error */
1014	#define FE 0x08 /* Framing Error */
1015	#define BI 0x10 /* Break Interrupt */
1016	#define THRE 0x20 /* THR Empty */
1017	#define TEMT 0x40 /* TSR and UART_THR Empty */
1018
1019	/* UARTx_IER Masks */
1020	#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
1021	#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
1022	#define ELSI 0x04 /* Enable RX Status Interrupt */
1023
1024	/* UARTx_IIR Masks */
1025	#define NINT 0x01 /* Pending Interrupt */
1026	#define STATUS 0x06 /* Highest Priority Pending Interrupt */
1027
1028	/* UARTx_GCTL Masks */
1029	#define UCEN 0x01 /* Enable UARTx Clocks */
1030	#define IREN 0x02 /* Enable IrDA Mode */
1031	#define TPOLC 0x04 /* IrDA TX Polarity Change */
1032	#define RPOLC 0x08 /* IrDA RX Polarity Change */
1033	#define FPE 0x10 /* Force Parity Error On Transmit */
1034	#define FFE 0x20 /* Force Framing Error On Transmit */
1035
1036	/* Bit masks for UART Divisor Latch Registers: UARTx_DLL & UARTx_DLH */
1037	#define UARTDLL 0x00FF /* Divisor Latch Low Byte */
1038	#define UARTDLH 0xFF00 /* Divisor Latch High Byte */
1039
1040
1041	/* ********* SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************************/
1042	/* SPI_CTL Masks */
1043	#define TIMOD 0x0003 /* Transfer Initiate Mode */
1044	#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
1045	#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
1046	#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
1047	#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
1048	#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last) /
1049	#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard) /
1050	#define PSSE 0x0010 /* Slave-Select Input Enable */
1051	#define EMISO 0x0020 /* Enable MISO As Output */
1052	#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
1053	#define LSBF 0x0200 /* LSB First */
1054	#define CPHA 0x0400 /* Clock Phase */
1055	#define CPOL 0x0800 /* Clock Polarity */
1056	#define MSTR 0x1000 /* Master/Slave* */
1057	#define WOM 0x2000 /* Write Open Drain Master */
1058	#define SPE 0x4000 /* SPI Enable */
1059
1060	/* SPI_FLG Masks */
1061	#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
1062	#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
1063	#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
1064	#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
1065	#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
1066	#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
1067	#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
1068	#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
1069	#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
1070	#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
1071	#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
1072	#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
1073	#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
1074	#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
1075
1076	/* SPI_STAT Masks */
1077	#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
1078	#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
1079	#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
1080	#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty) /
1081	#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
1082	#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty) /
1083	#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
1084
1085
1086	/* ************** GENERAL PURPOSE TIMER MASKS ********************/
1087	/* TIMER_ENABLE Masks */
1088	#define TIMEN0 0x0001 /* Enable Timer 0 */
1089	#define TIMEN1 0x0002 /* Enable Timer 1 */
1090	#define TIMEN2 0x0004 /* Enable Timer 2 */
1091	#define TIMEN3 0x0008 /* Enable Timer 3 */
1092	#define TIMEN4 0x0010 /* Enable Timer 4 */
1093	#define TIMEN5 0x0020 /* Enable Timer 5 */
1094	#define TIMEN6 0x0040 /* Enable Timer 6 */
1095	#define TIMEN7 0x0080 /* Enable Timer 7 */
1096
1097	/* TIMER_DISABLE Masks */
1098	#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
1099	#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
1100	#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
1101	#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
1102	#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
1103	#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
1104	#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
1105	#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
1106
1107	/* TIMER_STATUS Masks */
1108	#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
1109	#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
1110	#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
1111	#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
1112	#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
1113	#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
1114	#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
1115	#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
1116	#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
1117	#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
1118	#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
1119	#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
1120	#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
1121	#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
1122	#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
1123	#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
1124	#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
1125	#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
1126	#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
1127	#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
1128	#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
1129	#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
1130	#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
1131	#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
1132
1133	/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1134	#define TOVL_ERR0 TOVF_ERR0
1135	#define TOVL_ERR1 TOVF_ERR1
1136	#define TOVL_ERR2 TOVF_ERR2
1137	#define TOVL_ERR3 TOVF_ERR3
1138	#define TOVL_ERR4 TOVF_ERR4
1139	#define TOVL_ERR5 TOVF_ERR5
1140	#define TOVL_ERR6 TOVF_ERR6
1141	#define TOVL_ERR7 TOVF_ERR7
1142
1143	/* TIMERx_CONFIG Masks */
1144	#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
1145	#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
1146	#define EXT_CLK 0x0003 /* External Clock Mode */
1147	#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative) /
1148	#define PERIOD_CNT 0x0008 /* Period Count */
1149	#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
1150	#define TIN_SEL 0x0020 /* Timer Input Select */
1151	#define OUT_DIS 0x0040 /* Output Pad Disable */
1152	#define CLK_SEL 0x0080 /* Timer Clock Select */
1153	#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
1154	#define EMU_RUN 0x0200 /* Emulation Behavior Select */
1155	#define ERR_TYP 0xC000 /* Error Type */
1156
1157
1158	/* **************** GPIO PORTS F, G, H MASKS *********************/
1159	/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
1160	/* Port F Masks */
1161	#define PF0 0x0001
1162	#define PF1 0x0002
1163	#define PF2 0x0004
1164	#define PF3 0x0008
1165	#define PF4 0x0010
1166	#define PF5 0x0020
1167	#define PF6 0x0040
1168	#define PF7 0x0080
1169	#define PF8 0x0100
1170	#define PF9 0x0200
1171	#define PF10 0x0400
1172	#define PF11 0x0800
1173	#define PF12 0x1000
1174	#define PF13 0x2000
1175	#define PF14 0x4000
1176	#define PF15 0x8000
1177
1178	/* Port G Masks */
1179	#define PG0 0x0001
1180	#define PG1 0x0002
1181	#define PG2 0x0004
1182	#define PG3 0x0008
1183	#define PG4 0x0010
1184	#define PG5 0x0020
1185	#define PG6 0x0040
1186	#define PG7 0x0080
1187	#define PG8 0x0100
1188	#define PG9 0x0200
1189	#define PG10 0x0400
1190	#define PG11 0x0800
1191	#define PG12 0x1000
1192	#define PG13 0x2000
1193	#define PG14 0x4000
1194	#define PG15 0x8000
1195
1196	/* Port H Masks */
1197	#define PH0 0x0001
1198	#define PH1 0x0002
1199	#define PH2 0x0004
1200	#define PH3 0x0008
1201	#define PH4 0x0010
1202	#define PH5 0x0020
1203	#define PH6 0x0040
1204	#define PH7 0x0080
1205	#define PH8 0x0100
1206	#define PH9 0x0200
1207	#define PH10 0x0400
1208	#define PH11 0x0800
1209	#define PH12 0x1000
1210	#define PH13 0x2000
1211	#define PH14 0x4000
1212	#define PH15 0x8000
1213
1214
1215	/* ***************** SERIAL PORT MASKS ************************************/
1216	/* SPORTx_TCR1 Masks */
1217	#define TSPEN 0x0001 /* Transmit Enable */
1218	#define ITCLK 0x0002 /* Internal Transmit Clock Select */
1219	#define DTYPE_NORM 0x0000 /* Data Format Normal */
1220	#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1221	#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1222	#define TLSBIT 0x0010 /* Transmit Bit Order */
1223	#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
1224	#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
1225	#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
1226	#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
1227	#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
1228	#define TCKFE 0x4000 /* Clock Falling Edge Select */
1229
1230	/* SPORTx_TCR2 Masks and Macro */
1231	#ifdef _MISRA_RULES
1232	#define SLEN(x) ((x)&0x1Fu) /* SPORT TX Word Length (2 - 31) */
1233	#else
1234	#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
1235	#endif /* _MISRA_RULES */
1236
1237	#define TXSE 0x0100 /* TX Secondary Enable */
1238	#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
1239	#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
1240
1241	/* SPORTx_RCR1 Masks */
1242	#define RSPEN 0x0001 /* Receive Enable */
1243	#define IRCLK 0x0002 /* Internal Receive Clock Select */
1244	#define DTYPE_NORM 0x0000 /* Data Format Normal */
1245	#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1246	#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1247	#define RLSBIT 0x0010 /* Receive Bit Order */
1248	#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
1249	#define RFSR 0x0400 /* Receive Frame Sync Required Select */
1250	#define LRFS 0x1000 /* Low Receive Frame Sync Select */
1251	#define LARFS 0x2000 /* Late Receive Frame Sync Select */
1252	#define RCKFE 0x4000 /* Clock Falling Edge Select */
1253
1254	/* SPORTx_RCR2 Masks */
1255	#ifdef _MISRA_RULES
1256	#define SLEN(x) ((x)&0x1Fu) /* SPORT RX Word Length (2 - 31) */
1257	#else
1258	#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
1259	#endif /* _MISRA_RULES */
1260	#define RXSE 0x0100 /* RX Secondary Enable */
1261	#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
1262	#define RRFST 0x0400 /* Right-First Data Order */
1263
1264	/* SPORTx_STAT Masks */
1265	#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
1266	#define RUVF 0x0002 /* Sticky Receive Underflow Status */
1267	#define ROVF 0x0004 /* Sticky Receive Overflow Status */
1268	#define TXF 0x0008 /* Transmit FIFO Full Status */
1269	#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
1270	#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
1271	#define TXHRE 0x0040 /* Transmit Hold Register Empty */
1272
1273	/* SPORTx_MCMC1 Macros */
1274	#ifdef _MISRA_RULES
1275	#define WOFF(x) ((x) & 0x3FFu) /* Multichannel Window Offset Field */
1276	/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
1277	#define WSIZE(x) (((((x)>>0x3)-1u)&0xFu) << 0xC) /* Multichannel Window Size = (x/8)-1 */
1278
1279	#else
1280	#define WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
1281	/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
1282	#define WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
1283
1284	#endif /* _MISRA_RULES */
1285
1286	/* SPORTx_MCMC2 Masks */
1287	#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
1288	#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
1289	#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
1290	#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
1291	#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
1292	#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
1293	#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
1294	#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
1295	#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
1296	#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
1297	#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
1298	#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
1299	#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
1300	#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
1301	#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
1302	#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
1303	#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
1304	#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
1305	#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
1306	#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
1307	#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
1308	#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
1309	#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
1310
1311
1312	/* ******************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ***********************/
1313	/* EBIU_AMGCTL Masks */
1314	#define AMCKEN 0x0001 /* Enable CLKOUT */
1315	#define AMBEN 0x000e /* Async bank enable */
1316	#define AMBEN_NONE 0x0000 /* All Banks Disabled */
1317	#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
1318	#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
1319	#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
1320	#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
1321	#define CDPRIO 0x0100 /* DMA has priority over core for for external accesses */
1322
1323	/* EBIU_AMBCTL0 Masks */
1324	#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
1325	#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
1326	#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
1327	#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
1328	#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
1329	#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
1330	#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
1331	#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
1332	#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
1333	#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
1334	#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1335	#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1336	#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1337	#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1338	#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
1339	#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
1340	#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
1341	#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
1342	#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
1343	#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
1344	#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
1345	#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
1346	#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
1347	#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
1348	#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
1349	#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
1350	#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
1351	#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
1352	#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
1353	#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
1354	#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
1355	#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
1356	#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
1357	#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
1358	#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
1359	#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
1360	#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
1361	#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
1362	#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
1363	#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
1364	#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
1365	#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
1366	#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
1367	#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
1368
1369	#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
1370	#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
1371	#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
1372	#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
1373	#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
1374	#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
1375	#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
1376	#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
1377	#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
1378	#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
1379	#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1380	#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1381	#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1382	#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1383	#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
1384	#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
1385	#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
1386	#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
1387	#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
1388	#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
1389	#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
1390	#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
1391	#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
1392	#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
1393	#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
1394	#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
1395	#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
1396	#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
1397	#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
1398	#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
1399	#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
1400	#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
1401	#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
1402	#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
1403	#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
1404	#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
1405	#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
1406	#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
1407	#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
1408	#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
1409	#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
1410	#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
1411	#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
1412	#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
1413
1414	/* EBIU_AMBCTL1 Masks */
1415	#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
1416	#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
1417	#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
1418	#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
1419	#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
1420	#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
1421	#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
1422	#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
1423	#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
1424	#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
1425	#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1426	#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1427	#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1428	#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1429	#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
1430	#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
1431	#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
1432	#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
1433	#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
1434	#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
1435	#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
1436	#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
1437	#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
1438	#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
1439	#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
1440	#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
1441	#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
1442	#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
1443	#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
1444	#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
1445	#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
1446	#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
1447	#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
1448	#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
1449	#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
1450	#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
1451	#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
1452	#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
1453	#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
1454	#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
1455	#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
1456	#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
1457	#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
1458	#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
1459
1460	#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
1461	#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
1462	#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
1463	#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
1464	#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
1465	#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
1466	#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
1467	#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
1468	#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
1469	#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
1470	#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1471	#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1472	#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1473	#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1474	#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
1475	#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
1476	#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
1477	#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
1478	#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
1479	#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
1480	#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
1481	#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
1482	#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
1483	#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
1484	#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
1485	#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
1486	#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
1487	#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
1488	#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
1489	#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
1490	#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
1491	#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
1492	#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
1493	#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
1494	#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
1495	#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
1496	#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
1497	#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
1498	#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
1499	#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
1500	#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
1501	#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
1502	#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
1503	#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
1504
1505
1506	/* ******************** SDRAM CONTROLLER MASKS ********************************************/
1507	/* EBIU_SDGCTL Masks */
1508	#define SCTLE 0x00000001 /* Enable SDRAM Signals */
1509	#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
1510	#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
1511	/* EBIU_SDGCTL Masks */
1512	#define CL 0x0000000C /* SDRAM CAS latency */
1513	#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
1514	#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
1515	#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
1516	#define PASR 0x00000030 /* SDRAM partial array self-refresh */
1517	#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
1518	#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
1519	#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
1520	#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
1521	#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
1522	#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
1523	#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
1524	#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
1525	#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
1526	#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
1527	#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
1528	#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
1529	#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
1530	#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
1531	#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
1532	#define TRAS 0x000003C0 /* SDRAM tRAS in SCLK cycles */
1533	#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
1534	#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
1535	#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
1536	#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
1537	#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
1538	#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
1539	#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
1540	#define TRP 0x00003800 /* SDRAM tRP in SCLK cycles */
1541	#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
1542	#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
1543	#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
1544	#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
1545	#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
1546	#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1547	#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1548	#define TRCD 0x00030000 /* SDRAM tRCD in SCLK cycles */
1549	#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
1550	#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1551	#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1552	#define TWR 0x00180000 /* SDRAM tWR in SCLK cycles */
1553	#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
1554	#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
1555	#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
1556	#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
1557	#define EBUFE 0x02000000 /* Enable External Buffering Timing */
1558	#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
1559	#define EMREN 0x10000000 /* Extended Mode Register Enable */
1560	#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
1561	#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
1562
1563	/* EBIU_SDBCTL Masks */
1564	#define EBE 0x0001 /* Enable SDRAM External Bank */
1565	#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
1566	#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
1567	#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
1568	#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
1569	#define EBSZ 0x0006 /* SDRAM external bank size */
1570	#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
1571	#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
1572	#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
1573	#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
1574	#define EBCAW 0x0030 /* SDRAM external bank column address width */
1575
1576	/* EBIU_SDSTAT Masks */
1577	#define SDCI 0x0001 /* SDRAM Controller Idle */
1578	#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
1579	#define SDPUA 0x0004 /* SDRAM Power-Up Active */
1580	#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
1581	#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
1582	#define BGSTAT 0x0020 /* Bus Grant Status */
1583
1584
1585	/* ************************ DMA CONTROLLER MASKS ******************************/
1586	/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
1587	#define DMAEN 0x0001 /* DMA Channel Enable */
1588	#define WNR 0x0002 /* Channel Direction (W/R) /
1589	#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
1590	#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
1591	#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
1592	#define DMA2D 0x0010 /* DMA Mode (2D/1D) /
1593	#define SYNC 0x0020 /* DMA Buffer Clear */
1594	#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
1595	#define DI_EN 0x0080 /* Data Interrupt Enable */
1596	#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1597	#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1598	#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1599	#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1600	#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1601	#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1602	#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1603	#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1604	#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1605	#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1606	#define FLOW_STOP 0x0000 /* Stop Mode */
1607	#define FLOW_AUTO 0x1000 /* Autobuffer Mode */
1608	#define FLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1609	#define FLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1610	#define FLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1611
1612	/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1613	#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral) /
1614	#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
1615	#define PMAP_PPI 0x0000 /* PPI Port DMA */
1616	#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
1617	#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
1618	#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
1619	#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
1620	#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
1621	#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
1622	#define PMAP_SPI 0x7000 /* SPI Port DMA */
1623	#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
1624	#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
1625	#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
1626	#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
1627
1628	/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
1629	#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
1630	#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
1631	#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
1632	#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
1633
1634
1635	/* ********** PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ***********/
1636	/* PPI_CONTROL Masks */
1637	#define PORT_EN 0x0001 /* PPI Port Enable */
1638	#define PORT_DIR 0x0002 /* PPI Port Direction */
1639	#define XFR_TYPE 0x000C /* PPI Transfer Type */
1640	#define PORT_CFG 0x0030 /* PPI Port Configuration */
1641	#define FLD_SEL 0x0040 /* PPI Active Field Select */
1642	#define PACK_EN 0x0080 /* PPI Packing Mode */
1643	/* previous versions of defBF532.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
1644	#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
1645	#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
1646	#define DLEN_8 0x0000 /* Data Length = 8 Bits */
1647	#define DLEN_10 0x0800 /* Data Length = 10 Bits */
1648	#define DLEN_11 0x1000 /* Data Length = 11 Bits */
1649	#define DLEN_12 0x1800 /* Data Length = 12 Bits */
1650	#define DLEN_13 0x2000 /* Data Length = 13 Bits */
1651	#define DLEN_14 0x2800 /* Data Length = 14 Bits */
1652	#define DLEN_15 0x3000 /* Data Length = 15 Bits */
1653	#define DLEN_16 0x3800 /* Data Length = 16 Bits */
1654	#define POLC 0x4000 /* PPI Clock Polarity */
1655	#define POLS 0x8000 /* PPI Frame Sync Polarity */
1656
1657	/* PPI_STATUS Masks */
1658	#define LT_ERR_OVR 0x0100 /* Line Track Overflow Error */
1659	#define LT_ERR_UNDR 0x0200 /* Line Track Underflow Error */
1660	#define FLD 0x0400 /* Field Indicator */
1661	#define FT_ERR 0x0800 /* Frame Track Error */
1662	#define OVR 0x1000 /* FIFO Overflow Error */
1663	#define UNDR 0x2000 /* FIFO Underrun Error */
1664	#define ERR_DET 0x4000 /* Error Detected Indicator */
1665	#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
1666
1667
1668	/* ****************** TWO-WIRE INTERFACE (TWI) MASKS *********************/
1669	/* TWI_CLKDIV Macros (Use: pTWI_CLKDIV = CLKLOW(x)\|CLKHI(y); ) /
1670	#ifdef _MISRA_RULES
1671	#define CLKLOW(x) ((x) & 0xFFu) /* Periods Clock Is Held Low */
1672	#define CLKHI(y) (((y)&0xFFu)<<0x8) /* Periods Before New Clock Low */
1673	#else
1674	#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
1675	#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
1676	#endif /* _MISRA_RULES */
1677
1678	/* TWI_PRESCALE Masks */
1679	#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
1680	#define TWI_ENA 0x0080 /* TWI Enable */
1681	#define SCCB 0x0200 /* SCCB Compatibility Enable */
1682
1683	/* TWI_SLAVE_CTRL Masks */
1684	#define SEN 0x0001 /* Slave Enable */
1685	#define SADD_LEN 0x0002 /* Slave Address Length */
1686	#define STDVAL 0x0004 /* Slave Transmit Data Valid */
1687	#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1688	#define GEN 0x0010 /* General Call Adrress Matching Enabled */
1689
1690	/* TWI_SLAVE_STAT Masks */
1691	#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive) /
1692	#define GCALL 0x0002 /* General Call Indicator */
1693
1694	/* TWI_MASTER_CTRL Masks */
1695	#define MEN 0x0001 /* Master Mode Enable */
1696	#define MADD_LEN 0x0002 /* Master Address Length */
1697	#define MDIR 0x0004 /* Master Transmit Direction (RX/TX) /
1698	#define FAST 0x0008 /* Use Fast Mode Timing Specs */
1699	#define STOP 0x0010 /* Issue Stop Condition */
1700	#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
1701	#define DCNT 0x3FC0 /* Data Bytes To Transfer */
1702	#define SDAOVR 0x4000 /* Serial Data Override */
1703	#define SCLOVR 0x8000 /* Serial Clock Override */
1704
1705	/* TWI_MASTER_STAT Masks */
1706	#define MPROG 0x0001 /* Master Transfer In Progress */
1707	#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
1708	#define ANAK 0x0004 /* Address Not Acknowledged */
1709	#define DNAK 0x0008 /* Data Not Acknowledged */
1710	#define BUFRDERR 0x0010 /* Buffer Read Error */
1711	#define BUFWRERR 0x0020 /* Buffer Write Error */
1712	#define SDASEN 0x0040 /* Serial Data Sense */
1713	#define SCLSEN 0x0080 /* Serial Clock Sense */
1714	#define BUSBUSY 0x0100 /* Bus Busy Indicator */
1715
1716	/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
1717	#define SINIT 0x0001 /* Slave Transfer Initiated */
1718	#define SCOMP 0x0002 /* Slave Transfer Complete */
1719	#define SERR 0x0004 /* Slave Transfer Error */
1720	#define SOVF 0x0008 /* Slave Overflow */
1721	#define MCOMP 0x0010 /* Master Transfer Complete */
1722	#define MERR 0x0020 /* Master Transfer Error */
1723	#define XMTSERV 0x0040 /* Transmit FIFO Service */
1724	#define RCVSERV 0x0080 /* Receive FIFO Service */
1725
1726	/* TWI_FIFO_CTRL Masks */
1727	#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
1728	#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
1729	#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
1730	#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
1731
1732	/* TWI_FIFO_STAT Masks */
1733	#define XMTSTAT 0x0003 /* Transmit FIFO Status */
1734	#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
1735	#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
1736	#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
1737
1738	#define RCVSTAT 0x000C /* Receive FIFO Status */
1739	#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
1740	#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1741	#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1742
1743
1744	/* Omit CAN masks from defBF534.h */
1745
1746	/* ***************** PIN CONTROL REGISTER MASKS **********************/
1747	/* PORT_MUX deleted in VisualDSP++ 5.0 Update 3 */
1748
1749
1750	/* **************** HANDSHAKE DMA (HMDMA) MASKS *******************/
1751	/* HMDMAx_CTL Masks */
1752	#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */
1753	#define REP 0x0002 /* HMDMA Request Polarity */
1754	#define UTE 0x0004 /* Urgency Threshold Enable */
1755	#define OIE 0x0010 /* Overflow Interrupt Enable */
1756	#define BDIE 0x0020 /* Block Done Interrupt Enable */
1757	#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */
1758	#define DRQ 0x0300 /* HMDMA Request Type */
1759	#define DRQ_NONE 0x0000 /* No Request */
1760	#define DRQ_SINGLE 0x0100 /* Channels Request Single */
1761	#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */
1762	#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */
1763	#define RBC 0x1000 /* Reload BCNT With IBCNT */
1764	#define PS 0x2000 /* HMDMA Pin Status */
1765	#define OI 0x4000 /* Overflow Interrupt Generated */
1766	#define BDI 0x8000 /* Block Done Interrupt Generated */
1767
1768	/* entry addresses of the user-callable Boot ROM functions */
1769
1770	#define _BOOTROM_RESET 0xEF000000
1771	#define _BOOTROM_FINAL_INIT 0xEF000002
1772	#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
1773	#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
1774	#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
1775	#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
1776	#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
1777	#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
1778	#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
1779
1780	/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1781	#define CKELOW SCKELOW
1782
1783	/* ==== end from defBF534.h ==== */
1784
1785	/* HOST Port Registers */
1786
1787	#define HOST_CONTROL 0xffc03400 /* HOSTDP Control Register */
1788	#define HOST_STATUS 0xffc03404 /* HOSTDP Status Register */
1789	#define HOST_TIMEOUT 0xffc03408 /* HOSTDP Acknowledge Mode Timeout Register */
1790
1791	/* Counter Registers */
1792
1793	#define CNT_CONFIG 0xffc03500 /* Configuration Register */
1794	#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */
1795	#define CNT_STATUS 0xffc03508 /* Status Register */
1796	#define CNT_COMMAND 0xffc0350c /* Command Register */
1797	#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */
1798	#define CNT_COUNTER 0xffc03514 /* Counter Register */
1799	#define CNT_MAX 0xffc03518 /* Maximal Count Register */
1800	#define CNT_MIN 0xffc0351c /* Minimal Count Register */
1801
1802	/* OTP/FUSE Registers */
1803
1804	#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */
1805	#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */
1806	#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */
1807	#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */
1808
1809	/* Security Registers */
1810
1811	#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */
1812	#define SECURE_CONTROL 0xffc03624 /* Secure Control */
1813	#define SECURE_STATUS 0xffc03628 /* Secure Status */
1814
1815	/* OTP Read/Write Data Buffer Registers */
1816
1817	#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1818	#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1819	#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1820	#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1821
1822	/* NFC Registers */
1823
1824	#define NFC_CTL 0xffc03700 /* NAND Control Register */
1825	#define NFC_STAT 0xffc03704 /* NAND Status Register */
1826	#define NFC_IRQSTAT 0xffc03708 /* NAND Interrupt Status Register */
1827	#define NFC_IRQMASK 0xffc0370c /* NAND Interrupt Mask Register */
1828	#define NFC_ECC0 0xffc03710 /* NAND ECC Register 0 */
1829	#define NFC_ECC1 0xffc03714 /* NAND ECC Register 1 */
1830	#define NFC_ECC2 0xffc03718 /* NAND ECC Register 2 */
1831	#define NFC_ECC3 0xffc0371c /* NAND ECC Register 3 */
1832	#define NFC_COUNT 0xffc03720 /* NAND ECC Count Register */
1833	#define NFC_RST 0xffc03724 /* NAND ECC Reset Register */
1834	#define NFC_PGCTL 0xffc03728 /* NAND Page Control Register */
1835	#define NFC_READ 0xffc0372c /* NAND Read Data Register */
1836	#define NFC_ADDR 0xffc03740 /* NAND Address Register */
1837	#define NFC_CMD 0xffc03744 /* NAND Command Register */
1838	#define NFC_DATA_WR 0xffc03748 /* NAND Data Write Register */
1839	#define NFC_DATA_RD 0xffc0374c /* NAND Data Read Register */
1840
1841	/* ********************************************************** */
1842	/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
1843	/* and MULTI BIT READ MACROS */
1844	/* ********************************************************** */
1845
1846	/* Bit masks for HOST_CONTROL */
1847
1848	#define HOSTDP_EN 0x1 /* HOSTDP Enable */
1849	#define nHOSTDP_EN 0x0
1850	#define HOSTDP_END 0x2 /* Host Endianess */
1851	#define nHOSTDP_END 0x0
1852	#define HOSTDP_DATA_SIZE 0x4 /* Data Size */
1853	#define nHOSTDP_DATA_SIZE 0x0
1854	#define HOSTDP_RST 0x8 /* HOSTDP Reset */
1855	#define nHOSTDP_RST 0x0
1856	#define HRDY_OVR 0x20 /* HRDY Override */
1857	#define nHRDY_OVR 0x0
1858	#define INT_MODE 0x40 /* Interrupt Mode */
1859	#define nINT_MODE 0x0
1860	#define BT_EN 0x80 /* Bus Timeout Enable */
1861	#define nBT_EN 0x0
1862	#define EHW 0x100 /* Enable Host Write */
1863	#define nEHW 0x0
1864	#define EHR 0x200 /* Enable Host Read */
1865	#define nEHR 0x0
1866	#define BDR 0x400 /* Burst DMA Requests */
1867	#define nBDR 0x0
1868
1869	/* Bit masks for HOST_STATUS */
1870
1871	#define DMA_RDY 0x1 /* DMA Ready */
1872	#define nDMA_RDY 0x0
1873	#define FIFOFULL 0x2 /* FIFO Full */
1874	#define nFIFOFULL 0x0
1875	#define FIFOEMPTY 0x4 /* FIFO Empty */
1876	#define nFIFOEMPTY 0x0
1877	#define DMA_CMPLT 0x8 /* DMA Complete */
1878	#define nDMA_CMPLT 0x0
1879	#define HSHK 0x10 /* Host Handshake */
1880	#define nHSHK 0x0
1881	#define HOSTDP_TOUT 0x20 /* HOSTDP Timeout */
1882	#define nHOSTDP_TOUT 0x0
1883	#define HIRQ 0x40 /* Host Interrupt Request */
1884	#define nHIRQ 0x0
1885	#define ALLOW_CNFG 0x80 /* Allow New Configuration */
1886	#define nALLOW_CNFG 0x0
1887	#define DMA_DIR 0x100 /* DMA Direction */
1888	#define nDMA_DIR 0x0
1889	#define BTE 0x200 /* Bus Timeout Enabled */
1890	#define nBTE 0x0
1891	#define HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
1892	#define nHOSTRD_DONE 0x0
1893
1894	/* Bit masks for HOST_TIMEOUT */
1895
1896	#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
1897
1898	/* Bit masks for CNT_CONFIG */
1899
1900	#define CNTE 0x1 /* Counter Enable */
1901	#define nCNTE 0x0
1902	#define DEBE 0x2 /* Debounce Enable */
1903	#define nDEBE 0x0
1904	#define CDGINV 0x10 /* CDG Pin Polarity Invert */
1905	#define nCDGINV 0x0
1906	#define CUDINV 0x20 /* CUD Pin Polarity Invert */
1907	#define nCUDINV 0x0
1908	#define CZMINV 0x40 /* CZM Pin Polarity Invert */
1909	#define nCZMINV 0x0
1910	#define CNTMODE 0x700 /* Counter Operating Mode */
1911	#define ZMZC 0x800 /* CZM Zeroes Counter Enable */
1912	#define nZMZC 0x0
1913	#define BNDMODE 0x3000 /* Boundary register Mode */
1914	#define INPDIS 0x8000 /* CUG and CDG Input Disable */
1915	#define nINPDIS 0x0
1916
1917	/* Bit masks for CNT_IMASK */
1918
1919	#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
1920	#define nICIE 0x0
1921	#define UCIE 0x2 /* Up count Interrupt Enable */
1922	#define nUCIE 0x0
1923	#define DCIE 0x4 /* Down count Interrupt Enable */
1924	#define nDCIE 0x0
1925	#define MINCIE 0x8 /* Min Count Interrupt Enable */
1926	#define nMINCIE 0x0
1927	#define MAXCIE 0x10 /* Max Count Interrupt Enable */
1928	#define nMAXCIE 0x0
1929	#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
1930	#define nCOV31IE 0x0
1931	#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
1932	#define nCOV15IE 0x0
1933	#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
1934	#define nCZEROIE 0x0
1935	#define CZMIE 0x100 /* CZM Pin Interrupt Enable */
1936	#define nCZMIE 0x0
1937	#define CZMEIE 0x200 /* CZM Error Interrupt Enable */
1938	#define nCZMEIE 0x0
1939	#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
1940	#define nCZMZIE 0x0
1941
1942	/* Bit masks for CNT_STATUS */
1943
1944	#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
1945	#define nICII 0x0
1946	#define UCII 0x2 /* Up count Interrupt Identifier */
1947	#define nUCII 0x0
1948	#define DCII 0x4 /* Down count Interrupt Identifier */
1949	#define nDCII 0x0
1950	#define MINCII 0x8 /* Min Count Interrupt Identifier */
1951	#define nMINCII 0x0
1952	#define MAXCII 0x10 /* Max Count Interrupt Identifier */
1953	#define nMAXCII 0x0
1954	#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
1955	#define nCOV31II 0x0
1956	#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
1957	#define nCOV15II 0x0
1958	#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
1959	#define nCZEROII 0x0
1960	#define CZMII 0x100 /* CZM Pin Interrupt Identifier */
1961	#define nCZMII 0x0
1962	#define CZMEII 0x200 /* CZM Error Interrupt Identifier */
1963	#define nCZMEII 0x0
1964	#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
1965	#define nCZMZII 0x0
1966
1967	/* Bit masks for CNT_COMMAND */
1968
1969	#define W1LCNT 0xf /* Load Counter Register */
1970	#define W1LMIN 0xf0 /* Load Min Register */
1971	#define W1LMAX 0xf00 /* Load Max Register */
1972	#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
1973	#define nW1ZMONCE 0x0
1974
1975	/* Bit masks for CNT_DEBOUNCE */
1976
1977	#define DPRESCALE 0xf /* Load Counter Register */
1978
1979	/* Bit masks for SECURE_SYSSWT */
1980
1981	#define EMUDABL 0x1 /* Emulation Disable. */
1982	#define nEMUDABL 0x0
1983	#define RSTDABL 0x2 /* Reset Disable */
1984	#define nRSTDABL 0x0
1985	#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
1986	#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
1987	#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
1988	#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
1989	#define nDMA0OVR 0x0
1990	#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
1991	#define nDMA1OVR 0x0
1992	#define EMUOVR 0x4000 /* Emulation Override */
1993	#define nEMUOVR 0x0
1994	#define OTPSEN 0x8000 /* OTP Secrets Enable. */
1995	#define nOTPSEN 0x0
1996
1997	/* Bit masks for SECURE_CONTROL */
1998
1999	#define SECURE0 0x1 /* SECURE 0 */
2000	#define nSECURE0 0x0
2001	#define SECURE1 0x2 /* SECURE 1 */
2002	#define nSECURE1 0x0
2003	#define SECURE2 0x4 /* SECURE 2 */
2004	#define nSECURE2 0x0
2005	#define SECURE3 0x8 /* SECURE 3 */
2006	#define nSECURE3 0x0
2007
2008	/* Bit masks for SECURE_STATUS */
2009
2010	#define SECMODE 0x3 /* Secured Mode Control State */
2011	#define NMI 0x4 /* Non Maskable Interrupt */
2012	#define nNMI 0x0
2013	#define AFVALID 0x8 /* Authentication Firmware Valid */
2014	#define nAFVALID 0x0
2015	#define AFEXIT 0x10 /* Authentication Firmware Exit */
2016	#define nAFEXIT 0x0
2017	#define SECSTAT 0xe0 /* Secure Status */
2018
2019	/* Bit masks for NFC_CTL */
2020
2021	#define WR_DLY 0xf /* Write Strobe Delay */
2022	#define RD_DLY 0xf0 /* Read Strobe Delay */
2023	#define PG_SIZE 0x200 /* Page Size */
2024	#define nPG_SIZE 0x0
2025
2026	/* Bit masks for NFC_STAT */
2027
2028	#define NBUSY 0x1 /* Not Busy */
2029	#define nNBUSY 0x0
2030	#define WB_FULL 0x2 /* Write Buffer Full */
2031	#define nWB_FULL 0x0
2032	#define PG_WR_STAT 0x4 /* Page Write Pending */
2033	#define nPG_WR_STAT 0x0
2034	#define PG_RD_STAT 0x8 /* Page Read Pending */
2035	#define nPG_RD_STAT 0x0
2036	#define WB_EMPTY 0x10 /* Write Buffer Empty */
2037	#define nWB_EMPTY 0x0
2038
2039	/* Bit masks for NFC_IRQSTAT */
2040
2041	#define NBUSYIRQ 0x1 /* Not Busy IRQ */
2042	#define nNBUSYIRQ 0x0
2043	#define WB_OVF 0x2 /* Write Buffer Overflow */
2044	#define nWB_OVF 0x0
2045	#define WB_EDGE 0x4 /* Write Buffer Edge Detect */
2046	#define nWB_EDGE 0x0
2047	#define RD_RDY 0x8 /* Read Data Ready */
2048	#define nRD_RDY 0x0
2049	#define WR_DONE 0x10 /* Page Write Done */
2050	#define nWR_DONE 0x0
2051
2052	/* Bit masks for NFC_IRQMASK */
2053
2054	#define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */
2055	#define nMASK_BUSYIRQ 0x0
2056	#define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */
2057	#define nMASK_WBOVF 0x0
2058	#define MASK_WBEDGE 0x4 /* Mask Write Buffer Edge Detect */
2059	#define nMASK_WBEDGE 0x0
2060	#define MASK_RDRDY 0x8 /* Mask Read Data Ready */
2061	#define nMASK_RDRDY 0x0
2062	#define MASK_WRDONE 0x10 /* Mask Write Done */
2063	#define nMASK_WRDONE 0x0
2064
2065	/* Bit masks for NFC_RST */
2066
2067	#define ECC_RST 0x1 /* ECC (and NFC counters) Reset */
2068	#define nECC_RST 0x0
2069
2070	/* Bit masks for NFC_PGCTL */
2071
2072	#define PG_RD_START 0x1 /* Page Read Start */
2073	#define nPG_RD_START 0x0
2074	#define PG_WR_START 0x2 /* Page Write Start */
2075	#define nPG_WR_START 0x0
2076
2077	/* Bit masks for NFC_ECC0 */
2078
2079	#define ECC0 0x7ff /* Parity Calculation Result0 */
2080
2081	/* Bit masks for NFC_ECC1 */
2082
2083	#define ECC1 0x7ff /* Parity Calculation Result1 */
2084
2085	/* Bit masks for NFC_ECC2 */
2086
2087	#define ECC2 0x7ff /* Parity Calculation Result2 */
2088
2089	/* Bit masks for NFC_ECC3 */
2090
2091	#define ECC3 0x7ff /* Parity Calculation Result3 */
2092
2093	/* Bit masks for NFC_COUNT */
2094
2095	#define ECCCNT 0x3ff /* Transfer Count */
2096
2097	#ifdef _MISRA_RULES
2098	#pragma diag(pop)
2099	#endif /* _MISRA_RULES */
2100
2101	#endif /* _DEF_BF52X_H */

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source: trunk/libs/newlib/src/libgloss/bfin/include/defBF52x_base.h @ 444

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