Context Navigation

← Previous Revision
Latest Revision
Next Revision →
Blame
Revision Log

defBF547.h @ 444

Last change on this file since 444 was 444, checked in by satin@…, 6 years ago
add newlib,libalmos-mkh, restructure shared_syscalls.h and mini-libc
File size: 88.9 KB

Line
1	/*
2	* The authors hereby grant permission to use, copy, modify, distribute,
3	* and license this software and its documentation for any purpose, provided
4	* that existing copyright notices are retained in all copies and that this
5	* notice is included verbatim in any distributions. No written agreement,
6	* license, or royalty fee is required for any of the authorized uses.
7	* Modifications to this software may be copyrighted by their authors
8	* and need not follow the licensing terms described here, provided that
9	* the new terms are clearly indicated on the first page of each file where
10	* they apply.
11	*/
12
13	/*
14	** defBF547.h
15	**
16	** Copyright (C) 2007-2008 Analog Devices Inc., All Rights Reserved.
17	**
18	************************************************************************************
19	**
20	** This include file contains a list of macro "defines" to enable the programmer
21	** to use symbolic names for register-access and bit-manipulation.
22	**
23	**/
24	#ifndef _DEF_BF547_H
25	#define _DEF_BF547_H
26
27	/* Include all Core registers and bit definitions */
28	#include <def_LPBlackfin.h>
29
30	/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF547 */
31
32	/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
33	#include <defBF54x_base.h>
34
35	#ifdef _MISRA_RULES
36	#pragma diag(push)
37	#pragma diag(suppress:misra_rule_19_4:"some macros violate rule 19.4 ")
38	#pragma diag(suppress:misra_rule_19_7:"Allow function-like macros ")
39	#endif /* _MISRA_RULES */
40
41	/* The following are the #defines needed by ADSP-BF547 that are not in the common header */
42
43	/* Timer Registers */
44
45	#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
46	#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
47	#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
48	#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
49	#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
50	#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
51	#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
52	#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
53	#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
54	#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
55	#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
56	#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
57
58	/* Timer Group of 3 Registers */
59
60	#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
61	#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
62	#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
63
64	/* SPORT0 Registers */
65
66	#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
67	#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
68	#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
69	#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
70	#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */
71	#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */
72	#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */
73	#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */
74	#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
75	#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
76	#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */
77	#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */
78	#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
79	#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
80	#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
81	#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
82	#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
83	#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
84	#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
85	#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
86	#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
87	#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
88
89	/* EPPI0 Registers */
90
91	#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
92	#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
93	#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
94	#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
95	#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
96	#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
97	#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
98	#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
99	#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
100	#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
101	#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
102	#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
103	#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
104	#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
105
106	/* UART2 Registers */
107
108	#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */
109	#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */
110	#define UART2_GCTL 0xffc02108 /* Global Control Register */
111	#define UART2_LCR 0xffc0210c /* Line Control Register */
112	#define UART2_MCR 0xffc02110 /* Modem Control Register */
113	#define UART2_LSR 0xffc02114 /* Line Status Register */
114	#define UART2_MSR 0xffc02118 /* Modem Status Register */
115	#define UART2_SCR 0xffc0211c /* Scratch Register */
116	#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */
117	#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */
118	#define UART2_THR 0xffc02128 /* Transmit Hold Register */
119	#define UART2_RBR 0xffc0212c /* Receive Buffer Register */
120
121	/* Two Wire Interface Registers (TWI1) */
122
123	#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
124	#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
125	#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */
126	#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
127	#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
128	#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */
129	#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
130	#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
131	#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
132	#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
133	#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */
134	#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
135	#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
136	#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
137	#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
138	#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
139
140	/* SPI2 Registers */
141
142	#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
143	#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
144	#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
145	#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */
146	#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */
147	#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */
148	#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */
149
150
151	/* ATAPI Registers */
152
153	#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
154	#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
155	#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
156	#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
157	#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
158	#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
159	#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
160	#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
161	#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
162	#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
163	#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
164	#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
165	#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
166	#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
167	#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
168	#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
169	#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
170	#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
171	#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
172	#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
173	#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
174	#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
175	#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
176	#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
177	#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
178
179	/* SDH Registers */
180
181	#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
182	#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
183	#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
184	#define SDH_COMMAND 0xffc0390c /* SDH Command */
185	#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
186	#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
187	#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
188	#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
189	#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
190	#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
191	#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
192	#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
193	#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
194	#define SDH_STATUS 0xffc03934 /* SDH Status */
195	#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
196	#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
197	#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
198	#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
199	#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
200	#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
201	#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
202	#define SDH_CFG 0xffc039c8 /* SDH Configuration */
203	#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
204	#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
205	#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
206	#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
207	#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
208	#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
209	#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
210	#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
211	#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
212
213	/* HOST Port Registers */
214
215	#define HOST_CONTROL 0xffc03a00 /* HOSTDP Control Register */
216	#define HOST_STATUS 0xffc03a04 /* HOSTDP Status Register */
217	#define HOST_TIMEOUT 0xffc03a08 /* HOSTDP Acknowledge Mode Timeout Register */
218
219	/* USB Control Registers */
220
221	#define USB_FADDR 0xffc03c00 /* Function address register */
222	#define USB_POWER 0xffc03c04 /* Power management register */
223	#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
224	#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
225	#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
226	#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
227	#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
228	#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
229	#define USB_FRAME 0xffc03c20 /* USB frame number */
230	#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
231	#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
232	#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
233	#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
234
235	/* USB Packet Control Registers */
236
237	#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
238	#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
239	#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
240	#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
241	#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
242	#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
243	#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
244	#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
245	#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
246	#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
247	#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
248	#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
249	#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
250
251	/* USB Endpoint FIFO Registers */
252
253	#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
254	#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
255	#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
256	#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
257	#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
258	#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
259	#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
260	#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
261
262	/* USB OTG Control Registers */
263
264	#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
265	#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
266	#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
267
268	/* USB Phy Control Registers */
269
270	#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
271	#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
272	#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
273	#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
274	#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
275
276	/* (APHY_CNTRL is for ADI usage only) */
277
278	#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
279
280	/* (APHY_CALIB is for ADI usage only) */
281
282	#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
283	#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
284
285	/* (PHY_TEST is for ADI usage only) */
286
287	#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
288	#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
289	#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
290
291	/* USB Endpoint 0 Control Registers */
292
293	#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
294	#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
295	#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
296	#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
297	#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
298	#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
299	#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
300	#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
301	#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
302
303	/* USB Endpoint 1 Control Registers */
304
305	#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
306	#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
307	#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
308	#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
309	#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
310	#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
311	#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
312	#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
313	#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
314	#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
315
316	/* USB Endpoint 2 Control Registers */
317
318	#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
319	#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
320	#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
321	#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
322	#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
323	#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
324	#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
325	#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
326	#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
327	#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
328
329	/* USB Endpoint 3 Control Registers */
330
331	#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
332	#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
333	#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
334	#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
335	#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
336	#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
337	#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
338	#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
339	#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
340	#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
341
342	/* USB Endpoint 4 Control Registers */
343
344	#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
345	#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
346	#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
347	#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
348	#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
349	#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
350	#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
351	#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
352	#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
353	#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
354
355	/* USB Endpoint 5 Control Registers */
356
357	#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
358	#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
359	#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
360	#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
361	#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
362	#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
363	#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
364	#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
365	#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
366	#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
367
368	/* USB Endpoint 6 Control Registers */
369
370	#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
371	#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
372	#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
373	#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
374	#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
375	#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
376	#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
377	#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
378	#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
379	#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
380
381	/* USB Endpoint 7 Control Registers */
382
383	#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
384	#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
385	#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
386	#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
387	#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
388	#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
389	#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
390	#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
391	#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
392	#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
393	#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
394	#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
395
396	/* USB Channel 0 Config Registers */
397
398	#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
399	#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
400	#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
401	#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
402	#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
403
404	/* USB Channel 1 Config Registers */
405
406	#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
407	#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
408	#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
409	#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
410	#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
411
412	/* USB Channel 2 Config Registers */
413
414	#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
415	#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
416	#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
417	#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
418	#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
419
420	/* USB Channel 3 Config Registers */
421
422	#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
423	#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
424	#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
425	#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
426	#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
427
428	/* USB Channel 4 Config Registers */
429
430	#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
431	#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
432	#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
433	#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
434	#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
435
436	/* USB Channel 5 Config Registers */
437
438	#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
439	#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
440	#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
441	#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
442	#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
443
444	/* USB Channel 6 Config Registers */
445
446	#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
447	#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
448	#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
449	#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
450	#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
451
452	/* USB Channel 7 Config Registers */
453
454	#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
455	#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
456	#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
457	#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
458	#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
459
460	/* Keypad Registers */
461
462	#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
463	#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
464	#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
465	#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
466	#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
467	#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
468
469	/* Pixel Compositor (PIXC) Registers */
470
471	#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
472	#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
473	#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
474	#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
475	#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
476	#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
477	#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
478	#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
479	#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
480	#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
481	#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
482	#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
483	#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
484	#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
485	#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
486	#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
487	#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
488	#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
489	#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
490
491	/* ********************************************************** */
492	/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
493	/* and MULTI BIT READ MACROS */
494	/* ********************************************************** */
495
496	/* Bit masks for PIXC_CTL */
497
498	#define PIXC_EN 0x1 /* Pixel Compositor Enable */
499	#define nPIXC_EN 0x0
500	#define OVR_A_EN 0x2 /* Overlay A Enable */
501	#define nOVR_A_EN 0x0
502	#define OVR_B_EN 0x4 /* Overlay B Enable */
503	#define nOVR_B_EN 0x0
504	#define IMG_FORM 0x8 /* Image Data Format */
505	#define nIMG_FORM 0x0
506	#define OVR_FORM 0x10 /* Overlay Data Format */
507	#define nOVR_FORM 0x0
508	#define OUT_FORM 0x20 /* Output Data Format */
509	#define nOUT_FORM 0x0
510	#define UDS_MOD 0x40 /* Resampling Mode */
511	#define nUDS_MOD 0x0
512	#define TC_EN 0x80 /* Transparent Color Enable */
513	#define nTC_EN 0x0
514	#define IMG_STAT 0x300 /* Image FIFO Status */
515	#define OVR_STAT 0xc00 /* Overlay FIFO Status */
516	#define WM_LVL 0x3000 /* FIFO Watermark Level */
517
518	/* Bit masks for PIXC_AHSTART */
519
520	#define A_HSTART 0xfff /* Horizontal Start Coordinates */
521
522	/* Bit masks for PIXC_AHEND */
523
524	#define A_HEND 0xfff /* Horizontal End Coordinates */
525
526	/* Bit masks for PIXC_AVSTART */
527
528	#define A_VSTART 0x3ff /* Vertical Start Coordinates */
529
530	/* Bit masks for PIXC_AVEND */
531
532	#define A_VEND 0x3ff /* Vertical End Coordinates */
533
534	/* Bit masks for PIXC_ATRANSP */
535
536	#define A_TRANSP 0xf /* Transparency Value */
537
538	/* Bit masks for PIXC_BHSTART */
539
540	#define B_HSTART 0xfff /* Horizontal Start Coordinates */
541
542	/* Bit masks for PIXC_BHEND */
543
544	#define B_HEND 0xfff /* Horizontal End Coordinates */
545
546	/* Bit masks for PIXC_BVSTART */
547
548	#define B_VSTART 0x3ff /* Vertical Start Coordinates */
549
550	/* Bit masks for PIXC_BVEND */
551
552	#define B_VEND 0x3ff /* Vertical End Coordinates */
553
554	/* Bit masks for PIXC_BTRANSP */
555
556	#define B_TRANSP 0xf /* Transparency Value */
557
558	/* Bit masks for PIXC_INTRSTAT */
559
560	#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
561	#define nOVR_INT_EN 0x0
562	#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
563	#define nFRM_INT_EN 0x0
564	#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
565	#define nOVR_INT_STAT 0x0
566	#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
567	#define nFRM_INT_STAT 0x0
568
569	/* Bit masks for PIXC_RYCON */
570
571	#define A11 0x3ff /* A11 in the Coefficient Matrix */
572	#define A12 0xffc00 /* A12 in the Coefficient Matrix */
573	#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
574	#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
575	#define nRY_MULT4 0x0
576
577	/* Bit masks for PIXC_GUCON */
578
579	#define A21 0x3ff /* A21 in the Coefficient Matrix */
580	#define A22 0xffc00 /* A22 in the Coefficient Matrix */
581	#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
582	#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
583	#define nGU_MULT4 0x0
584
585	/* Bit masks for PIXC_BVCON */
586
587	#define A31 0x3ff /* A31 in the Coefficient Matrix */
588	#define A32 0xffc00 /* A32 in the Coefficient Matrix */
589	#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
590	#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
591	#define nBV_MULT4 0x0
592
593	/* Bit masks for PIXC_CCBIAS */
594
595	#define A14 0x3ff /* A14 in the Bias Vector */
596	#define A24 0xffc00 /* A24 in the Bias Vector */
597	#define A34 0x3ff00000 /* A34 in the Bias Vector */
598
599	/* Bit masks for PIXC_TC */
600
601	#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
602	#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
603	#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
604
605	/* Bit masks for HOST_CONTROL */
606
607	#define HOSTDP_EN 0x1 /* HOSTDP Enable */
608	#define nHOSTDP_EN 0x0
609	#define HOSTDP_END 0x2 /* Host Endianess */
610	#define nHOSTDP_END 0x0
611	#define HOSTDP_DATA_SIZE 0x4 /* Data Size */
612	#define nHOSTDP_DATA_SIZE 0x0
613	#define HOSTDP_RST 0x8 /* HOSTDP Reset */
614	#define nHOSTDP_RST 0x0
615	#define HRDY_OVR 0x20 /* HRDY Override */
616	#define nHRDY_OVR 0x0
617	#define INT_MODE 0x40 /* Interrupt Mode */
618	#define nINT_MODE 0x0
619	#define BT_EN 0x80 /* Bus Timeout Enable */
620	#define nBT_EN 0x0
621	#define EHW 0x100 /* Enable Host Write */
622	#define nEHW 0x0
623	#define EHR 0x200 /* Enable Host Read */
624	#define nEHR 0x0
625	#define BDR 0x400 /* Burst DMA Requests */
626	#define nBDR 0x0
627
628	/* Bit masks for HOST_STATUS */
629
630	#define DMA_RDY 0x1 /* DMA Ready */
631	#define nDMA_RDY 0x0
632	#define FIFOFULL 0x2 /* FIFO Full */
633	#define nFIFOFULL 0x0
634	#define FIFOEMPTY 0x4 /* FIFO Empty */
635	#define nFIFOEMPTY 0x0
636	#define DMA_CMPLT 0x8 /* DMA Complete */
637	#define nDMA_CMPLT 0x0
638	#define HSHK 0x10 /* Host Handshake */
639	#define nHSHK 0x0
640	#define HOSTDP_TOUT 0x20 /* HOSTDP Timeout */
641	#define nHOSTDP_TOUT 0x0
642	#define HIRQ 0x40 /* Host Interrupt Request */
643	#define nHIRQ 0x0
644	#define ALLOW_CNFG 0x80 /* Allow New Configuration */
645	#define nALLOW_CNFG 0x0
646	#define DMA_DIR 0x100 /* DMA Direction */
647	#define nDMA_DIR 0x0
648	#define BTE 0x200 /* Bus Timeout Enabled */
649	#define nBTE 0x0
650
651	/* Bit masks for HOST_TIMEOUT */
652
653	#define COUNT_TIMEOUT 0x7ff /* HOSTDP Timeout count */
654
655	/* Bit masks for KPAD_CTL */
656
657	#define KPAD_EN 0x1 /* Keypad Enable */
658	#define nKPAD_EN 0x0
659	#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
660	#define nKPAD_IRQMODE 0x0 /* Interrupt Disabled */
661	#define KPAD_IRQMODE_SK 0x2 /* Single key (single row, single column) press interrupt enable */
662	#define KPAD_IRQMODE_MK 0x4 /* Single key press multiple key press interrupt enable */
663
664	#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
665	#define KPAD_COLEN 0xe000 /* Column Enable Width */
666
667	#ifdef _MISRA_RULES
668	#define SET_KPAD_ROWEN(x) (((x)&0x7u)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
669	#define SET_KPAD_COLEN(x) (((x)&0x7u)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
670	#else
671	#define SET_KPAD_ROWEN(x) (((x)&0x7)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
672	#define SET_KPAD_COLEN(x) (((x)&0x7)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
673	#endif /* _MISRA_RULES */
674
675
676	/* Bit masks for KPAD_PRESCALE */
677
678	#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
679
680	#ifdef _MISRA_RULES
681	#define SET_KPAD_PRESCALE(x) ((x)&0x3Fu) /* KPAD_PRESCALE_VAL (Key Prescale). Key Prescale Value (5:0) */
682	#else
683	#define SET_KPAD_PRESCALE(x) ((x)&0x3F) /* KPAD_PRESCALE_VAL (Key Prescale). Key Prescale Value (5:0) */
684	#endif /* _MISRA_RULES */
685
686
687	/* Bit masks for KPAD_MSEL */
688
689	#define DBON_SCALE 0xff /* Debounce Scale Value */
690	#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
691
692	#ifdef _MISRA_RULES
693	#define SET_KPAD_DBON_SCALE(x) ((x)&0xFFu) /* DBON_SCALE (Debounce Scale). Debounce Delay Multiplier Select [7:0] */
694	#define SET_KPAD_COLDRV_SCALE(x) (((x)&0xFFu)<<8) /* COLDRV_SCALE (Column Driver Scale). Column Driver Period Multiplier Select [15:8] */
695	#else
696	#define SET_KPAD_DBON_SCALE(x) ((x)&0xFF) /* DBON_SCALE (Debounce Scale). Debounce Delay Multiplier Select [7:0] */
697	#define SET_KPAD_COLDRV_SCALE(x) (((x)&0xFF)<<8) /* COLDRV_SCALE (Column Driver Scale). Column Driver Period Multiplier Select [15:8] */
698	#endif /* _MISRA_RULES */
699
700
701	/* Bit masks for KPAD_ROWCOL */
702
703	#define KPAD_ROW 0xff /* Rows Pressed */
704	#define KPAD_COL 0xff00 /* Columns Pressed */
705
706	/* Bit masks for KPAD_STAT */
707
708	#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
709	#define nKPAD_IRQ 0x0
710	#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
711	#define KPAD_PRESSED 0x8 /* Key press current status */
712	#define nKPAD_PRESSED 0x0
713	#define KPAD_NO_KEY 0x0 /* No Keypress Status*/
714	#define KPAD_SINGLE_KEY 0x2 /* Single Keypress Status */
715	#define KPAD_MKSROWCOL 0x4 /* Multiple Keypress in the same row or column Status */
716	#define KPAD_MKMROWCOL 0x6 /* Multiple Keypress in the same multiple rows and multiple columns Status */
717
718	/* Bit masks for KPAD_SOFTEVAL */
719
720	#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
721	#define nKPAD_SOFTEVAL_E 0x0
722
723	/* Bit masks for SDH_COMMAND */
724
725	#define CMD_IDX 0x3f /* Command Index */
726	#define CMD_RSP 0x40 /* Response */
727	#define nCMD_RSP 0x0
728	#define CMD_L_RSP 0x80 /* Long Response */
729	#define nCMD_L_RSP 0x0
730	#define CMD_INT_E 0x100 /* Command Interrupt */
731	#define nCMD_INT_E 0x0
732	#define CMD_PEND_E 0x200 /* Command Pending */
733	#define nCMD_PEND_E 0x0
734	#define CMD_E 0x400 /* Command Enable */
735	#define nCMD_E 0x0
736
737	/* Bit masks for SDH_PWR_CTL */
738
739	#define PWR_ON 0x3 /* Power On */
740	#if 0
741	#define TBD 0x3c /* TBD */
742	#endif
743	#define SD_CMD_OD 0x40 /* Open Drain Output */
744	#define nSD_CMD_OD 0x0
745	#define ROD_CTL 0x80 /* Rod Control */
746	#define nROD_CTL 0x0
747
748	/* Bit masks for SDH_CLK_CTL */
749
750	#define CLKDIV 0xff /* MC_CLK Divisor */
751	#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
752	#define nCLK_E 0x0
753	#define PWR_SV_E 0x200 /* Power Save Enable */
754	#define nPWR_SV_E 0x0
755	#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
756	#define nCLKDIV_BYPASS 0x0
757	#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
758	#define nWIDE_BUS 0x0
759
760	/* Bit masks for SDH_RESP_CMD */
761
762	#define RESP_CMD 0x3f /* Response Command */
763
764	/* Bit masks for SDH_DATA_CTL */
765
766	#define DTX_E 0x1 /* Data Transfer Enable */
767	#define nDTX_E 0x0
768	#define DTX_DIR 0x2 /* Data Transfer Direction */
769	#define nDTX_DIR 0x0
770	#define DTX_MODE 0x4 /* Data Transfer Mode */
771	#define nDTX_MODE 0x0
772	#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
773	#define nDTX_DMA_E 0x0
774	#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
775
776	/* Bit masks for SDH_STATUS */
777
778	#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
779	#define nCMD_CRC_FAIL 0x0
780	#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
781	#define nDAT_CRC_FAIL 0x0
782	#define CMD_TIMEOUT 0x4 /* CMD Time Out */
783	#define nCMD_TIMEOUT 0x0
784	#define DAT_TIMEOUT 0x8 /* Data Time Out */
785	#define nDAT_TIMEOUT 0x0
786	#define TX_UNDERRUN 0x10 /* Transmit Underrun */
787	#define nTX_UNDERRUN 0x0
788	#define RX_OVERRUN 0x20 /* Receive Overrun */
789	#define nRX_OVERRUN 0x0
790	#define CMD_RESP_END 0x40 /* CMD Response End */
791	#define nCMD_RESP_END 0x0
792	#define CMD_SENT 0x80 /* CMD Sent */
793	#define nCMD_SENT 0x0
794	#define DAT_END 0x100 /* Data End */
795	#define nDAT_END 0x0
796	#define START_BIT_ERR 0x200 /* Start Bit Error */
797	#define nSTART_BIT_ERR 0x0
798	#define DAT_BLK_END 0x400 /* Data Block End */
799	#define nDAT_BLK_END 0x0
800	#define CMD_ACT 0x800 /* CMD Active */
801	#define nCMD_ACT 0x0
802	#define TX_ACT 0x1000 /* Transmit Active */
803	#define nTX_ACT 0x0
804	#define RX_ACT 0x2000 /* Receive Active */
805	#define nRX_ACT 0x0
806	#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
807	#define nTX_FIFO_STAT 0x0
808	#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
809	#define nRX_FIFO_STAT 0x0
810	#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
811	#define nTX_FIFO_FULL 0x0
812	#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
813	#define nRX_FIFO_FULL 0x0
814	#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
815	#define nTX_FIFO_ZERO 0x0
816	#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
817	#define nRX_DAT_ZERO 0x0
818	#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
819	#define nTX_DAT_RDY 0x0
820	#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
821	#define nRX_FIFO_RDY 0x0
822
823	/* Bit masks for SDH_STATUS_CLR */
824
825	#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
826	#define nCMD_CRC_FAIL_STAT 0x0
827	#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
828	#define nDAT_CRC_FAIL_STAT 0x0
829	#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
830	#define nCMD_TIMEOUT_STAT 0x0
831	#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
832	#define nDAT_TIMEOUT_STAT 0x0
833	#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
834	#define nTX_UNDERRUN_STAT 0x0
835	#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
836	#define nRX_OVERRUN_STAT 0x0
837	#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
838	#define nCMD_RESP_END_STAT 0x0
839	#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
840	#define nCMD_SENT_STAT 0x0
841	#define DAT_END_STAT 0x100 /* Data End Status */
842	#define nDAT_END_STAT 0x0
843	#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
844	#define nSTART_BIT_ERR_STAT 0x0
845	#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
846	#define nDAT_BLK_END_STAT 0x0
847
848	/* Bit masks for SDH_MASK0 */
849
850	#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
851	#define nCMD_CRC_FAIL_MASK 0x0
852	#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
853	#define nDAT_CRC_FAIL_MASK 0x0
854	#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
855	#define nCMD_TIMEOUT_MASK 0x0
856	#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
857	#define nDAT_TIMEOUT_MASK 0x0
858	#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
859	#define nTX_UNDERRUN_MASK 0x0
860	#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
861	#define nRX_OVERRUN_MASK 0x0
862	#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
863	#define nCMD_RESP_END_MASK 0x0
864	#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
865	#define nCMD_SENT_MASK 0x0
866	#define DAT_END_MASK 0x100 /* Data End Mask */
867	#define nDAT_END_MASK 0x0
868	#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
869	#define nSTART_BIT_ERR_MASK 0x0
870	#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
871	#define nDAT_BLK_END_MASK 0x0
872	#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
873	#define nCMD_ACT_MASK 0x0
874	#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
875	#define nTX_ACT_MASK 0x0
876	#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
877	#define nRX_ACT_MASK 0x0
878	#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
879	#define nTX_FIFO_STAT_MASK 0x0
880	#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
881	#define nRX_FIFO_STAT_MASK 0x0
882	#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
883	#define nTX_FIFO_FULL_MASK 0x0
884	#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
885	#define nRX_FIFO_FULL_MASK 0x0
886	#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
887	#define nTX_FIFO_ZERO_MASK 0x0
888	#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
889	#define nRX_DAT_ZERO_MASK 0x0
890	#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
891	#define nTX_DAT_RDY_MASK 0x0
892	#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
893	#define nRX_FIFO_RDY_MASK 0x0
894
895	/* Bit masks for SDH_FIFO_CNT */
896
897	#define FIFO_COUNT 0x7fff /* FIFO Count */
898
899	/* Bit masks for SDH_E_STATUS */
900
901	#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
902	#define nSDIO_INT_DET 0x0
903	#define SD_CARD_DET 0x10 /* SD Card Detect */
904	#define nSD_CARD_DET 0x0
905
906	/* Bit masks for SDH_E_MASK */
907
908	#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
909	#define nSDIO_MSK 0x0
910	#define SCD_MSK 0x40 /* Mask Card Detect */
911	#define nSCD_MSK 0x0
912
913	/* Bit masks for SDH_CFG */
914
915	#define CLKS_EN 0x1 /* Clocks Enable */
916	#define nCLKS_EN 0x0
917	#define SD4E 0x4 /* SDIO 4-Bit Enable */
918	#define nSD4E 0x0
919	#define MWE 0x8 /* Moving Window Enable */
920	#define nMWE 0x0
921	#define SD_RST 0x10 /* SDMMC Reset */
922	#define nSD_RST 0x0
923	#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
924	#define nPUP_SDDAT 0x0
925	#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
926	#define nPUP_SDDAT3 0x0
927	#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
928	#define nPD_SDDAT3 0x0
929
930	/* Bit masks for SDH_RD_WAIT_EN */
931
932	#define RWR 0x1 /* Read Wait Request */
933	#define nRWR 0x0
934
935	/* Bit masks for ATAPI_CONTROL */
936
937	#define PIO_START 0x1 /* Start PIO/Reg Op */
938	#define nPIO_START 0x0
939	#define MULTI_START 0x2 /* Start Multi-DMA Op */
940	#define nMULTI_START 0x0
941	#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
942	#define nULTRA_START 0x0
943	#define XFER_DIR 0x8 /* Transfer Direction */
944	#define nXFER_DIR 0x0
945	#define IORDY_EN 0x10 /* IORDY Enable */
946	#define nIORDY_EN 0x0
947	#define FIFO_FLUSH 0x20 /* Flush FIFOs */
948	#define nFIFO_FLUSH 0x0
949	#define SOFT_RST 0x40 /* Soft Reset */
950	#define nSOFT_RST 0x0
951	#define DEV_RST 0x80 /* Device Reset */
952	#define nDEV_RST 0x0
953	#define TFRCNT_RST 0x100 /* Trans Count Reset */
954	#define nTFRCNT_RST 0x0
955	#define END_ON_TERM 0x200 /* End/Terminate Select */
956	#define nEND_ON_TERM 0x0
957	#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
958	#define nPIO_USE_DMA 0x0
959	#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
960
961	/* Bit masks for ATAPI_STATUS */
962
963	#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
964	#define nPIO_XFER_ON 0x0
965	#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
966	#define nMULTI_XFER_ON 0x0
967	#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
968	#define nULTRA_XFER_ON 0x0
969	#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
970
971	/* Bit masks for ATAPI_DEV_ADDR */
972
973	#define DEV_ADDR 0x1f /* Device Address */
974
975	/* Bit masks for ATAPI_INT_MASK */
976
977	#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
978	#define nATAPI_DEV_INT_MASK 0x0
979	#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
980	#define nPIO_DONE_MASK 0x0
981	#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
982	#define nMULTI_DONE_MASK 0x0
983	#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
984	#define nUDMAIN_DONE_MASK 0x0
985	#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
986	#define nUDMAOUT_DONE_MASK 0x0
987	#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
988	#define nHOST_TERM_XFER_MASK 0x0
989	#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
990	#define nMULTI_TERM_MASK 0x0
991	#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
992	#define nUDMAIN_TERM_MASK 0x0
993	#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
994	#define nUDMAOUT_TERM_MASK 0x0
995
996	/* Bit masks for ATAPI_INT_STATUS */
997
998	#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
999	#define nATAPI_DEV_INT 0x0
1000	#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
1001	#define nPIO_DONE_INT 0x0
1002	#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
1003	#define nMULTI_DONE_INT 0x0
1004	#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
1005	#define nUDMAIN_DONE_INT 0x0
1006	#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
1007	#define nUDMAOUT_DONE_INT 0x0
1008	#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
1009	#define nHOST_TERM_XFER_INT 0x0
1010	#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
1011	#define nMULTI_TERM_INT 0x0
1012	#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
1013	#define nUDMAIN_TERM_INT 0x0
1014	#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
1015	#define nUDMAOUT_TERM_INT 0x0
1016
1017	/* Bit masks for ATAPI_LINE_STATUS */
1018
1019	#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
1020	#define nATAPI_INTR 0x0
1021	#define ATAPI_DASP 0x2 /* Device dasp to host line status */
1022	#define nATAPI_DASP 0x0
1023	#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
1024	#define nATAPI_CS0N 0x0
1025	#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
1026	#define nATAPI_CS1N 0x0
1027	#define ATAPI_ADDR 0x70 /* ATAPI address line status */
1028	#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
1029	#define nATAPI_DMAREQ 0x0
1030	#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
1031	#define nATAPI_DMAACKN 0x0
1032	#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
1033	#define nATAPI_DIOWN 0x0
1034	#define ATAPI_DIORN 0x400 /* ATAPI read line status */
1035	#define nATAPI_DIORN 0x0
1036	#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
1037	#define nATAPI_IORDY 0x0
1038
1039	/* Bit masks for ATAPI_SM_STATE */
1040
1041	#define PIO_CSTATE 0xf /* PIO mode state machine current state */
1042	#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
1043	#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
1044	#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
1045
1046	/* Bit masks for ATAPI_TERMINATE */
1047
1048	#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
1049	#define nATAPI_HOST_TERM 0x0
1050
1051	/* Bit masks for ATAPI_REG_TIM_0 */
1052
1053	#define T2_REG 0xff /* End of cycle time for register access transfers */
1054	#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
1055
1056	/* Bit masks for ATAPI_PIO_TIM_0 */
1057
1058	#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
1059	#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
1060	#define T4_REG 0xf000 /* DIOW data hold */
1061
1062	/* Bit masks for ATAPI_PIO_TIM_1 */
1063
1064	#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
1065
1066	/* Bit masks for ATAPI_MULTI_TIM_0 */
1067
1068	#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
1069	#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
1070
1071	/* Bit masks for ATAPI_MULTI_TIM_1 */
1072
1073	#define TKW 0xff /* Selects DIOW negated pulsewidth */
1074	#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
1075
1076	/* Bit masks for ATAPI_MULTI_TIM_2 */
1077
1078	#define TH 0xff /* Selects DIOW data hold */
1079	#define TEOC 0xff00 /* Selects end of cycle for DMA */
1080
1081	/* Bit masks for ATAPI_ULTRA_TIM_0 */
1082
1083	#define TACK 0xff /* Selects setup and hold times for TACK */
1084	#define TENV 0xff00 /* Selects envelope time */
1085
1086	/* Bit masks for ATAPI_ULTRA_TIM_1 */
1087
1088	#define TDVS 0xff /* Selects data valid setup time */
1089	#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
1090
1091	/* Bit masks for ATAPI_ULTRA_TIM_2 */
1092
1093	#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
1094	#define TMLI 0xff00 /* Selects interlock time */
1095
1096	/* Bit masks for ATAPI_ULTRA_TIM_3 */
1097
1098	#define TZAH 0xff /* Selects minimum delay required for output */
1099	#define READY_PAUSE 0xff00 /* Selects ready to pause */
1100
1101	/* Bit masks for TIMER_ENABLE1 */
1102
1103	#define TIMEN8 0x1 /* Timer 8 Enable */
1104	#define nTIMEN8 0x0
1105	#define TIMEN9 0x2 /* Timer 9 Enable */
1106	#define nTIMEN9 0x0
1107	#define TIMEN10 0x4 /* Timer 10 Enable */
1108	#define nTIMEN10 0x0
1109
1110	/* Bit masks for TIMER_DISABLE1 */
1111
1112	#define TIMDIS8 0x1 /* Timer 8 Disable */
1113	#define nTIMDIS8 0x0
1114	#define TIMDIS9 0x2 /* Timer 9 Disable */
1115	#define nTIMDIS9 0x0
1116	#define TIMDIS10 0x4 /* Timer 10 Disable */
1117	#define nTIMDIS10 0x0
1118
1119	/* Bit masks for TIMER_STATUS1 */
1120
1121	#define TIMIL8 0x1 /* Timer 8 Interrupt */
1122	#define nTIMIL8 0x0
1123	#define TIMIL9 0x2 /* Timer 9 Interrupt */
1124	#define nTIMIL9 0x0
1125	#define TIMIL10 0x4 /* Timer 10 Interrupt */
1126	#define nTIMIL10 0x0
1127	#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
1128	#define nTOVF_ERR8 0x0
1129	#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
1130	#define nTOVF_ERR9 0x0
1131	#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
1132	#define nTOVF_ERR10 0x0
1133	#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
1134	#define nTRUN8 0x0
1135	#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
1136	#define nTRUN9 0x0
1137	#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
1138	#define nTRUN10 0x0
1139
1140	/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
1141
1142	/* Bit masks for USB_FADDR */
1143
1144	#define FUNCTION_ADDRESS 0x7f /* Function address */
1145
1146	/* Bit masks for USB_POWER */
1147
1148	#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
1149	#define nENABLE_SUSPENDM 0x0
1150	#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
1151	#define nSUSPEND_MODE 0x0
1152	#define RESUME_MODE 0x4 /* DMA Mode */
1153	#define nRESUME_MODE 0x0
1154	#define RESET 0x8 /* Reset indicator */
1155	#define nRESET 0x0
1156	#define HS_MODE 0x10 /* High Speed mode indicator */
1157	#define nHS_MODE 0x0
1158	#define HS_ENABLE 0x20 /* high Speed Enable */
1159	#define nHS_ENABLE 0x0
1160	#define SOFT_CONN 0x40 /* Soft connect */
1161	#define nSOFT_CONN 0x0
1162	#define ISO_UPDATE 0x80 /* Isochronous update */
1163	#define nISO_UPDATE 0x0
1164
1165	/* Bit masks for USB_INTRTX */
1166
1167	#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
1168	#define nEP0_TX 0x0
1169	#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
1170	#define nEP1_TX 0x0
1171	#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
1172	#define nEP2_TX 0x0
1173	#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
1174	#define nEP3_TX 0x0
1175	#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
1176	#define nEP4_TX 0x0
1177	#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
1178	#define nEP5_TX 0x0
1179	#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
1180	#define nEP6_TX 0x0
1181	#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
1182	#define nEP7_TX 0x0
1183
1184	/* Bit masks for USB_INTRRX */
1185
1186	#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
1187	#define nEP1_RX 0x0
1188	#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
1189	#define nEP2_RX 0x0
1190	#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
1191	#define nEP3_RX 0x0
1192	#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
1193	#define nEP4_RX 0x0
1194	#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
1195	#define nEP5_RX 0x0
1196	#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
1197	#define nEP6_RX 0x0
1198	#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
1199	#define nEP7_RX 0x0
1200
1201	/* Bit masks for USB_INTRTXE */
1202
1203	#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
1204	#define nEP0_TX_E 0x0
1205	#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
1206	#define nEP1_TX_E 0x0
1207	#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
1208	#define nEP2_TX_E 0x0
1209	#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
1210	#define nEP3_TX_E 0x0
1211	#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
1212	#define nEP4_TX_E 0x0
1213	#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
1214	#define nEP5_TX_E 0x0
1215	#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
1216	#define nEP6_TX_E 0x0
1217	#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
1218	#define nEP7_TX_E 0x0
1219
1220	/* Bit masks for USB_INTRRXE */
1221
1222	#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
1223	#define nEP1_RX_E 0x0
1224	#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
1225	#define nEP2_RX_E 0x0
1226	#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
1227	#define nEP3_RX_E 0x0
1228	#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
1229	#define nEP4_RX_E 0x0
1230	#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
1231	#define nEP5_RX_E 0x0
1232	#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
1233	#define nEP6_RX_E 0x0
1234	#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
1235	#define nEP7_RX_E 0x0
1236
1237	/* Bit masks for USB_INTRUSB */
1238
1239	#define SUSPEND_B 0x1 /* Suspend indicator */
1240	#define nSUSPEND_B 0x0
1241	#define RESUME_B 0x2 /* Resume indicator */
1242	#define nRESUME_B 0x0
1243	#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
1244	#define nRESET_OR_BABLE_B 0x0
1245	#define SOF_B 0x8 /* Start of frame */
1246	#define nSOF_B 0x0
1247	#define CONN_B 0x10 /* Connection indicator */
1248	#define nCONN_B 0x0
1249	#define DISCON_B 0x20 /* Disconnect indicator */
1250	#define nDISCON_B 0x0
1251	#define SESSION_REQ_B 0x40 /* Session Request */
1252	#define nSESSION_REQ_B 0x0
1253	#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
1254	#define nVBUS_ERROR_B 0x0
1255
1256	/* Bit masks for USB_INTRUSBE */
1257
1258	#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
1259	#define nSUSPEND_BE 0x0
1260	#define RESUME_BE 0x2 /* Resume indicator int enable */
1261	#define nRESUME_BE 0x0
1262	#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
1263	#define nRESET_OR_BABLE_BE 0x0
1264	#define SOF_BE 0x8 /* Start of frame int enable */
1265	#define nSOF_BE 0x0
1266	#define CONN_BE 0x10 /* Connection indicator int enable */
1267	#define nCONN_BE 0x0
1268	#define DISCON_BE 0x20 /* Disconnect indicator int enable */
1269	#define nDISCON_BE 0x0
1270	#define SESSION_REQ_BE 0x40 /* Session Request int enable */
1271	#define nSESSION_REQ_BE 0x0
1272	#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
1273	#define nVBUS_ERROR_BE 0x0
1274
1275	/* Bit masks for USB_FRAME */
1276
1277	#define FRAME_NUMBER 0x7ff /* Frame number */
1278
1279	/* Bit masks for USB_INDEX */
1280
1281	#define SELECTED_ENDPOINT 0xf /* selected endpoint */
1282
1283	/* Bit masks for USB_GLOBAL_CTL */
1284
1285	#define GLOBAL_ENA 0x1 /* enables USB module */
1286	#define nGLOBAL_ENA 0x0
1287	#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
1288	#define nEP1_TX_ENA 0x0
1289	#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
1290	#define nEP2_TX_ENA 0x0
1291	#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
1292	#define nEP3_TX_ENA 0x0
1293	#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
1294	#define nEP4_TX_ENA 0x0
1295	#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
1296	#define nEP5_TX_ENA 0x0
1297	#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
1298	#define nEP6_TX_ENA 0x0
1299	#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
1300	#define nEP7_TX_ENA 0x0
1301	#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
1302	#define nEP1_RX_ENA 0x0
1303	#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
1304	#define nEP2_RX_ENA 0x0
1305	#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
1306	#define nEP3_RX_ENA 0x0
1307	#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
1308	#define nEP4_RX_ENA 0x0
1309	#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
1310	#define nEP5_RX_ENA 0x0
1311	#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
1312	#define nEP6_RX_ENA 0x0
1313	#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
1314	#define nEP7_RX_ENA 0x0
1315
1316	/* Bit masks for USB_OTG_DEV_CTL */
1317
1318	#define SESSION 0x1 /* session indicator */
1319	#define nSESSION 0x0
1320	#define HOST_REQ 0x2 /* Host negotiation request */
1321	#define nHOST_REQ 0x0
1322	#define HOST_MODE 0x4 /* indicates USBDRC is a host */
1323	#define nHOST_MODE 0x0
1324	#define VBUS0 0x8 /* Vbus level indicator[0] */
1325	#define nVBUS0 0x0
1326	#define VBUS1 0x10 /* Vbus level indicator[1] */
1327	#define nVBUS1 0x0
1328	#define LSDEV 0x20 /* Low-speed indicator */
1329	#define nLSDEV 0x0
1330	#define FSDEV 0x40 /* Full or High-speed indicator */
1331	#define nFSDEV 0x0
1332	#define B_DEVICE 0x80 /* A' or 'B' device indicator */
1333	#define nB_DEVICE 0x0
1334
1335	/* Bit masks for USB_OTG_VBUS_IRQ */
1336
1337	#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
1338	#define nDRIVE_VBUS_ON 0x0
1339	#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
1340	#define nDRIVE_VBUS_OFF 0x0
1341	#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
1342	#define nCHRG_VBUS_START 0x0
1343	#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
1344	#define nCHRG_VBUS_END 0x0
1345	#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
1346	#define nDISCHRG_VBUS_START 0x0
1347	#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
1348	#define nDISCHRG_VBUS_END 0x0
1349
1350	/* Bit masks for USB_OTG_VBUS_MASK */
1351
1352	#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
1353	#define nDRIVE_VBUS_ON_ENA 0x0
1354	#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
1355	#define nDRIVE_VBUS_OFF_ENA 0x0
1356	#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
1357	#define nCHRG_VBUS_START_ENA 0x0
1358	#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
1359	#define nCHRG_VBUS_END_ENA 0x0
1360	#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
1361	#define nDISCHRG_VBUS_START_ENA 0x0
1362	#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
1363	#define nDISCHRG_VBUS_END_ENA 0x0
1364
1365	/* Bit masks for USB_CSR0 */
1366
1367	#define RXPKTRDY 0x1 /* data packet receive indicator */
1368	#define nRXPKTRDY 0x0
1369	#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
1370	#define nTXPKTRDY 0x0
1371	#define STALL_SENT 0x4 /* STALL handshake sent */
1372	#define nSTALL_SENT 0x0
1373	#define DATAEND 0x8 /* Data end indicator */
1374	#define nDATAEND 0x0
1375	#define SETUPEND 0x10 /* Setup end */
1376	#define nSETUPEND 0x0
1377	#define SENDSTALL 0x20 /* Send STALL handshake */
1378	#define nSENDSTALL 0x0
1379	#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
1380	#define nSERVICED_RXPKTRDY 0x0
1381	#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
1382	#define nSERVICED_SETUPEND 0x0
1383	#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
1384	#define nFLUSHFIFO 0x0
1385	#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
1386	#define nSTALL_RECEIVED_H 0x0
1387	#define SETUPPKT_H 0x8 /* send Setup token host mode */
1388	#define nSETUPPKT_H 0x0
1389	#define ERROR_H 0x10 /* timeout error indicator host mode */
1390	#define nERROR_H 0x0
1391	#define REQPKT_H 0x20 /* Request an IN transaction host mode */
1392	#define nREQPKT_H 0x0
1393	#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
1394	#define nSTATUSPKT_H 0x0
1395	#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
1396	#define nNAK_TIMEOUT_H 0x0
1397
1398	/* Bit masks for USB_COUNT0 */
1399
1400	#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
1401
1402	/* Bit masks for USB_NAKLIMIT0 */
1403
1404	#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
1405
1406	/* Bit masks for USB_TX_MAX_PACKET */
1407
1408	#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
1409
1410	/* Bit masks for USB_RX_MAX_PACKET */
1411
1412	#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
1413
1414	/* Bit masks for USB_TXCSR */
1415
1416	#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
1417	#define nTXPKTRDY_T 0x0
1418	#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
1419	#define nFIFO_NOT_EMPTY_T 0x0
1420	#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
1421	#define nUNDERRUN_T 0x0
1422	#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
1423	#define nFLUSHFIFO_T 0x0
1424	#define STALL_SEND_T 0x10 /* issue a Stall handshake */
1425	#define nSTALL_SEND_T 0x0
1426	#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
1427	#define nSTALL_SENT_T 0x0
1428	#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
1429	#define nCLEAR_DATATOGGLE_T 0x0
1430	#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
1431	#define nINCOMPTX_T 0x0
1432	#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
1433	#define nDMAREQMODE_T 0x0
1434	#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
1435	#define nFORCE_DATATOGGLE_T 0x0
1436	#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
1437	#define nDMAREQ_ENA_T 0x0
1438	#define ISO_T 0x4000 /* enable Isochronous transfers */
1439	#define nISO_T 0x0
1440	#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
1441	#define nAUTOSET_T 0x0
1442	#define ERROR_TH 0x4 /* error condition host mode */
1443	#define nERROR_TH 0x0
1444	#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
1445	#define nSTALL_RECEIVED_TH 0x0
1446	#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
1447	#define nNAK_TIMEOUT_TH 0x0
1448
1449	/* Bit masks for USB_TXCOUNT */
1450
1451	#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
1452
1453	/* Bit masks for USB_RXCSR */
1454
1455	#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
1456	#define nRXPKTRDY_R 0x0
1457	#define FIFO_FULL_R 0x2 /* FIFO not empty */
1458	#define nFIFO_FULL_R 0x0
1459	#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
1460	#define nOVERRUN_R 0x0
1461	#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
1462	#define nDATAERROR_R 0x0
1463	#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
1464	#define nFLUSHFIFO_R 0x0
1465	#define STALL_SEND_R 0x20 /* issue a Stall handshake */
1466	#define nSTALL_SEND_R 0x0
1467	#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
1468	#define nSTALL_SENT_R 0x0
1469	#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
1470	#define nCLEAR_DATATOGGLE_R 0x0
1471	#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
1472	#define nINCOMPRX_R 0x0
1473	#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
1474	#define nDMAREQMODE_R 0x0
1475	#define DISNYET_R 0x1000 /* disable Nyet handshakes */
1476	#define nDISNYET_R 0x0
1477	#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
1478	#define nDMAREQ_ENA_R 0x0
1479	#define ISO_R 0x4000 /* enable Isochronous transfers */
1480	#define nISO_R 0x0
1481	#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
1482	#define nAUTOCLEAR_R 0x0
1483	#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
1484	#define nERROR_RH 0x0
1485	#define REQPKT_RH 0x20 /* request an IN transaction host mode */
1486	#define nREQPKT_RH 0x0
1487	#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
1488	#define nSTALL_RECEIVED_RH 0x0
1489	#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
1490	#define nINCOMPRX_RH 0x0
1491	#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
1492	#define nDMAREQMODE_RH 0x0
1493	#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
1494	#define nAUTOREQ_RH 0x0
1495
1496	/* Bit masks for USB_RXCOUNT */
1497
1498	#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
1499
1500	/* Bit masks for USB_TXTYPE */
1501
1502	#define TARGET_EP_NO_T 0xf /* EP number */
1503	#define PROTOCOL_T 0xc /* transfer type */
1504
1505	/* Bit masks for USB_TXINTERVAL */
1506
1507	#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
1508
1509	/* Bit masks for USB_RXTYPE */
1510
1511	#define TARGET_EP_NO_R 0xf /* EP number */
1512	#define PROTOCOL_R 0xc /* transfer type */
1513
1514	/* Bit masks for USB_RXINTERVAL */
1515
1516	#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
1517
1518	/* Bit masks for USB_DMA_INTERRUPT */
1519
1520	#define DMA0_INT 0x1 /* DMA0 pending interrupt */
1521	#define nDMA0_INT 0x0
1522	#define DMA1_INT 0x2 /* DMA1 pending interrupt */
1523	#define nDMA1_INT 0x0
1524	#define DMA2_INT 0x4 /* DMA2 pending interrupt */
1525	#define nDMA2_INT 0x0
1526	#define DMA3_INT 0x8 /* DMA3 pending interrupt */
1527	#define nDMA3_INT 0x0
1528	#define DMA4_INT 0x10 /* DMA4 pending interrupt */
1529	#define nDMA4_INT 0x0
1530	#define DMA5_INT 0x20 /* DMA5 pending interrupt */
1531	#define nDMA5_INT 0x0
1532	#define DMA6_INT 0x40 /* DMA6 pending interrupt */
1533	#define nDMA6_INT 0x0
1534	#define DMA7_INT 0x80 /* DMA7 pending interrupt */
1535	#define nDMA7_INT 0x0
1536
1537	/* Bit masks for USB_DMAxCONTROL */
1538
1539	#define DMA_ENA 0x1 /* DMA enable */
1540	#define nDMA_ENA 0x0
1541	#define DIRECTION 0x2 /* direction of DMA transfer */
1542	#define nDIRECTION 0x0
1543	#define MODE 0x4 /* DMA Bus error */
1544	#define nMODE 0x0
1545	#define INT_ENA 0x8 /* Interrupt enable */
1546	#define nINT_ENA 0x0
1547	#define EPNUM 0xf0 /* EP number */
1548	#define BUSERROR 0x100 /* DMA Bus error */
1549	#define nBUSERROR 0x0
1550
1551	/* Bit masks for USB_DMAxADDRHIGH */
1552
1553	#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
1554
1555	/* Bit masks for USB_DMAxADDRLOW */
1556
1557	#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
1558
1559	/* Bit masks for USB_DMAxCOUNTHIGH */
1560
1561	#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
1562
1563	/* Bit masks for USB_DMAxCOUNTLOW */
1564
1565	#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
1566
1567	/* ******************************************* */
1568	/* MULTI BIT MACRO ENUMERATIONS */
1569	/* ******************************************* */
1570
1571	#ifdef _MISRA_RULES
1572	#pragma diag(pop)
1573	#endif /* _MISRA_RULES */
1574
1575	#endif /* _DEF_BF547_H */

Note: See TracBrowser for help on using the repository browser.

Context Navigation

source: trunk/libs/newlib/src/libgloss/bfin/include/defBF547.h @ 444

Download in other formats: