source: trunk/libs/newlib/src/libgloss/mt/startup-64-001.S @ 450

Last change on this file since 450 was 444, checked in by satin@…, 6 years ago

add newlib,libalmos-mkh, restructure shared_syscalls.h and mini-libc
File size: 8.8 KB
Line 
1/*
2 * $Header$
3 *
4 * interrupt_vectors.s -- the interrupt handler jump table.
5 *
6 *
7 * There are a total of 32 interrupt vector possible, however, only
8 *   11 of those are currently used (the others are reserved). The
9 *   order of vectors is as follows:
10 *
11 *     1. Boot Vector. Vector for power-on/reset.
12 *     2. Software Vector. Vector for handling the SI instruction (an
13 *          explicit interrupt caused by software).
14 *     3. Break Vector. Vector for handling the Break instruction.
15 *     4. Device 0 Vector. Service vector for device zero.
16 *     5. Device 1 Vector. Service vector for device one.
17 *     6. Device 2 Vector. Service vector for device two.
18 *     7. Device 3 Vector. Service vector for device three.
19 *     8. Device 4 Vector. Service vector for device four.
20 *     9. Device 5 Vector. Service vector for device five.
21 *    10. Device 6 Vector. Service vector for device six.
22 *    11. Device 7 Vector. Service vector for device seven.
23 *
24 *   The rest of the interrupt vectors are reserved for future use.
25 *
26 *
27 * Each jump table entry consists of the following two instructions:
28 *
29 *   jmp Label          ; Label as appropriate
30 *   nop                ; implemented as or r0,r0,r0
31 *
32 *   The following labels are reserved for the vectors named above,
33 *   respectively:
34 *
35 *     _BOOTIVEC, _SOFTIVEC, _BRKIVEC, _DEV0IVEC, _DEV1IVEC, _DEV2IVEC,
36 *     _DEV3IVEC, _DEV4IVEC, _DEV5IVEC, _DEV6IVEC, _DEV7IVEC
37 *
38 *
39 *   26Sep01 (DJK) The memory map is changed and the device interrupts are
40 *                   now memory-mapped.
41 *
42 *   10Oct01 (DJK) The memory map is finalized and the first 4K of address
43 *                   space is now reserved for memory-mapped I/O devices.
44 *                   (There is over 2K unused, reserved space in this area.)
45 *
46 *   27Jul02 (DJK) Fixed the address for the interrupt mask register. Old
47 *                   documentation stated the port address as 0x140, but
48 *                   the implementation uses 0x13c.
49 *
50 *   30Jul02 (DJK) Added support for printf. This only supports output to
51 *                   stderr and stdout. Using the message box interface,
52 *                   a (newly defined) message or series of messages is
53 *                   passed to the controller to output bytes as text to
54 *                   the debug console. These messages are constructed in
55 *                   the interrupt handler for the SI instruction.
56 *                   With this implementation, the user is unable to
57 *                   utilize the message box interface in applications as
58 *                   specialized interrupt handlers for the external
59 *                   interrupts are necessary.
60 *
61 *
62 *
63 * Copyright (c) 2001, 2002, 2003, 2004 Morpho Technologies, Inc.
64 *
65 */
66
67        .section .startup, "a", @progbits
68        .global __boot_start
69_INTERRUPT_VECTOR_TABLE:
70__boot_start:
71        jmp     _BOOTIVEC               ; Boot vector
72        or      r0, r0, r0
73        jmp     _SOFTIVEC               ; Vector for SI instruction
74        or      r0,r0,r0
75        jmp     _BRKIVEC                ; Vector for Break instruction
76        or      r0,r0,r0
77
78
79        ; This is the memory-mapped I/O region.
80
81        ; Hardware Interrupt Registers
82        .org 0x100
83        .global _DEV0_INTERRUPT_REG
84_DEV0_INTERRUPT_REG:
85        .word 0x00000000
86
87        .global _DEV1_INTERRUPT_REG
88_DEV1_INTERRUPT_REG:
89        .word 0x00000000
90
91        .global _DEV2_INTERRUPT_REG
92_DEV2_INTERRUPT_REG:
93        .word 0x00000000
94
95        .global _DEV3_INTERRUPT_REG
96_DEV3_INTERRUPT_REG:
97        .word 0x00000000
98
99        .global _DEV4_INTERRUPT_REG
100_DEV4_INTERRUPT_REG:
101        .word 0x00000000
102
103        .global _DEV5_INTERRUPT_REG
104_DEV5_INTERRUPT_REG:
105        .word 0x00000000
106
107        .global _DEV6_INTERRUPT_REG
108_DEV6_INTERRUPT_REG:
109        .word 0x00000000
110
111        .global _DEV7_INTERRUPT_REG
112_DEV7_INTERRUPT_REG:
113        .word 0x00000000
114
115        ; 60 bytes minus eight registers (four bytes per register)
116        .fill (60 - 8 * 4)
117
118        .global _INTERRUPT_MASK_REG
119_INTERRUPT_MASK_REG:
120        .word 0x00000000
121
122        ; 256 bytes minus sixteen registers (four bytes per register)
123        .fill (256 - 16 * 4)
124
125
126
127        .org 0x200
128        ; MorphoSys Decoder Registers
129        .global _MS_DEC_AUTO_INCREMENT_REG
130_MS_DEC_AUTO_INCREMENT_REG:
131        .word 0x00000000
132
133        .global _MS_DEC_SKIP_FACTOR_REG
134_MS_DEC_SKIP_FACTOR_REG:
135        .word 0x00000000
136
137        .global _MS_DEC_CUSTOM_PERMUTATION_REG
138_MS_DEC_CUSTOM_PERMUTATION_REG:
139        .word 0x00000000
140
141        .global _MS_DEC_CONTEXT_BASE_REG
142_MS_DEC_CONTEXT_BASE_REG:
143        .word 0x00000000
144
145        .global _MS_DEC_LOOKUP_TABLE_BASE_REG
146_MS_DEC_LOOKUP_TABLE_BASE_REG:
147        .word 0x00000000
148
149        .global _MS_CIRCULAR_BUFFER_END_REG
150_MS_CIRCULAR_BUFFER_END_REG:
151        .word (__FRAME_BUFFER_END)
152
153        .global _MS_CIRCULAR_BUFFER_SIZE_REG
154_MS_CIRCULAR_BUFFER_SIZE_REG:
155        .word __FRAME_BUFFER_SIZE
156
157        .global _MS_DATA_BLOCK_END_REG
158_MS_DATA_BLOCK_END_REG:
159        .word 0x00000000
160
161        .global _MS_DATA_BLOCK_SIZE_REG
162_MS_DATA_BLOCK_SIZE_REG:
163        .word 0x00000000
164
165        ; 256 bytes minus nine registers (four bytes per register)
166        .fill (256 - 9 * 4)
167
168
169
170        .org 0x300
171        ; Debug Registers
172        .global _DEBUG_HALT_REG
173_DEBUG_HALT_REG:
174        .word 0x00000000
175
176        .global _DEBUG_BREAK_REG
177_DEBUG_BREAK_REG:
178        .word 0x00000000
179
180        .global _DEBUG_HW_RESERVED0_REG
181_DEBUG_HW_RESERVED0_REG:
182        .word 0x00000000
183
184        .global _DEBUG_HW_RESERVED1_REG
185_DEBUG_HW_RESERVED1_REG:
186        .word 0x00000000
187
188        .global _DEBUG_HW_RESERVED2_REG
189_DEBUG_HW_RESERVED2_REG:
190        .word 0x00000000
191
192        .global _DEBUG_HW_RESERVED3_REG
193_DEBUG_HW_RESERVED3_REG:
194        .word 0x00000000
195
196        .global _DEBUG_HW_RESERVED4_REG
197_DEBUG_HW_RESERVED4_REG:
198        .word 0x00000000
199
200        .global _DEBUG_SW_SYSREQ_REG
201_DEBUG_SW_SYSREQ_REG:
202        .word 0x00000000
203
204        ; 256 bytes minus eight registers (four bytes per register)
205        .fill (256 - 8 * 4)
206
207
208
209        .org 0x400
210        ; Sequence Generator Registers
211_SEQ_GEN_REGS:
212        .fill 256
213
214
215
216        .org 0x500
217_RESERVED_SEQ_GEN_REGS:
218        .fill 256
219
220
221
222        .org 0x600
223        .global _TIMER0_VAL_REG
224_TIMER0_VAL_REG:
225        .word 0x00000000
226
227        .global _TIMER0_CTRL_REG
228_TIMER0_CTRL_REG:
229        .word 0x00000000
230
231        .global _TIMER1_VAL_REG
232_TIMER1_VAL_REG:
233        .word 0x00000000
234
235        .global _TIMER1_CTRL_REG
236_TIMER1_CTRL_REG:
237        .word 0x00000000
238
239        .global _TIMER2_VAL_REG
240_TIMER2_VAL_REG:
241        .word 0x00000000
242
243        .global _TIMER2_CTRL_REG
244_TIMER2_CTRL_REG:
245        .word 0x00000000
246
247        ; 256 bytes minus six registers (four bytes per register)
248        .fill (256 - 6 * 4)
249
250
251
252        .org 0x700
253        .global _OUTPUT0_CONTROL
254_OUTPUT0_CONTROL:
255        .word 0x00000000
256
257        .global _OUTPUT1_CONTROL
258_OUTPUT1_CONTROL:
259        .word 0x00000000
260
261        .global _OUTPUT2_CONTROL
262_OUTPUT2_CONTROL:
263        .word 0x00000000
264
265        .global _OUTPUT3_CONTROL
266_OUTPUT3_CONTROL:
267        .word 0x00000000
268
269        .global _OUTPUT4_CONTROL
270_OUTPUT4_CONTROL:
271        .word 0x00000000
272
273        .global _OUTPUT5_CONTROL
274_OUTPUT5_CONTROL:
275        .word 0x00000000
276
277        .global _OUTPUT6_CONTROL
278_OUTPUT6_CONTROL:
279        .word 0x00000000
280
281        .global _OUTPUT7_CONTROL
282_OUTPUT7_CONTROL:
283        .word 0x00000000
284
285        ; 256 bytes minus eight registers (four bytes per register)
286        .fill (256 - 8 * 4)
287
288
289
290        .org 0x800
291        ; Reserved memory-mapped space.
292        .fill (0x1000 - 0x800)
293
294
295
296        .text
297
298        .equ SI_IOPORT_ADR, _DEBUG_SW_SYSREQ_REG
299        .equ SI_IOPORT_BIT, 0x1
300        .equ BRK_IOPORT_ADR, _DEBUG_BREAK_REG
301        .equ BRK_IOPORT_BIT, 0x1
302
303        .global _BOOTIVEC
304_BOOTIVEC:
305
306        ; Initialize the interrupt controller's interrupt vector registers
307        ; for devices zero through seven.
308        ldui    r1, #%hi16(_IVEC_DEFAULT)
309        ori     r1, r1, #%lo16(_IVEC_DEFAULT)
310        stw     r1, r0, #%lo16(_DEV0_INTERRUPT_REG)
311        stw     r1, r0, #%lo16(_DEV1_INTERRUPT_REG)
312        stw     r1, r0, #%lo16(_DEV2_INTERRUPT_REG)
313        stw     r1, r0, #%lo16(_DEV3_INTERRUPT_REG)
314        stw     r1, r0, #%lo16(_DEV4_INTERRUPT_REG)
315        stw     r1, r0, #%lo16(_DEV5_INTERRUPT_REG)
316        stw     r1, r0, #%lo16(_DEV6_INTERRUPT_REG)
317        stw     r1, r0, #%lo16(_DEV7_INTERRUPT_REG)
318
319        ; Jump to the beginning of the application and enable interrupts.
320        jmp     _start
321        ei
322
323
324
325        ; Handler for the SI instruction. To perform a system call, the
326        ; C model uses a trapping mechanism which executes an SI instruction.
327        ; The Morpho Technologies simulator simply performs a branch to
328        ; this vector to simulate the SI instruction (this is as the hardware
329        ; behaves). In order to trigger the simulator that a system call
330        ; is needed, a write into the I/O register at address $40005 to
331        ; set bit #2 (0x4) is necessary.
332        ;
333        ; The above address has been changed to 0x31C and the bit number
334        ; is zero. (The manifest constants have been changed to reflect this.)
335        ;
336        .global _SOFTIVEC
337_SOFTIVEC:
338        ; Build a frame to save registers.
339        subi    sp, sp, #$8
340        stw     r9, sp, #$4
341        ldui    r9, #%hi16(SI_IOPORT_ADR)
342        stw     r10, sp, #$0
343        ori     r9, r9, #%lo16(SI_IOPORT_ADR)
344        ori     r10, r0, #SI_IOPORT_BIT
345        stw     r10, r9, #$0
346        ; SYS_call is handled by simulator here...
347        or      r0, r0, r0
348        ldw     r10, sp, #$0
349        or      r0, r0, r0
350        ldw     r9, sp, #$4
351        reti    r14
352        addi    sp, sp, #$8
353
354
355
356        .global _BRKIVEC
357_BRKIVEC:
358        ; Build a frame to save registers.
359        subi    sp, sp, #$8
360        stw     r9, sp, #$4
361        ldui    r9, #%hi16(BRK_IOPORT_ADR)
362        stw     r10, sp, #$0
363        ori     r9, r9, #%lo16(BRK_IOPORT_ADR)
364        ori     r10, r0, #BRK_IOPORT_BIT
365        stw     r10, r9, #$0
366        or      r0, r0, r0
367        ldw     r10, sp, #$0
368        subi    r15, r15, #$4           ; Backup to address of break
369        ldw     r9, sp, #$4
370        reti    r15
371        addi    sp, sp, #$8
372
373
374
375        .global _IVEC_DEFAULT
376_IVEC_DEFAULT:
377        reti    r15
378        or      r0, r0, r0
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