source: trunk/libs/newlib/src/libgloss/or1k/or1k_uart.c @ 444

Last change on this file since 444 was 444, checked in by satin@…, 6 years ago

add newlib,libalmos-mkh, restructure shared_syscalls.h and mini-libc

File size: 5.2 KB
Line 
1/* or1k_uart.c -- UART implementation for OpenRISC 1000.
2 *
3 *Copyright (c) 2014 Authors
4 *
5 * Contributor Stefan Wallentowitz <stefan.wallentowitz@tum.de>
6 * Contributor Olof Kindgren <olof.kindgren@gmail.com>
7 *
8 * The authors hereby grant permission to use, copy, modify, distribute,
9 * and license this software and its documentation for any purpose, provided
10 * that existing copyright notices are retained in all copies and that this
11 * notice is included verbatim in any distributions. No written agreement,
12 * license, or royalty fee is required for any of the authorized uses.
13 * Modifications to this software may be copyrighted by their authors
14 * and need not follow the licensing terms described here, provided that
15 * the new terms are clearly indicated on the first page of each file where
16 * they apply.
17 */
18
19#include "include/or1k-support.h"
20#include "or1k_uart.h"
21
22#include <stdint.h>
23
24// Register interface
25#define RB  _or1k_board_uart_base + 0 // Receiver Buffer (R)
26#define THR _or1k_board_uart_base + 0 // Transmitter Holding Register (W)
27#define IER _or1k_board_uart_base + 1 // Interrupt Enable Register (RW)
28#define IIR _or1k_board_uart_base + 2 // Interrupt Identification Register (R)
29#define FCR _or1k_board_uart_base + 2 // FIFO Control Register (W)
30#define LCR _or1k_board_uart_base + 3 // Line Control Register (RW)
31#define MCR _or1k_board_uart_base + 4 // Modem Control Register (W)
32#define LSR _or1k_board_uart_base + 5 // Line Status Register (R)
33#define MSR _or1k_board_uart_base + 6 // Modem Status Register (R)
34
35// Divisor Register (Accessed when DLAB bit in LCR is set)
36#define DLB1 _or1k_board_uart_base + 0 // Divisor Latch LSB (RW)
37#define DLB2 _or1k_board_uart_base + 1 // Divisor Latch MSB (RW)
38
39// Interrupt Enable Register bits
40#define IER_RDAI 0 // Receiver Data Available Interrupt
41#define IER_TEI  1 // Transmitter Holding Register Empty Interrupt
42#define IER_RLSI 2 // Receiver Line Status Interrupt
43#define IER_MSI  3 // Modem Status Interrupt
44
45// Interrupt Identification Register Values
46#define IIR_RLS  0xC6 // Receiver Line Status
47#define IIR_RDA  0xC4 // Receiver Data Available
48#define IIR_TO   0xCC // Timeout
49#define IIR_THRE 0xC2 // Transmitter Holding Register Empty
50#define IIT_MS   0xC0 // Modem Status
51
52// FIFO Control Register bits
53#define FCR_CLRRECV 0x1  // Clear receiver FIFO
54#define FCR_CLRTMIT 0x2  // Clear transmitter FIFO
55
56// FIFO Control Register bit 7-6 values
57#define FCR_TRIG_1  0x0  // Trigger level 1 byte
58#define FCR_TRIG_4  0x40 // Trigger level 4 bytes
59#define FCR_TRIG_8  0x80 // Trigger level 8 bytes
60#define FCR_TRIG_14 0xC0 // Trigger level 14 bytes
61
62// Line Control Reigster values and bits
63#define LCR_BPC_5 0x0  // 5 bits per character
64#define LCR_BPC_6 0x1  // 6 bits per character
65#define LCR_BPC_7 0x2  // 7 bits per character
66#define LCR_BPC_8 0x3  // 8 bits per character
67#define LCR_SB_1  0x0  // 1 stop bit
68#define LCR_SB_2  0x4  // 1.5 stop bits (LCR_BPC_5) or 2 stop bits (else)
69#define LCR_PE    0x8  // Parity Enabled
70#define LCR_EPS   0x10 // Even Parity Select
71#define LCR_SP    0x20 // Stick Parity
72#define LCR_BC    0x40 // Break Control
73#define LCR_DLA   0x80 // Divisor Latch Access
74
75// Line Status Register
76#define LSR_DR  0x0  // Data Ready
77#define LSR_OE  0x2  // Overrun Error
78#define LSR_PE  0x4  // Parity Error
79#define LSR_FE  0x8  // Framing Error
80#define LSR_BI  0x10 // Break Interrupt
81#define LSR_TFE 0x20 // Transmitter FIFO Empty
82#define LSR_TEI 0x40 // Transmitter Empty Indicator
83
84/**
85 * The registered callback function
86 */
87void (*_or1k_uart_read_cb)(char c);
88
89/**
90 * This is the interrupt handler that is registered for the callback
91 * function.
92 */
93void _or1k_uart_interrupt_handler(uint32_t data)
94{
95        uint8_t iir = REG8(IIR);
96
97        // Check if this is a read fifo or timeout interrupt, bit 0
98        // indicates pending interrupt and the other bits are IIR_RDA
99        // or IIR_TO
100        if (!(iir & 0x1) || ((iir & 0xfe) != IIR_RDA) ||
101            ((iir & 0xfe) != IIR_TO)) {
102                return;
103        }
104
105        // Read character and call callback function
106        _or1k_uart_read_cb(REG8(RB));
107}
108
109int _or1k_uart_init(void)
110{
111        uint16_t divisor;
112
113        // Is uart present?
114        if (!_or1k_board_uart_base) {
115                return -1;
116        }
117
118        // Reset the callback function
119        _or1k_uart_read_cb = 0;
120
121        // Calculate and set divisor
122        divisor = _or1k_board_clk_freq / (_or1k_board_uart_baud * 16);
123        REG8(LCR) = LCR_DLA;
124        REG8(DLB1) = divisor & 0xff;
125        REG8(DLB2) = divisor >> 8;
126
127        // Set line control register:
128        //  - 8 bits per character
129        //  - 1 stop bit
130        //  - No parity
131        //  - Break disabled
132        //  - Disallow access to divisor latch
133        REG8(LCR) = LCR_BPC_8;
134
135        // Reset FIFOs and set trigger level to 14 bytes
136        REG8(FCR) = FCR_CLRRECV | FCR_CLRTMIT | FCR_TRIG_14;
137
138        // Disable all interrupts
139        REG8(IER) = 0;
140
141        return 0;
142}
143
144void _or1k_uart_write(char c)
145{
146        // Wait until FIFO is empty
147        while (!(REG8(LSR) & LSR_TFE)) {}
148
149        // Write character to device
150        REG8(THR) = c;
151}
152
153void or1k_uart_set_read_cb(void (*cb)(char c))
154{
155        // Set callback function
156        _or1k_uart_read_cb = cb;
157
158        // Enable interrupt
159        REG8(IER) = 1 << IER_RDAI;
160
161        // Add the interrupt handler that calls the callback function
162        or1k_interrupt_handler_add(_or1k_board_uart_IRQ,
163                        _or1k_uart_interrupt_handler, 0);
164
165        // Enable UART interrupt
166        or1k_interrupt_enable(_or1k_board_uart_IRQ);
167}
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