1 | /* Copyright (c) 2012-2013, Linaro Limited |
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2 | All rights reserved. |
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3 | |
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4 | Redistribution and use in source and binary forms, with or without |
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5 | modification, are permitted provided that the following conditions are met: |
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6 | * Redistributions of source code must retain the above copyright |
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7 | notice, this list of conditions and the following disclaimer. |
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8 | * Redistributions in binary form must reproduce the above copyright |
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9 | notice, this list of conditions and the following disclaimer in the |
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10 | documentation and/or other materials provided with the distribution. |
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11 | * Neither the name of the Linaro nor the |
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12 | names of its contributors may be used to endorse or promote products |
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13 | derived from this software without specific prior written permission. |
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14 | |
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15 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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16 | "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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17 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
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18 | A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
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19 | HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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20 | SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
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21 | LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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22 | DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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23 | THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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24 | (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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25 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
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26 | |
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27 | /* |
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28 | * Copyright (c) 2015 ARM Ltd |
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29 | * All rights reserved. |
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30 | * |
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31 | * Redistribution and use in source and binary forms, with or without |
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32 | * modification, are permitted provided that the following conditions |
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33 | * are met: |
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34 | * 1. Redistributions of source code must retain the above copyright |
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35 | * notice, this list of conditions and the following disclaimer. |
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36 | * 2. Redistributions in binary form must reproduce the above copyright |
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37 | * notice, this list of conditions and the following disclaimer in the |
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38 | * documentation and/or other materials provided with the distribution. |
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39 | * 3. The name of the company may not be used to endorse or promote |
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40 | * products derived from this software without specific prior written |
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41 | * permission. |
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42 | * |
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43 | * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED |
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44 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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45 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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46 | * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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47 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED |
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48 | * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
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49 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
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50 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
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51 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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52 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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53 | */ |
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54 | |
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55 | /* Assumptions: |
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56 | * |
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57 | * ARMv8-a, AArch64, unaligned accesses |
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58 | * |
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59 | */ |
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60 | |
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61 | #if (defined (__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED)) |
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62 | /* See memset-stub.c */ |
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63 | #else |
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64 | |
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65 | #define dstin x0 |
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66 | #define val x1 |
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67 | #define valw w1 |
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68 | #define count x2 |
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69 | #define dst x3 |
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70 | #define dstend x4 |
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71 | #define tmp1 x5 |
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72 | #define tmp1w w5 |
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73 | #define tmp2 x6 |
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74 | #define tmp2w w6 |
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75 | #define zva_len x7 |
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76 | #define zva_lenw w7 |
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77 | |
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78 | #define L(l) .L ## l |
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79 | |
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80 | .macro def_fn f p2align=0 |
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81 | .text |
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82 | .p2align \p2align |
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83 | .global \f |
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84 | .type \f, %function |
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85 | \f: |
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86 | .endm |
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87 | |
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88 | def_fn memset p2align=6 |
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89 | |
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90 | dup v0.16B, valw |
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91 | add dstend, dstin, count |
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92 | |
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93 | cmp count, 96 |
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94 | b.hi L(set_long) |
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95 | cmp count, 16 |
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96 | b.hs L(set_medium) |
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97 | mov val, v0.D[0] |
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98 | |
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99 | /* Set 0..15 bytes. */ |
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100 | tbz count, 3, 1f |
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101 | str val, [dstin] |
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102 | str val, [dstend, -8] |
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103 | ret |
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104 | nop |
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105 | 1: tbz count, 2, 2f |
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106 | str valw, [dstin] |
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107 | str valw, [dstend, -4] |
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108 | ret |
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109 | 2: cbz count, 3f |
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110 | strb valw, [dstin] |
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111 | tbz count, 1, 3f |
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112 | strh valw, [dstend, -2] |
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113 | 3: ret |
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114 | |
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115 | /* Set 17..96 bytes. */ |
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116 | L(set_medium): |
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117 | str q0, [dstin] |
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118 | tbnz count, 6, L(set96) |
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119 | str q0, [dstend, -16] |
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120 | tbz count, 5, 1f |
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121 | str q0, [dstin, 16] |
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122 | str q0, [dstend, -32] |
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123 | 1: ret |
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124 | |
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125 | .p2align 4 |
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126 | /* Set 64..96 bytes. Write 64 bytes from the start and |
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127 | 32 bytes from the end. */ |
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128 | L(set96): |
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129 | str q0, [dstin, 16] |
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130 | stp q0, q0, [dstin, 32] |
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131 | stp q0, q0, [dstend, -32] |
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132 | ret |
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133 | |
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134 | .p2align 3 |
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135 | nop |
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136 | L(set_long): |
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137 | and valw, valw, 255 |
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138 | bic dst, dstin, 15 |
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139 | str q0, [dstin] |
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140 | cmp count, 256 |
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141 | ccmp valw, 0, 0, cs |
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142 | b.eq L(try_zva) |
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143 | L(no_zva): |
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144 | sub count, dstend, dst /* Count is 16 too large. */ |
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145 | add dst, dst, 16 |
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146 | sub count, count, 64 + 16 /* Adjust count and bias for loop. */ |
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147 | 1: stp q0, q0, [dst], 64 |
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148 | stp q0, q0, [dst, -32] |
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149 | L(tail64): |
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150 | subs count, count, 64 |
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151 | b.hi 1b |
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152 | 2: stp q0, q0, [dstend, -64] |
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153 | stp q0, q0, [dstend, -32] |
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154 | ret |
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155 | |
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156 | .p2align 3 |
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157 | L(try_zva): |
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158 | mrs tmp1, dczid_el0 |
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159 | tbnz tmp1w, 4, L(no_zva) |
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160 | and tmp1w, tmp1w, 15 |
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161 | cmp tmp1w, 4 /* ZVA size is 64 bytes. */ |
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162 | b.ne L(zva_128) |
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163 | |
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164 | /* Write the first and last 64 byte aligned block using stp rather |
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165 | than using DC ZVA. This is faster on some cores. |
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166 | */ |
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167 | L(zva_64): |
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168 | str q0, [dst, 16] |
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169 | stp q0, q0, [dst, 32] |
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170 | bic dst, dst, 63 |
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171 | stp q0, q0, [dst, 64] |
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172 | stp q0, q0, [dst, 96] |
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173 | sub count, dstend, dst /* Count is now 128 too large. */ |
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174 | sub count, count, 128+64+64 /* Adjust count and bias for loop. */ |
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175 | add dst, dst, 128 |
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176 | nop |
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177 | 1: dc zva, dst |
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178 | add dst, dst, 64 |
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179 | subs count, count, 64 |
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180 | b.hi 1b |
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181 | stp q0, q0, [dst, 0] |
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182 | stp q0, q0, [dst, 32] |
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183 | stp q0, q0, [dstend, -64] |
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184 | stp q0, q0, [dstend, -32] |
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185 | ret |
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186 | |
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187 | .p2align 3 |
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188 | L(zva_128): |
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189 | cmp tmp1w, 5 /* ZVA size is 128 bytes. */ |
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190 | b.ne L(zva_other) |
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191 | |
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192 | str q0, [dst, 16] |
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193 | stp q0, q0, [dst, 32] |
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194 | stp q0, q0, [dst, 64] |
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195 | stp q0, q0, [dst, 96] |
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196 | bic dst, dst, 127 |
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197 | sub count, dstend, dst /* Count is now 128 too large. */ |
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198 | sub count, count, 128+128 /* Adjust count and bias for loop. */ |
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199 | add dst, dst, 128 |
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200 | 1: dc zva, dst |
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201 | add dst, dst, 128 |
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202 | subs count, count, 128 |
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203 | b.hi 1b |
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204 | stp q0, q0, [dstend, -128] |
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205 | stp q0, q0, [dstend, -96] |
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206 | stp q0, q0, [dstend, -64] |
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207 | stp q0, q0, [dstend, -32] |
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208 | ret |
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209 | |
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210 | L(zva_other): |
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211 | mov tmp2w, 4 |
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212 | lsl zva_lenw, tmp2w, tmp1w |
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213 | add tmp1, zva_len, 64 /* Max alignment bytes written. */ |
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214 | cmp count, tmp1 |
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215 | blo L(no_zva) |
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216 | |
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217 | sub tmp2, zva_len, 1 |
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218 | add tmp1, dst, zva_len |
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219 | add dst, dst, 16 |
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220 | subs count, tmp1, dst /* Actual alignment bytes to write. */ |
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221 | bic tmp1, tmp1, tmp2 /* Aligned dc zva start address. */ |
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222 | beq 2f |
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223 | 1: stp q0, q0, [dst], 64 |
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224 | stp q0, q0, [dst, -32] |
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225 | subs count, count, 64 |
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226 | b.hi 1b |
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227 | 2: mov dst, tmp1 |
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228 | sub count, dstend, tmp1 /* Remaining bytes to write. */ |
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229 | subs count, count, zva_len |
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230 | b.lo 4f |
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231 | 3: dc zva, dst |
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232 | add dst, dst, zva_len |
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233 | subs count, count, zva_len |
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234 | b.hs 3b |
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235 | 4: add count, count, zva_len |
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236 | b L(tail64) |
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237 | |
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238 | .size memset, . - memset |
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239 | #endif |
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